ALSA: ASoC - Fix wrong section types
[deliverable/linux.git] / arch / arm / mach-s3c2410 / mach-vr1000.c
1 /* linux/arch/arm/mach-s3c2410/mach-vr1000.c
2 *
3 * Copyright (c) 2003-2005,2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Machine support for Thorcom VR1000 board. Designed for Thorcom by
7 * Simtec Electronics, http://www.simtec.co.uk/
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/interrupt.h>
18 #include <linux/list.h>
19 #include <linux/timer.h>
20 #include <linux/init.h>
21 #include <linux/dm9000.h>
22 #include <linux/i2c.h>
23
24 #include <linux/serial.h>
25 #include <linux/tty.h>
26 #include <linux/serial_8250.h>
27 #include <linux/serial_reg.h>
28 #include <linux/io.h>
29
30 #include <asm/mach/arch.h>
31 #include <asm/mach/map.h>
32 #include <asm/mach/irq.h>
33
34 #include <mach/bast-map.h>
35 #include <mach/vr1000-map.h>
36 #include <mach/vr1000-irq.h>
37 #include <mach/vr1000-cpld.h>
38
39 #include <mach/hardware.h>
40 #include <asm/irq.h>
41 #include <asm/mach-types.h>
42
43 #include <plat/regs-serial.h>
44 #include <mach/regs-gpio.h>
45 #include <mach/leds-gpio.h>
46
47 #include <plat/clock.h>
48 #include <plat/devs.h>
49 #include <plat/cpu.h>
50
51 #include "usb-simtec.h"
52 #include "nor-simtec.h"
53
54 /* macros for virtual address mods for the io space entries */
55 #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
56 #define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
57 #define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
58 #define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
59
60 /* macros to modify the physical addresses for io space */
61
62 #define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
63 #define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
64 #define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
65 #define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
66
67 static struct map_desc vr1000_iodesc[] __initdata = {
68 /* ISA IO areas */
69 {
70 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
71 .pfn = PA_CS2(BAST_PA_ISAIO),
72 .length = SZ_16M,
73 .type = MT_DEVICE,
74 }, {
75 .virtual = (u32)S3C24XX_VA_ISA_WORD,
76 .pfn = PA_CS3(BAST_PA_ISAIO),
77 .length = SZ_16M,
78 .type = MT_DEVICE,
79 },
80
81 /* CPLD control registers, and external interrupt controls */
82 {
83 .virtual = (u32)VR1000_VA_CTRL1,
84 .pfn = __phys_to_pfn(VR1000_PA_CTRL1),
85 .length = SZ_1M,
86 .type = MT_DEVICE,
87 }, {
88 .virtual = (u32)VR1000_VA_CTRL2,
89 .pfn = __phys_to_pfn(VR1000_PA_CTRL2),
90 .length = SZ_1M,
91 .type = MT_DEVICE,
92 }, {
93 .virtual = (u32)VR1000_VA_CTRL3,
94 .pfn = __phys_to_pfn(VR1000_PA_CTRL3),
95 .length = SZ_1M,
96 .type = MT_DEVICE,
97 }, {
98 .virtual = (u32)VR1000_VA_CTRL4,
99 .pfn = __phys_to_pfn(VR1000_PA_CTRL4),
100 .length = SZ_1M,
101 .type = MT_DEVICE,
102 },
103 };
104
105 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
106 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
107 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
108
109 /* uart clock source(s) */
110
111 static struct s3c24xx_uart_clksrc vr1000_serial_clocks[] = {
112 [0] = {
113 .name = "uclk",
114 .divisor = 1,
115 .min_baud = 0,
116 .max_baud = 0,
117 },
118 [1] = {
119 .name = "pclk",
120 .divisor = 1,
121 .min_baud = 0,
122 .max_baud = 0.
123 }
124 };
125
126 static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = {
127 [0] = {
128 .hwport = 0,
129 .flags = 0,
130 .ucon = UCON,
131 .ulcon = ULCON,
132 .ufcon = UFCON,
133 .clocks = vr1000_serial_clocks,
134 .clocks_size = ARRAY_SIZE(vr1000_serial_clocks),
135 },
136 [1] = {
137 .hwport = 1,
138 .flags = 0,
139 .ucon = UCON,
140 .ulcon = ULCON,
141 .ufcon = UFCON,
142 .clocks = vr1000_serial_clocks,
143 .clocks_size = ARRAY_SIZE(vr1000_serial_clocks),
144 },
145 /* port 2 is not actually used */
146 [2] = {
147 .hwport = 2,
148 .flags = 0,
149 .ucon = UCON,
150 .ulcon = ULCON,
151 .ufcon = UFCON,
152 .clocks = vr1000_serial_clocks,
153 .clocks_size = ARRAY_SIZE(vr1000_serial_clocks),
154
155 }
156 };
157
158 /* definitions for the vr1000 extra 16550 serial ports */
159
160 #define VR1000_BAUDBASE (3692307)
161
162 #define VR1000_SERIAL_MAPBASE(x) (VR1000_PA_SERIAL + 0x80 + ((x) << 5))
163
164 static struct plat_serial8250_port serial_platform_data[] = {
165 [0] = {
166 .mapbase = VR1000_SERIAL_MAPBASE(0),
167 .irq = IRQ_VR1000_SERIAL + 0,
168 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
169 .iotype = UPIO_MEM,
170 .regshift = 0,
171 .uartclk = VR1000_BAUDBASE,
172 },
173 [1] = {
174 .mapbase = VR1000_SERIAL_MAPBASE(1),
175 .irq = IRQ_VR1000_SERIAL + 1,
176 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
177 .iotype = UPIO_MEM,
178 .regshift = 0,
179 .uartclk = VR1000_BAUDBASE,
180 },
181 [2] = {
182 .mapbase = VR1000_SERIAL_MAPBASE(2),
183 .irq = IRQ_VR1000_SERIAL + 2,
184 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
185 .iotype = UPIO_MEM,
186 .regshift = 0,
187 .uartclk = VR1000_BAUDBASE,
188 },
189 [3] = {
190 .mapbase = VR1000_SERIAL_MAPBASE(3),
191 .irq = IRQ_VR1000_SERIAL + 3,
192 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
193 .iotype = UPIO_MEM,
194 .regshift = 0,
195 .uartclk = VR1000_BAUDBASE,
196 },
197 { },
198 };
199
200 static struct platform_device serial_device = {
201 .name = "serial8250",
202 .id = PLAT8250_DEV_PLATFORM,
203 .dev = {
204 .platform_data = serial_platform_data,
205 },
206 };
207
208 /* DM9000 ethernet devices */
209
210 static struct resource vr1000_dm9k0_resource[] = {
211 [0] = {
212 .start = S3C2410_CS5 + VR1000_PA_DM9000,
213 .end = S3C2410_CS5 + VR1000_PA_DM9000 + 3,
214 .flags = IORESOURCE_MEM
215 },
216 [1] = {
217 .start = S3C2410_CS5 + VR1000_PA_DM9000 + 0x40,
218 .end = S3C2410_CS5 + VR1000_PA_DM9000 + 0x7f,
219 .flags = IORESOURCE_MEM
220 },
221 [2] = {
222 .start = IRQ_VR1000_DM9000A,
223 .end = IRQ_VR1000_DM9000A,
224 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
225 }
226
227 };
228
229 static struct resource vr1000_dm9k1_resource[] = {
230 [0] = {
231 .start = S3C2410_CS5 + VR1000_PA_DM9000 + 0x80,
232 .end = S3C2410_CS5 + VR1000_PA_DM9000 + 0x83,
233 .flags = IORESOURCE_MEM
234 },
235 [1] = {
236 .start = S3C2410_CS5 + VR1000_PA_DM9000 + 0xC0,
237 .end = S3C2410_CS5 + VR1000_PA_DM9000 + 0xFF,
238 .flags = IORESOURCE_MEM
239 },
240 [2] = {
241 .start = IRQ_VR1000_DM9000N,
242 .end = IRQ_VR1000_DM9000N,
243 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
244 }
245 };
246
247 /* for the moment we limit ourselves to 16bit IO until some
248 * better IO routines can be written and tested
249 */
250
251 static struct dm9000_plat_data vr1000_dm9k_platdata = {
252 .flags = DM9000_PLATF_16BITONLY,
253 };
254
255 static struct platform_device vr1000_dm9k0 = {
256 .name = "dm9000",
257 .id = 0,
258 .num_resources = ARRAY_SIZE(vr1000_dm9k0_resource),
259 .resource = vr1000_dm9k0_resource,
260 .dev = {
261 .platform_data = &vr1000_dm9k_platdata,
262 }
263 };
264
265 static struct platform_device vr1000_dm9k1 = {
266 .name = "dm9000",
267 .id = 1,
268 .num_resources = ARRAY_SIZE(vr1000_dm9k1_resource),
269 .resource = vr1000_dm9k1_resource,
270 .dev = {
271 .platform_data = &vr1000_dm9k_platdata,
272 }
273 };
274
275 /* LEDS */
276
277 static struct s3c24xx_led_platdata vr1000_led1_pdata = {
278 .name = "led1",
279 .gpio = S3C2410_GPB0,
280 .def_trigger = "",
281 };
282
283 static struct s3c24xx_led_platdata vr1000_led2_pdata = {
284 .name = "led2",
285 .gpio = S3C2410_GPB1,
286 .def_trigger = "",
287 };
288
289 static struct s3c24xx_led_platdata vr1000_led3_pdata = {
290 .name = "led3",
291 .gpio = S3C2410_GPB2,
292 .def_trigger = "",
293 };
294
295 static struct platform_device vr1000_led1 = {
296 .name = "s3c24xx_led",
297 .id = 1,
298 .dev = {
299 .platform_data = &vr1000_led1_pdata,
300 },
301 };
302
303 static struct platform_device vr1000_led2 = {
304 .name = "s3c24xx_led",
305 .id = 2,
306 .dev = {
307 .platform_data = &vr1000_led2_pdata,
308 },
309 };
310
311 static struct platform_device vr1000_led3 = {
312 .name = "s3c24xx_led",
313 .id = 3,
314 .dev = {
315 .platform_data = &vr1000_led3_pdata,
316 },
317 };
318
319 /* I2C devices. */
320
321 static struct i2c_board_info vr1000_i2c_devs[] __initdata = {
322 {
323 I2C_BOARD_INFO("tlv320aic23", 0x1a),
324 }, {
325 I2C_BOARD_INFO("tmp101", 0x48),
326 }, {
327 I2C_BOARD_INFO("m41st87", 0x68),
328 },
329 };
330
331 /* devices for this board */
332
333 static struct platform_device *vr1000_devices[] __initdata = {
334 &s3c_device_usb,
335 &s3c_device_lcd,
336 &s3c_device_wdt,
337 &s3c_device_i2c,
338 &s3c_device_adc,
339 &serial_device,
340 &vr1000_dm9k0,
341 &vr1000_dm9k1,
342 &vr1000_led1,
343 &vr1000_led2,
344 &vr1000_led3,
345 };
346
347 static struct clk *vr1000_clocks[] __initdata = {
348 &s3c24xx_dclk0,
349 &s3c24xx_dclk1,
350 &s3c24xx_clkout0,
351 &s3c24xx_clkout1,
352 &s3c24xx_uclk,
353 };
354
355 static void vr1000_power_off(void)
356 {
357 s3c2410_gpio_cfgpin(S3C2410_GPB9, S3C2410_GPB9_OUTP);
358 s3c2410_gpio_setpin(S3C2410_GPB9, 1);
359 }
360
361 static void __init vr1000_map_io(void)
362 {
363 /* initialise clock sources */
364
365 s3c24xx_dclk0.parent = &clk_upll;
366 s3c24xx_dclk0.rate = 12*1000*1000;
367
368 s3c24xx_dclk1.parent = NULL;
369 s3c24xx_dclk1.rate = 3692307;
370
371 s3c24xx_clkout0.parent = &s3c24xx_dclk0;
372 s3c24xx_clkout1.parent = &s3c24xx_dclk1;
373
374 s3c24xx_uclk.parent = &s3c24xx_clkout1;
375
376 s3c24xx_register_clocks(vr1000_clocks, ARRAY_SIZE(vr1000_clocks));
377
378 pm_power_off = vr1000_power_off;
379
380 s3c24xx_init_io(vr1000_iodesc, ARRAY_SIZE(vr1000_iodesc));
381 s3c24xx_init_clocks(0);
382 s3c24xx_init_uarts(vr1000_uartcfgs, ARRAY_SIZE(vr1000_uartcfgs));
383 }
384
385 static void __init vr1000_init(void)
386 {
387 platform_add_devices(vr1000_devices, ARRAY_SIZE(vr1000_devices));
388
389 i2c_register_board_info(0, vr1000_i2c_devs,
390 ARRAY_SIZE(vr1000_i2c_devs));
391
392 nor_simtec_init();
393 }
394
395 MACHINE_START(VR1000, "Thorcom-VR1000")
396 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
397 .phys_io = S3C2410_PA_UART,
398 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
399 .boot_params = S3C2410_SDRAM_PA + 0x100,
400 .map_io = vr1000_map_io,
401 .init_machine = vr1000_init,
402 .init_irq = s3c24xx_init_irq,
403 .timer = &s3c24xx_timer,
404 MACHINE_END
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