arch/arm/mach-s3c2416/clock.c

   1 /* linux/arch/arm/mach-s3c2416/clock.c
   2  *
   3  * Copyright (c) 2010 Simtec Electronics
   4  * Copyright (c) 2010 Ben Dooks <ben-linux@fluff.org>
   5  *
   6  * S3C2416 Clock control support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/init.h>
  15 #include <linux/clk.h>
  16
  17 #include <plat/s3c2416.h>
  18 #include <plat/clock.h>
  19 #include <plat/clock-clksrc.h>
  20 #include <plat/cpu.h>
  21
  22 #include <plat/cpu-freq.h>
  23 #include <plat/pll.h>
  24
  25 #include <asm/mach/map.h>
  26
  27 #include <mach/regs-clock.h>
  28 #include <mach/regs-s3c2443-clock.h>
  29
  30 /* armdiv
  31  *
  32  * this clock is sourced from msysclk and can have a number of
  33  * divider values applied to it to then be fed into armclk.
  34  * The real clock definition is done in s3c2443-clock.c,
  35  * only the armdiv divisor table must be defined here.
  36 */
  37
  38 static unsigned int armdiv[8] = {
  39         [0] = 1,
  40         [1] = 2,
  41         [2] = 3,
  42         [3] = 4,
  43         [5] = 6,
  44         [7] = 8,
  45 };
  46
  47 static struct clksrc_clk hsspi_eplldiv = {
  48         .clk = {
  49                 .name   = "hsspi-eplldiv",
  50                 .parent = &clk_esysclk.clk,
  51                 .ctrlbit = (1 << 14),
  52                 .enable = s3c2443_clkcon_enable_s,
  53         },
  54         .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 24 },
  55 };
  56
  57 static struct clk *hsspi_sources[] = {
  58         [0] = &hsspi_eplldiv.clk,
  59         [1] = NULL, /* to fix */
  60 };
  61
  62 static struct clksrc_clk hsspi_mux = {
  63         .clk    = {
  64                 .name   = "hsspi-if",
  65         },
  66         .sources = &(struct clksrc_sources) {
  67                 .sources = hsspi_sources,
  68                 .nr_sources = ARRAY_SIZE(hsspi_sources),
  69         },
  70         .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 18 },
  71 };
  72
  73 static struct clksrc_clk hsmmc_div[] = {
  74         [0] = {
  75                 .clk = {
  76                         .name   = "hsmmc-div",
  77                         .devname        = "s3c-sdhci.0",
  78                         .parent = &clk_esysclk.clk,
  79                 },
  80                 .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
  81         },
  82         [1] = {
  83                 .clk = {
  84                         .name   = "hsmmc-div",
  85                         .devname        = "s3c-sdhci.1",
  86                         .parent = &clk_esysclk.clk,
  87                 },
  88                 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
  89         },
  90 };
  91
  92 static struct clksrc_clk hsmmc_mux0 = {
  93         .clk    = {
  94                 .name           = "hsmmc-if",
  95                 .devname        = "s3c-sdhci.0",
  96                 .ctrlbit        = (1 << 6),
  97                 .enable         = s3c2443_clkcon_enable_s,
  98         },
  99         .sources        = &(struct clksrc_sources) {
 100                 .nr_sources     = 2,
 101                 .sources        = (struct clk * []) {
 102                         [0]     = &hsmmc_div[0].clk,
 103                         [1]     = NULL, /* to fix */
 104                 },
 105         },
 106         .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
 107 };
 108
 109 static struct clksrc_clk hsmmc_mux1 = {
 110         .clk    = {
 111                 .name           = "hsmmc-if",
 112                 .devname        = "s3c-sdhci.1",
 113                 .ctrlbit        = (1 << 12),
 114                 .enable         = s3c2443_clkcon_enable_s,
 115         },
 116         .sources        = &(struct clksrc_sources) {
 117                 .nr_sources     = 2,
 118                 .sources        = (struct clk * []) {
 119                         [0]     = &hsmmc_div[1].clk,
 120                         [1]     = NULL, /* to fix */
 121                 },
 122         },
 123         .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
 124 };
 125
 126 static struct clk hsmmc0_clk = {
 127         .name           = "hsmmc",
 128         .devname        = "s3c-sdhci.0",
 129         .parent         = &clk_h,
 130         .enable         = s3c2443_clkcon_enable_h,
 131         .ctrlbit        = S3C2416_HCLKCON_HSMMC0,
 132 };
 133
 134 void __init_or_cpufreq s3c2416_setup_clocks(void)
 135 {
 136         s3c2443_common_setup_clocks(s3c2416_get_pll);
 137 }
 138
 139
 140 static struct clksrc_clk *clksrcs[] __initdata = {
 141         &hsspi_eplldiv,
 142         &hsspi_mux,
 143         &hsmmc_div[0],
 144         &hsmmc_div[1],
 145         &hsmmc_mux0,
 146         &hsmmc_mux1,
 147 };
 148
 149 static struct clk_lookup s3c2416_clk_lookup[] = {
 150         CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk),
 151         CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk),
 152         CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk),
 153 };
 154
 155 void __init s3c2416_init_clocks(int xtal)
 156 {
 157         u32 epllcon = __raw_readl(S3C2443_EPLLCON);
 158         u32 epllcon1 = __raw_readl(S3C2443_EPLLCON+4);
 159         int ptr;
 160
 161         /* s3c2416 EPLL compatible with s3c64xx */
 162         clk_epll.rate = s3c_get_pll6553x(xtal, epllcon, epllcon1);
 163
 164         clk_epll.parent = &clk_epllref.clk;
 165
 166         s3c2443_common_init_clocks(xtal, s3c2416_get_pll,
 167                                    armdiv, ARRAY_SIZE(armdiv),
 168                                    S3C2416_CLKDIV0_ARMDIV_MASK);
 169
 170         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
 171                 s3c_register_clksrc(clksrcs[ptr], 1);
 172
 173         s3c24xx_register_clock(&hsmmc0_clk);
 174         clkdev_add_table(s3c2416_clk_lookup, ARRAY_SIZE(s3c2416_clk_lookup));
 175
 176         s3c_pwmclk_init();
 177
 178 }