arch/arm/mach-s3c2440/mach-osiris.c

   1 /* linux/arch/arm/mach-s3c2440/mach-osiris.c
   2  *
   3  * Copyright (c) 2005 Simtec Electronics
   4  *      http://armlinux.simtec.co.uk/
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/types.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/list.h>
  16 #include <linux/timer.h>
  17 #include <linux/init.h>
  18 #include <linux/device.h>
  19 #include <linux/sysdev.h>
  20 #include <linux/serial_core.h>
  21
  22 #include <asm/mach/arch.h>
  23 #include <asm/mach/map.h>
  24 #include <asm/mach/irq.h>
  25
  26 #include <asm/arch/osiris-map.h>
  27 #include <asm/arch/osiris-cpld.h>
  28
  29 #include <asm/hardware.h>
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <asm/mach-types.h>
  33
  34 #include <asm/arch/regs-serial.h>
  35 #include <asm/arch/regs-gpio.h>
  36 #include <asm/arch/regs-mem.h>
  37 #include <asm/arch/regs-lcd.h>
  38 #include <asm/arch/nand.h>
  39
  40 #include <linux/mtd/mtd.h>
  41 #include <linux/mtd/nand.h>
  42 #include <linux/mtd/nand_ecc.h>
  43 #include <linux/mtd/partitions.h>
  44
  45 #include <asm/plat-s3c24xx/clock.h>
  46 #include <asm/plat-s3c24xx/devs.h>
  47 #include <asm/plat-s3c24xx/cpu.h>
  48
  49 /* onboard perihperal map */
  50
  51 static struct map_desc osiris_iodesc[] __initdata = {
  52   /* ISA IO areas (may be over-written later) */
  53
  54   {
  55           .virtual      = (u32)S3C24XX_VA_ISA_BYTE,
  56           .pfn          = __phys_to_pfn(S3C2410_CS5),
  57           .length       = SZ_16M,
  58           .type         = MT_DEVICE,
  59   }, {
  60           .virtual      = (u32)S3C24XX_VA_ISA_WORD,
  61           .pfn          = __phys_to_pfn(S3C2410_CS5),
  62           .length       = SZ_16M,
  63           .type         = MT_DEVICE,
  64   },
  65
  66   /* CPLD control registers */
  67
  68   {
  69           .virtual      = (u32)OSIRIS_VA_CTRL0,
  70           .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL0),
  71           .length       = SZ_16K,
  72           .type         = MT_DEVICE,
  73   }, {
  74           .virtual      = (u32)OSIRIS_VA_CTRL1,
  75           .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL1),
  76           .length       = SZ_16K,
  77           .type         = MT_DEVICE,
  78   }, {
  79           .virtual      = (u32)OSIRIS_VA_CTRL2,
  80           .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL2),
  81           .length       = SZ_16K,
  82           .type         = MT_DEVICE,
  83   }, {
  84           .virtual      = (u32)OSIRIS_VA_IDREG,
  85           .pfn          = __phys_to_pfn(OSIRIS_PA_IDREG),
  86           .length       = SZ_16K,
  87           .type         = MT_DEVICE,
  88   },
  89 };
  90
  91 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
  92 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
  93 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
  94
  95 static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = {
  96         [0] = {
  97                 .name           = "uclk",
  98                 .divisor        = 1,
  99                 .min_baud       = 0,
 100                 .max_baud       = 0,
 101         },
 102         [1] = {
 103                 .name           = "pclk",
 104                 .divisor        = 1,
 105                 .min_baud       = 0,
 106                 .max_baud       = 0,
 107         }
 108 };
 109
 110 static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
 111         [0] = {
 112                 .hwport      = 0,
 113                 .flags       = 0,
 114                 .ucon        = UCON,
 115                 .ulcon       = ULCON,
 116                 .ufcon       = UFCON,
 117                 .clocks      = osiris_serial_clocks,
 118                 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
 119         },
 120         [1] = {
 121                 .hwport      = 1,
 122                 .flags       = 0,
 123                 .ucon        = UCON,
 124                 .ulcon       = ULCON,
 125                 .ufcon       = UFCON,
 126                 .clocks      = osiris_serial_clocks,
 127                 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
 128         },
 129         [2] = {
 130                 .hwport      = 2,
 131                 .flags       = 0,
 132                 .ucon        = UCON,
 133                 .ulcon       = ULCON,
 134                 .ufcon       = UFCON,
 135                 .clocks      = osiris_serial_clocks,
 136                 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
 137         }
 138 };
 139
 140 /* NAND Flash on Osiris board */
 141
 142 static int external_map[]   = { 2 };
 143 static int chip0_map[]      = { 0 };
 144 static int chip1_map[]      = { 1 };
 145
 146 static struct mtd_partition osiris_default_nand_part[] = {
 147         [0] = {
 148                 .name   = "Boot Agent",
 149                 .size   = SZ_16K,
 150                 .offset = 0,
 151         },
 152         [1] = {
 153                 .name   = "/boot",
 154                 .size   = SZ_4M - SZ_16K,
 155                 .offset = SZ_16K,
 156         },
 157         [2] = {
 158                 .name   = "user1",
 159                 .offset = SZ_4M,
 160                 .size   = SZ_32M - SZ_4M,
 161         },
 162         [3] = {
 163                 .name   = "user2",
 164                 .offset = SZ_32M,
 165                 .size   = MTDPART_SIZ_FULL,
 166         }
 167 };
 168
 169 /* the Osiris has 3 selectable slots for nand-flash, the two
 170  * on-board chip areas, as well as the external slot.
 171  *
 172  * Note, there is no current hot-plug support for the External
 173  * socket.
 174 */
 175
 176 static struct s3c2410_nand_set osiris_nand_sets[] = {
 177         [1] = {
 178                 .name           = "External",
 179                 .nr_chips       = 1,
 180                 .nr_map         = external_map,
 181                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
 182                 .partitions     = osiris_default_nand_part,
 183         },
 184         [0] = {
 185                 .name           = "chip0",
 186                 .nr_chips       = 1,
 187                 .nr_map         = chip0_map,
 188                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
 189                 .partitions     = osiris_default_nand_part,
 190         },
 191         [2] = {
 192                 .name           = "chip1",
 193                 .nr_chips       = 1,
 194                 .nr_map         = chip1_map,
 195                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
 196                 .partitions     = osiris_default_nand_part,
 197         },
 198 };
 199
 200 static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
 201 {
 202         unsigned int tmp;
 203
 204         slot = set->nr_map[slot] & 3;
 205
 206         pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
 207                  slot, set, set->nr_map);
 208
 209         tmp = __raw_readb(OSIRIS_VA_CTRL0);
 210         tmp &= ~OSIRIS_CTRL0_NANDSEL;
 211         tmp |= slot;
 212
 213         pr_debug("osiris_nand: ctrl0 now %02x\n", tmp);
 214
 215         __raw_writeb(tmp, OSIRIS_VA_CTRL0);
 216 }
 217
 218 static struct s3c2410_platform_nand osiris_nand_info = {
 219         .tacls          = 25,
 220         .twrph0         = 60,
 221         .twrph1         = 60,
 222         .nr_sets        = ARRAY_SIZE(osiris_nand_sets),
 223         .sets           = osiris_nand_sets,
 224         .select_chip    = osiris_nand_select,
 225 };
 226
 227 /* PCMCIA control and configuration */
 228
 229 static struct resource osiris_pcmcia_resource[] = {
 230         [0] = {
 231                 .start  = 0x0f000000,
 232                 .end    = 0x0f100000,
 233                 .flags  = IORESOURCE_MEM,
 234         },
 235         [1] = {
 236                 .start  = 0x0c000000,
 237                 .end    = 0x0c100000,
 238                 .flags  = IORESOURCE_MEM,
 239         }
 240 };
 241
 242 static struct platform_device osiris_pcmcia = {
 243         .name           = "osiris-pcmcia",
 244         .id             = -1,
 245         .num_resources  = ARRAY_SIZE(osiris_pcmcia_resource),
 246         .resource       = osiris_pcmcia_resource,
 247 };
 248
 249 /* Osiris power management device */
 250
 251 #ifdef CONFIG_PM
 252 static unsigned char pm_osiris_ctrl0;
 253
 254 static int osiris_pm_suspend(struct sys_device *sd, pm_message_t state)
 255 {
 256         pm_osiris_ctrl0 = __raw_readb(OSIRIS_VA_CTRL0);
 257         return 0;
 258 }
 259
 260 static int osiris_pm_resume(struct sys_device *sd)
 261 {
 262         if (pm_osiris_ctrl0 & OSIRIS_CTRL0_FIX8)
 263                 __raw_writeb(OSIRIS_CTRL1_FIX8, OSIRIS_VA_CTRL1);
 264
 265         return 0;
 266 }
 267
 268 #else
 269 #define osiris_pm_suspend NULL
 270 #define osiris_pm_resume NULL
 271 #endif
 272
 273 static struct sysdev_class osiris_pm_sysclass = {
 274         set_kset_name("mach-osiris"),
 275         .suspend        = osiris_pm_suspend,
 276         .resume         = osiris_pm_resume,
 277 };
 278
 279 static struct sys_device osiris_pm_sysdev = {
 280         .cls            = &osiris_pm_sysclass,
 281 };
 282
 283 /* Standard Osiris devices */
 284
 285 static struct platform_device *osiris_devices[] __initdata = {
 286         &s3c_device_i2c,
 287         &s3c_device_wdt,
 288         &s3c_device_nand,
 289         &osiris_pcmcia,
 290 };
 291
 292 static struct clk *osiris_clocks[] = {
 293         &s3c24xx_dclk0,
 294         &s3c24xx_dclk1,
 295         &s3c24xx_clkout0,
 296         &s3c24xx_clkout1,
 297         &s3c24xx_uclk,
 298 };
 299
 300 static void __init osiris_map_io(void)
 301 {
 302         unsigned long flags;
 303
 304         /* initialise the clocks */
 305
 306         s3c24xx_dclk0.parent = NULL;
 307         s3c24xx_dclk0.rate   = 12*1000*1000;
 308
 309         s3c24xx_dclk1.parent = NULL;
 310         s3c24xx_dclk1.rate   = 24*1000*1000;
 311
 312         s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
 313         s3c24xx_clkout1.parent  = &s3c24xx_dclk1;
 314
 315         s3c24xx_uclk.parent  = &s3c24xx_clkout1;
 316
 317         s3c24xx_register_clocks(osiris_clocks, ARRAY_SIZE(osiris_clocks));
 318
 319         s3c_device_nand.dev.platform_data = &osiris_nand_info;
 320
 321         s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
 322         s3c24xx_init_clocks(0);
 323         s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
 324
 325         /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
 326
 327         local_irq_save(flags);
 328         __raw_writel(__raw_readl(S3C2410_BWSCON) | S3C2410_BWSCON_ST1 | S3C2410_BWSCON_ST2 | S3C2410_BWSCON_ST3 | S3C2410_BWSCON_ST4 | S3C2410_BWSCON_ST5, S3C2410_BWSCON);
 329         local_irq_restore(flags);
 330
 331         /* write-protect line to the NAND */
 332         s3c2410_gpio_setpin(S3C2410_GPA0, 1);
 333 }
 334
 335 static void __init osiris_init(void)
 336 {
 337         sysdev_class_register(&osiris_pm_sysclass);
 338         sysdev_register(&osiris_pm_sysdev);
 339
 340         platform_add_devices(osiris_devices, ARRAY_SIZE(osiris_devices));
 341 };
 342
 343 MACHINE_START(OSIRIS, "Simtec-OSIRIS")
 344         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
 345         .phys_io        = S3C2410_PA_UART,
 346         .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
 347         .boot_params    = S3C2410_SDRAM_PA + 0x100,
 348         .map_io         = osiris_map_io,
 349         .init_machine   = osiris_init,
 350         .init_irq       = s3c24xx_init_irq,
 351         .init_machine   = osiris_init,
 352         .timer          = &s3c24xx_timer,
 353 MACHINE_END