arch/arm/mach-s3c24xx/common.c

   1 /* linux/arch/arm/plat-s3c24xx/cpu.c
   2  *
   3  * Copyright (c) 2004-2005 Simtec Electronics
   4  *      http://www.simtec.co.uk/products/SWLINUX/
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *
   7  * Common code for S3C24XX machines
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  22 */
  23
  24
  25 #include <linux/init.h>
  26 #include <linux/module.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/ioport.h>
  29 #include <linux/serial_core.h>
  30 #include <linux/serial_s3c.h>
  31 #include <clocksource/samsung_pwm.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/delay.h>
  34 #include <linux/io.h>
  35 #include <linux/platform_data/dma-s3c24xx.h>
  36
  37 #include <mach/hardware.h>
  38 #include <mach/regs-clock.h>
  39 #include <asm/irq.h>
  40 #include <asm/cacheflush.h>
  41 #include <asm/system_info.h>
  42 #include <asm/system_misc.h>
  43
  44 #include <asm/mach/arch.h>
  45 #include <asm/mach/map.h>
  46
  47 #include <mach/regs-gpio.h>
  48 #include <mach/dma.h>
  49
  50 #include <plat/cpu.h>
  51 #include <plat/devs.h>
  52 #include <plat/clock.h>
  53 #include <plat/cpu-freq.h>
  54 #include <plat/pll.h>
  55 #include <plat/pwm-core.h>
  56
  57 #include "common.h"
  58
  59 /* table of supported CPUs */
  60
  61 static const char name_s3c2410[]  = "S3C2410";
  62 static const char name_s3c2412[]  = "S3C2412";
  63 static const char name_s3c2416[]  = "S3C2416/S3C2450";
  64 static const char name_s3c2440[]  = "S3C2440";
  65 static const char name_s3c2442[]  = "S3C2442";
  66 static const char name_s3c2442b[]  = "S3C2442B";
  67 static const char name_s3c2443[]  = "S3C2443";
  68 static const char name_s3c2410a[] = "S3C2410A";
  69 static const char name_s3c2440a[] = "S3C2440A";
  70
  71 static struct cpu_table cpu_ids[] __initdata = {
  72         {
  73                 .idcode         = 0x32410000,
  74                 .idmask         = 0xffffffff,
  75                 .map_io         = s3c2410_map_io,
  76                 .init_clocks    = s3c2410_init_clocks,
  77                 .init_uarts     = s3c2410_init_uarts,
  78                 .init           = s3c2410_init,
  79                 .name           = name_s3c2410
  80         },
  81         {
  82                 .idcode         = 0x32410002,
  83                 .idmask         = 0xffffffff,
  84                 .map_io         = s3c2410_map_io,
  85                 .init_clocks    = s3c2410_init_clocks,
  86                 .init_uarts     = s3c2410_init_uarts,
  87                 .init           = s3c2410a_init,
  88                 .name           = name_s3c2410a
  89         },
  90         {
  91                 .idcode         = 0x32440000,
  92                 .idmask         = 0xffffffff,
  93                 .map_io         = s3c2440_map_io,
  94                 .init_clocks    = s3c244x_init_clocks,
  95                 .init_uarts     = s3c244x_init_uarts,
  96                 .init           = s3c2440_init,
  97                 .name           = name_s3c2440
  98         },
  99         {
 100                 .idcode         = 0x32440001,
 101                 .idmask         = 0xffffffff,
 102                 .map_io         = s3c2440_map_io,
 103                 .init_clocks    = s3c244x_init_clocks,
 104                 .init_uarts     = s3c244x_init_uarts,
 105                 .init           = s3c2440_init,
 106                 .name           = name_s3c2440a
 107         },
 108         {
 109                 .idcode         = 0x32440aaa,
 110                 .idmask         = 0xffffffff,
 111                 .map_io         = s3c2442_map_io,
 112                 .init_clocks    = s3c244x_init_clocks,
 113                 .init_uarts     = s3c244x_init_uarts,
 114                 .init           = s3c2442_init,
 115                 .name           = name_s3c2442
 116         },
 117         {
 118                 .idcode         = 0x32440aab,
 119                 .idmask         = 0xffffffff,
 120                 .map_io         = s3c2442_map_io,
 121                 .init_clocks    = s3c244x_init_clocks,
 122                 .init_uarts     = s3c244x_init_uarts,
 123                 .init           = s3c2442_init,
 124                 .name           = name_s3c2442b
 125         },
 126         {
 127                 .idcode         = 0x32412001,
 128                 .idmask         = 0xffffffff,
 129                 .map_io         = s3c2412_map_io,
 130                 .init_clocks    = s3c2412_init_clocks,
 131                 .init_uarts     = s3c2412_init_uarts,
 132                 .init           = s3c2412_init,
 133                 .name           = name_s3c2412,
 134         },
 135         {                       /* a newer version of the s3c2412 */
 136                 .idcode         = 0x32412003,
 137                 .idmask         = 0xffffffff,
 138                 .map_io         = s3c2412_map_io,
 139                 .init_clocks    = s3c2412_init_clocks,
 140                 .init_uarts     = s3c2412_init_uarts,
 141                 .init           = s3c2412_init,
 142                 .name           = name_s3c2412,
 143         },
 144         {                       /* a strange version of the s3c2416 */
 145                 .idcode         = 0x32450003,
 146                 .idmask         = 0xffffffff,
 147                 .map_io         = s3c2416_map_io,
 148                 .init_clocks    = s3c2416_init_clocks,
 149                 .init_uarts     = s3c2416_init_uarts,
 150                 .init           = s3c2416_init,
 151                 .name           = name_s3c2416,
 152         },
 153         {
 154                 .idcode         = 0x32443001,
 155                 .idmask         = 0xffffffff,
 156                 .map_io         = s3c2443_map_io,
 157                 .init_clocks    = s3c2443_init_clocks,
 158                 .init_uarts     = s3c2443_init_uarts,
 159                 .init           = s3c2443_init,
 160                 .name           = name_s3c2443,
 161         },
 162 };
 163
 164 /* minimal IO mapping */
 165
 166 static struct map_desc s3c_iodesc[] __initdata = {
 167         IODESC_ENT(GPIO),
 168         IODESC_ENT(IRQ),
 169         IODESC_ENT(MEMCTRL),
 170         IODESC_ENT(UART)
 171 };
 172
 173 /* read cpu identificaiton code */
 174
 175 static unsigned long s3c24xx_read_idcode_v5(void)
 176 {
 177 #if defined(CONFIG_CPU_S3C2416)
 178         /* s3c2416 is v5, with S3C24XX_GSTATUS1 instead of S3C2412_GSTATUS1 */
 179
 180         u32 gs = __raw_readl(S3C24XX_GSTATUS1);
 181
 182         /* test for s3c2416 or similar device */
 183         if ((gs >> 16) == 0x3245)
 184                 return gs;
 185 #endif
 186
 187 #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
 188         return __raw_readl(S3C2412_GSTATUS1);
 189 #else
 190         return 1UL;     /* don't look like an 2400 */
 191 #endif
 192 }
 193
 194 static unsigned long s3c24xx_read_idcode_v4(void)
 195 {
 196         return __raw_readl(S3C2410_GSTATUS1);
 197 }
 198
 199 static void s3c24xx_default_idle(void)
 200 {
 201         unsigned long tmp = 0;
 202         int i;
 203
 204         /* idle the system by using the idle mode which will wait for an
 205          * interrupt to happen before restarting the system.
 206          */
 207
 208         /* Warning: going into idle state upsets jtag scanning */
 209
 210         __raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE,
 211                      S3C2410_CLKCON);
 212
 213         /* the samsung port seems to do a loop and then unset idle.. */
 214         for (i = 0; i < 50; i++)
 215                 tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */
 216
 217         /* this bit is not cleared on re-start... */
 218
 219         __raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE,
 220                      S3C2410_CLKCON);
 221 }
 222
 223 static struct samsung_pwm_variant s3c24xx_pwm_variant = {
 224         .bits           = 16,
 225         .div_base       = 1,
 226         .has_tint_cstat = false,
 227         .tclk_mask      = (1 << 4),
 228 };
 229
 230 void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
 231 {
 232         arm_pm_idle = s3c24xx_default_idle;
 233
 234         /* initialise the io descriptors we need for initialisation */
 235         iotable_init(mach_desc, size);
 236         iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
 237
 238         if (cpu_architecture() >= CPU_ARCH_ARMv5) {
 239                 samsung_cpu_id = s3c24xx_read_idcode_v5();
 240         } else {
 241                 samsung_cpu_id = s3c24xx_read_idcode_v4();
 242         }
 243
 244         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 245
 246         samsung_pwm_set_platdata(&s3c24xx_pwm_variant);
 247 }
 248
 249 void __init samsung_set_timer_source(unsigned int event, unsigned int source)
 250 {
 251         s3c24xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
 252         s3c24xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
 253 }
 254
 255 void __init samsung_timer_init(void)
 256 {
 257         unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
 258                 IRQ_TIMER0, IRQ_TIMER1, IRQ_TIMER2, IRQ_TIMER3, IRQ_TIMER4,
 259         };
 260
 261         samsung_pwm_clocksource_init(S3C_VA_TIMER,
 262                                         timer_irqs, &s3c24xx_pwm_variant);
 263 }
 264
 265 /* Serial port registrations */
 266
 267 #define S3C2410_PA_UART0      (S3C24XX_PA_UART)
 268 #define S3C2410_PA_UART1      (S3C24XX_PA_UART + 0x4000 )
 269 #define S3C2410_PA_UART2      (S3C24XX_PA_UART + 0x8000 )
 270 #define S3C2443_PA_UART3      (S3C24XX_PA_UART + 0xC000 )
 271
 272 static struct resource s3c2410_uart0_resource[] = {
 273         [0] = DEFINE_RES_MEM(S3C2410_PA_UART0, SZ_16K),
 274         [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX0, \
 275                         IRQ_S3CUART_ERR0 - IRQ_S3CUART_RX0 + 1, \
 276                         NULL, IORESOURCE_IRQ)
 277 };
 278
 279 static struct resource s3c2410_uart1_resource[] = {
 280         [0] = DEFINE_RES_MEM(S3C2410_PA_UART1, SZ_16K),
 281         [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX1, \
 282                         IRQ_S3CUART_ERR1 - IRQ_S3CUART_RX1 + 1, \
 283                         NULL, IORESOURCE_IRQ)
 284 };
 285
 286 static struct resource s3c2410_uart2_resource[] = {
 287         [0] = DEFINE_RES_MEM(S3C2410_PA_UART2, SZ_16K),
 288         [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX2, \
 289                         IRQ_S3CUART_ERR2 - IRQ_S3CUART_RX2 + 1, \
 290                         NULL, IORESOURCE_IRQ)
 291 };
 292
 293 static struct resource s3c2410_uart3_resource[] = {
 294         [0] = DEFINE_RES_MEM(S3C2443_PA_UART3, SZ_16K),
 295         [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX3, \
 296                         IRQ_S3CUART_ERR3 - IRQ_S3CUART_RX3 + 1, \
 297                         NULL, IORESOURCE_IRQ)
 298 };
 299
 300 struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
 301         [0] = {
 302                 .resources      = s3c2410_uart0_resource,
 303                 .nr_resources   = ARRAY_SIZE(s3c2410_uart0_resource),
 304         },
 305         [1] = {
 306                 .resources      = s3c2410_uart1_resource,
 307                 .nr_resources   = ARRAY_SIZE(s3c2410_uart1_resource),
 308         },
 309         [2] = {
 310                 .resources      = s3c2410_uart2_resource,
 311                 .nr_resources   = ARRAY_SIZE(s3c2410_uart2_resource),
 312         },
 313         [3] = {
 314                 .resources      = s3c2410_uart3_resource,
 315                 .nr_resources   = ARRAY_SIZE(s3c2410_uart3_resource),
 316         },
 317 };
 318
 319 /* initialise all the clocks */
 320
 321 void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk,
 322                                            unsigned long hclk,
 323                                            unsigned long pclk)
 324 {
 325         clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON),
 326                                         clk_xtal.rate);
 327
 328         clk_mpll.rate = fclk;
 329         clk_h.rate = hclk;
 330         clk_p.rate = pclk;
 331         clk_f.rate = fclk;
 332 }
 333
 334 #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
 335         defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
 336 static struct resource s3c2410_dma_resource[] = {
 337         [0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA),
 338         [1] = DEFINE_RES_IRQ(IRQ_DMA0),
 339         [2] = DEFINE_RES_IRQ(IRQ_DMA1),
 340         [3] = DEFINE_RES_IRQ(IRQ_DMA2),
 341         [4] = DEFINE_RES_IRQ(IRQ_DMA3),
 342 };
 343 #endif
 344
 345 #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2442)
 346 static struct s3c24xx_dma_channel s3c2410_dma_channels[DMACH_MAX] = {
 347         [DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), },
 348         [DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), },
 349         [DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) |
 350                                                 S3C24XX_DMA_CHANREQ(2, 2) |
 351                                                 S3C24XX_DMA_CHANREQ(1, 3),
 352         },
 353         [DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), },
 354         [DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), },
 355         [DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), },
 356         [DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), },
 357         [DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), },
 358         [DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) |
 359                                                  S3C24XX_DMA_CHANREQ(3, 2) |
 360                                                  S3C24XX_DMA_CHANREQ(3, 3),
 361         },
 362         [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) |
 363                                                   S3C24XX_DMA_CHANREQ(1, 2),
 364         },
 365         [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 2), },
 366         [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), },
 367         [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), },
 368         [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), },
 369         [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), },
 370 };
 371
 372 static struct s3c24xx_dma_platdata s3c2410_dma_platdata = {
 373         .num_phy_channels = 4,
 374         .channels = s3c2410_dma_channels,
 375         .num_channels = DMACH_MAX,
 376 };
 377
 378 struct platform_device s3c2410_device_dma = {
 379         .name           = "s3c2410-dma",
 380         .id             = 0,
 381         .num_resources  = ARRAY_SIZE(s3c2410_dma_resource),
 382         .resource       = s3c2410_dma_resource,
 383         .dev    = {
 384                 .platform_data  = &s3c2410_dma_platdata,
 385         },
 386 };
 387 #endif
 388
 389 #ifdef CONFIG_CPU_S3C2412
 390 static struct s3c24xx_dma_channel s3c2412_dma_channels[DMACH_MAX] = {
 391         [DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 },
 392         [DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 },
 393         [DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 },
 394         [DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 },
 395         [DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 },
 396         [DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 },
 397         [DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 },
 398         [DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 },
 399         [DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 },
 400         [DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 },
 401         [DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 },
 402         [DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 },
 403         [DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 },
 404         [DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 },
 405         [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 },
 406         [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 },
 407         [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, 13 },
 408         [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, 14 },
 409         [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, 15 },
 410         [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, 16 },
 411 };
 412
 413 static struct s3c24xx_dma_platdata s3c2412_dma_platdata = {
 414         .num_phy_channels = 4,
 415         .channels = s3c2412_dma_channels,
 416         .num_channels = DMACH_MAX,
 417 };
 418
 419 struct platform_device s3c2412_device_dma = {
 420         .name           = "s3c2412-dma",
 421         .id             = 0,
 422         .num_resources  = ARRAY_SIZE(s3c2410_dma_resource),
 423         .resource       = s3c2410_dma_resource,
 424         .dev    = {
 425                 .platform_data  = &s3c2412_dma_platdata,
 426         },
 427 };
 428 #endif
 429
 430 #if defined(CONFIG_CPU_S3C2440)
 431 static struct s3c24xx_dma_channel s3c2440_dma_channels[DMACH_MAX] = {
 432         [DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), },
 433         [DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), },
 434         [DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) |
 435                                                 S3C24XX_DMA_CHANREQ(6, 1) |
 436                                                 S3C24XX_DMA_CHANREQ(2, 2) |
 437                                                 S3C24XX_DMA_CHANREQ(1, 3),
 438         },
 439         [DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), },
 440         [DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), },
 441         [DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), },
 442         [DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), },
 443         [DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), },
 444         [DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) |
 445                                                  S3C24XX_DMA_CHANREQ(3, 2) |
 446                                                  S3C24XX_DMA_CHANREQ(3, 3),
 447         },
 448         [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) |
 449                                                   S3C24XX_DMA_CHANREQ(1, 2),
 450         },
 451         [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 0) |
 452                                                    S3C24XX_DMA_CHANREQ(0, 2),
 453         },
 454         [DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 0) |
 455                                                   S3C24XX_DMA_CHANREQ(5, 2),
 456         },
 457         [DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 1) |
 458                                                   S3C24XX_DMA_CHANREQ(6, 3),
 459         },
 460         [DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 2) |
 461                                                   S3C24XX_DMA_CHANREQ(5, 3),
 462         },
 463         [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), },
 464         [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), },
 465         [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), },
 466         [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), },
 467 };
 468
 469 static struct s3c24xx_dma_platdata s3c2440_dma_platdata = {
 470         .num_phy_channels = 4,
 471         .channels = s3c2440_dma_channels,
 472         .num_channels = DMACH_MAX,
 473 };
 474
 475 struct platform_device s3c2440_device_dma = {
 476         .name           = "s3c2410-dma",
 477         .id             = 0,
 478         .num_resources  = ARRAY_SIZE(s3c2410_dma_resource),
 479         .resource       = s3c2410_dma_resource,
 480         .dev    = {
 481                 .platform_data  = &s3c2440_dma_platdata,
 482         },
 483 };
 484 #endif
 485
 486 #if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
 487 static struct resource s3c2443_dma_resource[] = {
 488         [0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA),
 489         [1] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA0),
 490         [2] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA1),
 491         [3] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA2),
 492         [4] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA3),
 493         [5] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA4),
 494         [6] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA5),
 495 };
 496
 497 static struct s3c24xx_dma_channel s3c2443_dma_channels[DMACH_MAX] = {
 498         [DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 },
 499         [DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 },
 500         [DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 },
 501         [DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 },
 502         [DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 },
 503         [DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 },
 504         [DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 },
 505         [DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 },
 506         [DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 },
 507         [DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 },
 508         [DMACH_UART3] = { S3C24XX_DMA_APB, true, 25 },
 509         [DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 },
 510         [DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 },
 511         [DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 },
 512         [DMACH_UART3_SRC2] = { S3C24XX_DMA_APB, true, 26 },
 513         [DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 },
 514         [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 },
 515         [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 },
 516         [DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, 28 },
 517         [DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, 27 },
 518         [DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, 29 },
 519 };
 520
 521 static struct s3c24xx_dma_platdata s3c2443_dma_platdata = {
 522         .num_phy_channels = 6,
 523         .channels = s3c2443_dma_channels,
 524         .num_channels = DMACH_MAX,
 525 };
 526
 527 struct platform_device s3c2443_device_dma = {
 528         .name           = "s3c2443-dma",
 529         .id             = 0,
 530         .num_resources  = ARRAY_SIZE(s3c2443_dma_resource),
 531         .resource       = s3c2443_dma_resource,
 532         .dev    = {
 533                 .platform_data  = &s3c2443_dma_platdata,
 534         },
 535 };
 536 #endif