1 /* linux/arch/arm/plat-s3c24xx/cpu.c
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * http://www.simtec.co.uk/products/SWLINUX/
5 * Ben Dooks <ben@simtec.co.uk>
7 * Common code for S3C24XX machines
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/dma-mapping.h>
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/interrupt.h>
28 #include <linux/ioport.h>
29 #include <linux/serial_core.h>
30 #include <linux/serial_s3c.h>
31 #include <clocksource/samsung_pwm.h>
32 #include <linux/platform_device.h>
33 #include <linux/delay.h>
35 #include <linux/platform_data/dma-s3c24xx.h>
37 #include <mach/hardware.h>
38 #include <mach/regs-clock.h>
40 #include <asm/cacheflush.h>
41 #include <asm/system_info.h>
42 #include <asm/system_misc.h>
44 #include <asm/mach/arch.h>
45 #include <asm/mach/map.h>
47 #include <mach/regs-gpio.h>
51 #include <plat/devs.h>
52 #include <plat/cpu-freq.h>
53 #include <plat/pwm-core.h>
57 /* table of supported CPUs */
59 static const char name_s3c2410
[] = "S3C2410";
60 static const char name_s3c2412
[] = "S3C2412";
61 static const char name_s3c2416
[] = "S3C2416/S3C2450";
62 static const char name_s3c2440
[] = "S3C2440";
63 static const char name_s3c2442
[] = "S3C2442";
64 static const char name_s3c2442b
[] = "S3C2442B";
65 static const char name_s3c2443
[] = "S3C2443";
66 static const char name_s3c2410a
[] = "S3C2410A";
67 static const char name_s3c2440a
[] = "S3C2440A";
69 static struct cpu_table cpu_ids
[] __initdata
= {
73 .map_io
= s3c2410_map_io
,
74 .init_uarts
= s3c2410_init_uarts
,
81 .map_io
= s3c2410_map_io
,
82 .init_uarts
= s3c2410_init_uarts
,
83 .init
= s3c2410a_init
,
89 .map_io
= s3c2440_map_io
,
90 .init_uarts
= s3c244x_init_uarts
,
97 .map_io
= s3c2440_map_io
,
98 .init_uarts
= s3c244x_init_uarts
,
100 .name
= name_s3c2440a
103 .idcode
= 0x32440aaa,
104 .idmask
= 0xffffffff,
105 .map_io
= s3c2442_map_io
,
106 .init_uarts
= s3c244x_init_uarts
,
107 .init
= s3c2442_init
,
111 .idcode
= 0x32440aab,
112 .idmask
= 0xffffffff,
113 .map_io
= s3c2442_map_io
,
114 .init_uarts
= s3c244x_init_uarts
,
115 .init
= s3c2442_init
,
116 .name
= name_s3c2442b
119 .idcode
= 0x32412001,
120 .idmask
= 0xffffffff,
121 .map_io
= s3c2412_map_io
,
122 .init_uarts
= s3c2412_init_uarts
,
123 .init
= s3c2412_init
,
124 .name
= name_s3c2412
,
126 { /* a newer version of the s3c2412 */
127 .idcode
= 0x32412003,
128 .idmask
= 0xffffffff,
129 .map_io
= s3c2412_map_io
,
130 .init_uarts
= s3c2412_init_uarts
,
131 .init
= s3c2412_init
,
132 .name
= name_s3c2412
,
134 { /* a strange version of the s3c2416 */
135 .idcode
= 0x32450003,
136 .idmask
= 0xffffffff,
137 .map_io
= s3c2416_map_io
,
138 .init_uarts
= s3c2416_init_uarts
,
139 .init
= s3c2416_init
,
140 .name
= name_s3c2416
,
143 .idcode
= 0x32443001,
144 .idmask
= 0xffffffff,
145 .map_io
= s3c2443_map_io
,
146 .init_uarts
= s3c2443_init_uarts
,
147 .init
= s3c2443_init
,
148 .name
= name_s3c2443
,
152 /* minimal IO mapping */
154 static struct map_desc s3c_iodesc
[] __initdata
= {
161 /* read cpu identificaiton code */
163 static unsigned long s3c24xx_read_idcode_v5(void)
165 #if defined(CONFIG_CPU_S3C2416)
166 /* s3c2416 is v5, with S3C24XX_GSTATUS1 instead of S3C2412_GSTATUS1 */
168 u32 gs
= __raw_readl(S3C24XX_GSTATUS1
);
170 /* test for s3c2416 or similar device */
171 if ((gs
>> 16) == 0x3245)
175 #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
176 return __raw_readl(S3C2412_GSTATUS1
);
178 return 1UL; /* don't look like an 2400 */
182 static unsigned long s3c24xx_read_idcode_v4(void)
184 return __raw_readl(S3C2410_GSTATUS1
);
187 static void s3c24xx_default_idle(void)
189 unsigned long tmp
= 0;
192 /* idle the system by using the idle mode which will wait for an
193 * interrupt to happen before restarting the system.
196 /* Warning: going into idle state upsets jtag scanning */
198 __raw_writel(__raw_readl(S3C2410_CLKCON
) | S3C2410_CLKCON_IDLE
,
201 /* the samsung port seems to do a loop and then unset idle.. */
202 for (i
= 0; i
< 50; i
++)
203 tmp
+= __raw_readl(S3C2410_CLKCON
); /* ensure loop not optimised out */
205 /* this bit is not cleared on re-start... */
207 __raw_writel(__raw_readl(S3C2410_CLKCON
) & ~S3C2410_CLKCON_IDLE
,
211 static struct samsung_pwm_variant s3c24xx_pwm_variant
= {
214 .has_tint_cstat
= false,
215 .tclk_mask
= (1 << 4),
218 void __init
s3c24xx_init_io(struct map_desc
*mach_desc
, int size
)
220 arm_pm_idle
= s3c24xx_default_idle
;
222 /* initialise the io descriptors we need for initialisation */
223 iotable_init(mach_desc
, size
);
224 iotable_init(s3c_iodesc
, ARRAY_SIZE(s3c_iodesc
));
226 if (cpu_architecture() >= CPU_ARCH_ARMv5
) {
227 samsung_cpu_id
= s3c24xx_read_idcode_v5();
229 samsung_cpu_id
= s3c24xx_read_idcode_v4();
232 s3c_init_cpu(samsung_cpu_id
, cpu_ids
, ARRAY_SIZE(cpu_ids
));
234 samsung_pwm_set_platdata(&s3c24xx_pwm_variant
);
237 void __init
samsung_set_timer_source(unsigned int event
, unsigned int source
)
239 s3c24xx_pwm_variant
.output_mask
= BIT(SAMSUNG_PWM_NUM
) - 1;
240 s3c24xx_pwm_variant
.output_mask
&= ~(BIT(event
) | BIT(source
));
243 void __init
samsung_timer_init(void)
245 unsigned int timer_irqs
[SAMSUNG_PWM_NUM
] = {
246 IRQ_TIMER0
, IRQ_TIMER1
, IRQ_TIMER2
, IRQ_TIMER3
, IRQ_TIMER4
,
249 samsung_pwm_clocksource_init(S3C_VA_TIMER
,
250 timer_irqs
, &s3c24xx_pwm_variant
);
253 /* Serial port registrations */
255 #define S3C2410_PA_UART0 (S3C24XX_PA_UART)
256 #define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 )
257 #define S3C2410_PA_UART2 (S3C24XX_PA_UART + 0x8000 )
258 #define S3C2443_PA_UART3 (S3C24XX_PA_UART + 0xC000 )
260 static struct resource s3c2410_uart0_resource
[] = {
261 [0] = DEFINE_RES_MEM(S3C2410_PA_UART0
, SZ_16K
),
262 [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX0
, \
263 IRQ_S3CUART_ERR0
- IRQ_S3CUART_RX0
+ 1, \
264 NULL
, IORESOURCE_IRQ
)
267 static struct resource s3c2410_uart1_resource
[] = {
268 [0] = DEFINE_RES_MEM(S3C2410_PA_UART1
, SZ_16K
),
269 [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX1
, \
270 IRQ_S3CUART_ERR1
- IRQ_S3CUART_RX1
+ 1, \
271 NULL
, IORESOURCE_IRQ
)
274 static struct resource s3c2410_uart2_resource
[] = {
275 [0] = DEFINE_RES_MEM(S3C2410_PA_UART2
, SZ_16K
),
276 [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX2
, \
277 IRQ_S3CUART_ERR2
- IRQ_S3CUART_RX2
+ 1, \
278 NULL
, IORESOURCE_IRQ
)
281 static struct resource s3c2410_uart3_resource
[] = {
282 [0] = DEFINE_RES_MEM(S3C2443_PA_UART3
, SZ_16K
),
283 [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX3
, \
284 IRQ_S3CUART_ERR3
- IRQ_S3CUART_RX3
+ 1, \
285 NULL
, IORESOURCE_IRQ
)
288 struct s3c24xx_uart_resources s3c2410_uart_resources
[] __initdata
= {
290 .resources
= s3c2410_uart0_resource
,
291 .nr_resources
= ARRAY_SIZE(s3c2410_uart0_resource
),
294 .resources
= s3c2410_uart1_resource
,
295 .nr_resources
= ARRAY_SIZE(s3c2410_uart1_resource
),
298 .resources
= s3c2410_uart2_resource
,
299 .nr_resources
= ARRAY_SIZE(s3c2410_uart2_resource
),
302 .resources
= s3c2410_uart3_resource
,
303 .nr_resources
= ARRAY_SIZE(s3c2410_uart3_resource
),
307 #define s3c24xx_device_dma_mask (*((u64[]) { DMA_BIT_MASK(32) }))
309 #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
310 defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
311 static struct resource s3c2410_dma_resource
[] = {
312 [0] = DEFINE_RES_MEM(S3C24XX_PA_DMA
, S3C24XX_SZ_DMA
),
313 [1] = DEFINE_RES_IRQ(IRQ_DMA0
),
314 [2] = DEFINE_RES_IRQ(IRQ_DMA1
),
315 [3] = DEFINE_RES_IRQ(IRQ_DMA2
),
316 [4] = DEFINE_RES_IRQ(IRQ_DMA3
),
320 #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2442)
321 static struct s3c24xx_dma_channel s3c2410_dma_channels
[DMACH_MAX
] = {
322 [DMACH_XD0
] = { S3C24XX_DMA_AHB
, true, S3C24XX_DMA_CHANREQ(0, 0), },
323 [DMACH_XD1
] = { S3C24XX_DMA_AHB
, true, S3C24XX_DMA_CHANREQ(0, 1), },
324 [DMACH_SDI
] = { S3C24XX_DMA_APB
, false, S3C24XX_DMA_CHANREQ(2, 0) |
325 S3C24XX_DMA_CHANREQ(2, 2) |
326 S3C24XX_DMA_CHANREQ(1, 3),
328 [DMACH_SPI0
] = { S3C24XX_DMA_APB
, true, S3C24XX_DMA_CHANREQ(3, 1), },
329 [DMACH_SPI1
] = { S3C24XX_DMA_APB
, true, S3C24XX_DMA_CHANREQ(2, 3), },
330 [DMACH_UART0
] = { S3C24XX_DMA_APB
, true, S3C24XX_DMA_CHANREQ(1, 0), },
331 [DMACH_UART1
] = { S3C24XX_DMA_APB
, true, S3C24XX_DMA_CHANREQ(1, 1), },
332 [DMACH_UART2
] = { S3C24XX_DMA_APB
, true, S3C24XX_DMA_CHANREQ(0, 3), },
333 [DMACH_TIMER
] = { S3C24XX_DMA_APB
, true, S3C24XX_DMA_CHANREQ(3, 0) |
334 S3C24XX_DMA_CHANREQ(3, 2) |
335 S3C24XX_DMA_CHANREQ(3, 3),
337 [DMACH_I2S_IN
] = { S3C24XX_DMA_APB
, true, S3C24XX_DMA_CHANREQ(2, 1) |
338 S3C24XX_DMA_CHANREQ(1, 2),
340 [DMACH_I2S_OUT
] = { S3C24XX_DMA_APB
, true, S3C24XX_DMA_CHANREQ(0, 2), },
341 [DMACH_USB_EP1
] = { S3C24XX_DMA_APB
, true, S3C24XX_DMA_CHANREQ(4, 0), },
342 [DMACH_USB_EP2
] = { S3C24XX_DMA_APB
, true, S3C24XX_DMA_CHANREQ(4, 1), },
343 [DMACH_USB_EP3
] = { S3C24XX_DMA_APB
, true, S3C24XX_DMA_CHANREQ(4, 2), },
344 [DMACH_USB_EP4
] = { S3C24XX_DMA_APB
, true, S3C24XX_DMA_CHANREQ(4, 3), },
347 static struct s3c24xx_dma_platdata s3c2410_dma_platdata
= {
348 .num_phy_channels
= 4,
349 .channels
= s3c2410_dma_channels
,
350 .num_channels
= DMACH_MAX
,
353 struct platform_device s3c2410_device_dma
= {
354 .name
= "s3c2410-dma",
356 .num_resources
= ARRAY_SIZE(s3c2410_dma_resource
),
357 .resource
= s3c2410_dma_resource
,
359 .dma_mask
= &s3c24xx_device_dma_mask
,
360 .coherent_dma_mask
= DMA_BIT_MASK(32),
361 .platform_data
= &s3c2410_dma_platdata
,
366 #ifdef CONFIG_CPU_S3C2412
367 static struct s3c24xx_dma_channel s3c2412_dma_channels
[DMACH_MAX
] = {
368 [DMACH_XD0
] = { S3C24XX_DMA_AHB
, true, 17 },
369 [DMACH_XD1
] = { S3C24XX_DMA_AHB
, true, 18 },
370 [DMACH_SDI
] = { S3C24XX_DMA_APB
, false, 10 },
371 [DMACH_SPI0_RX
] = { S3C24XX_DMA_APB
, true, 1 },
372 [DMACH_SPI0_TX
] = { S3C24XX_DMA_APB
, true, 0 },
373 [DMACH_SPI1_RX
] = { S3C24XX_DMA_APB
, true, 3 },
374 [DMACH_SPI1_TX
] = { S3C24XX_DMA_APB
, true, 2 },
375 [DMACH_UART0
] = { S3C24XX_DMA_APB
, true, 19 },
376 [DMACH_UART1
] = { S3C24XX_DMA_APB
, true, 21 },
377 [DMACH_UART2
] = { S3C24XX_DMA_APB
, true, 23 },
378 [DMACH_UART0_SRC2
] = { S3C24XX_DMA_APB
, true, 20 },
379 [DMACH_UART1_SRC2
] = { S3C24XX_DMA_APB
, true, 22 },
380 [DMACH_UART2_SRC2
] = { S3C24XX_DMA_APB
, true, 24 },
381 [DMACH_TIMER
] = { S3C24XX_DMA_APB
, true, 9 },
382 [DMACH_I2S_IN
] = { S3C24XX_DMA_APB
, true, 5 },
383 [DMACH_I2S_OUT
] = { S3C24XX_DMA_APB
, true, 4 },
384 [DMACH_USB_EP1
] = { S3C24XX_DMA_APB
, true, 13 },
385 [DMACH_USB_EP2
] = { S3C24XX_DMA_APB
, true, 14 },
386 [DMACH_USB_EP3
] = { S3C24XX_DMA_APB
, true, 15 },
387 [DMACH_USB_EP4
] = { S3C24XX_DMA_APB
, true, 16 },
390 static struct s3c24xx_dma_platdata s3c2412_dma_platdata
= {
391 .num_phy_channels
= 4,
392 .channels
= s3c2412_dma_channels
,
393 .num_channels
= DMACH_MAX
,
396 struct platform_device s3c2412_device_dma
= {
397 .name
= "s3c2412-dma",
399 .num_resources
= ARRAY_SIZE(s3c2410_dma_resource
),
400 .resource
= s3c2410_dma_resource
,
402 .dma_mask
= &s3c24xx_device_dma_mask
,
403 .coherent_dma_mask
= DMA_BIT_MASK(32),
404 .platform_data
= &s3c2412_dma_platdata
,
409 #if defined(CONFIG_CPU_S3C2440)
410 static struct s3c24xx_dma_channel s3c2440_dma_channels
[DMACH_MAX
] = {
411 [DMACH_XD0
] = { S3C24XX_DMA_AHB
, true, S3C24XX_DMA_CHANREQ(0, 0), },
412 [DMACH_XD1
] = { S3C24XX_DMA_AHB
, true, S3C24XX_DMA_CHANREQ(0, 1), },
413 [DMACH_SDI
] = { S3C24XX_DMA_APB
, false, S3C24XX_DMA_CHANREQ(2, 0) |
414 S3C24XX_DMA_CHANREQ(6, 1) |
415 S3C24XX_DMA_CHANREQ(2, 2) |
416 S3C24XX_DMA_CHANREQ(1, 3),
418 [DMACH_SPI0
] = { S3C24XX_DMA_APB
, true, S3C24XX_DMA_CHANREQ(3, 1), },
419 [DMACH_SPI1
] = { S3C24XX_DMA_APB
, true, S3C24XX_DMA_CHANREQ(2, 3), },
420 [DMACH_UART0
] = { S3C24XX_DMA_APB
, true, S3C24XX_DMA_CHANREQ(1, 0), },
421 [DMACH_UART1
] = { S3C24XX_DMA_APB
, true, S3C24XX_DMA_CHANREQ(1, 1), },
422 [DMACH_UART2
] = { S3C24XX_DMA_APB
, true, S3C24XX_DMA_CHANREQ(0, 3), },
423 [DMACH_TIMER
] = { S3C24XX_DMA_APB
, true, S3C24XX_DMA_CHANREQ(3, 0) |
424 S3C24XX_DMA_CHANREQ(3, 2) |
425 S3C24XX_DMA_CHANREQ(3, 3),
427 [DMACH_I2S_IN
] = { S3C24XX_DMA_APB
, true, S3C24XX_DMA_CHANREQ(2, 1) |
428 S3C24XX_DMA_CHANREQ(1, 2),
430 [DMACH_I2S_OUT
] = { S3C24XX_DMA_APB
, true, S3C24XX_DMA_CHANREQ(5, 0) |
431 S3C24XX_DMA_CHANREQ(0, 2),
433 [DMACH_PCM_IN
] = { S3C24XX_DMA_APB
, true, S3C24XX_DMA_CHANREQ(6, 0) |
434 S3C24XX_DMA_CHANREQ(5, 2),
436 [DMACH_PCM_OUT
] = { S3C24XX_DMA_APB
, true, S3C24XX_DMA_CHANREQ(5, 1) |
437 S3C24XX_DMA_CHANREQ(6, 3),
439 [DMACH_MIC_IN
] = { S3C24XX_DMA_APB
, true, S3C24XX_DMA_CHANREQ(6, 2) |
440 S3C24XX_DMA_CHANREQ(5, 3),
442 [DMACH_USB_EP1
] = { S3C24XX_DMA_APB
, true, S3C24XX_DMA_CHANREQ(4, 0), },
443 [DMACH_USB_EP2
] = { S3C24XX_DMA_APB
, true, S3C24XX_DMA_CHANREQ(4, 1), },
444 [DMACH_USB_EP3
] = { S3C24XX_DMA_APB
, true, S3C24XX_DMA_CHANREQ(4, 2), },
445 [DMACH_USB_EP4
] = { S3C24XX_DMA_APB
, true, S3C24XX_DMA_CHANREQ(4, 3), },
448 static struct s3c24xx_dma_platdata s3c2440_dma_platdata
= {
449 .num_phy_channels
= 4,
450 .channels
= s3c2440_dma_channels
,
451 .num_channels
= DMACH_MAX
,
454 struct platform_device s3c2440_device_dma
= {
455 .name
= "s3c2410-dma",
457 .num_resources
= ARRAY_SIZE(s3c2410_dma_resource
),
458 .resource
= s3c2410_dma_resource
,
460 .dma_mask
= &s3c24xx_device_dma_mask
,
461 .coherent_dma_mask
= DMA_BIT_MASK(32),
462 .platform_data
= &s3c2440_dma_platdata
,
467 #if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
468 static struct resource s3c2443_dma_resource
[] = {
469 [0] = DEFINE_RES_MEM(S3C24XX_PA_DMA
, S3C24XX_SZ_DMA
),
470 [1] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA0
),
471 [2] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA1
),
472 [3] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA2
),
473 [4] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA3
),
474 [5] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA4
),
475 [6] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA5
),
478 static struct s3c24xx_dma_channel s3c2443_dma_channels
[DMACH_MAX
] = {
479 [DMACH_XD0
] = { S3C24XX_DMA_AHB
, true, 17 },
480 [DMACH_XD1
] = { S3C24XX_DMA_AHB
, true, 18 },
481 [DMACH_SDI
] = { S3C24XX_DMA_APB
, false, 10 },
482 [DMACH_SPI0_RX
] = { S3C24XX_DMA_APB
, true, 1 },
483 [DMACH_SPI0_TX
] = { S3C24XX_DMA_APB
, true, 0 },
484 [DMACH_SPI1_RX
] = { S3C24XX_DMA_APB
, true, 3 },
485 [DMACH_SPI1_TX
] = { S3C24XX_DMA_APB
, true, 2 },
486 [DMACH_UART0
] = { S3C24XX_DMA_APB
, true, 19 },
487 [DMACH_UART1
] = { S3C24XX_DMA_APB
, true, 21 },
488 [DMACH_UART2
] = { S3C24XX_DMA_APB
, true, 23 },
489 [DMACH_UART3
] = { S3C24XX_DMA_APB
, true, 25 },
490 [DMACH_UART0_SRC2
] = { S3C24XX_DMA_APB
, true, 20 },
491 [DMACH_UART1_SRC2
] = { S3C24XX_DMA_APB
, true, 22 },
492 [DMACH_UART2_SRC2
] = { S3C24XX_DMA_APB
, true, 24 },
493 [DMACH_UART3_SRC2
] = { S3C24XX_DMA_APB
, true, 26 },
494 [DMACH_TIMER
] = { S3C24XX_DMA_APB
, true, 9 },
495 [DMACH_I2S_IN
] = { S3C24XX_DMA_APB
, true, 5 },
496 [DMACH_I2S_OUT
] = { S3C24XX_DMA_APB
, true, 4 },
497 [DMACH_PCM_IN
] = { S3C24XX_DMA_APB
, true, 28 },
498 [DMACH_PCM_OUT
] = { S3C24XX_DMA_APB
, true, 27 },
499 [DMACH_MIC_IN
] = { S3C24XX_DMA_APB
, true, 29 },
502 static struct s3c24xx_dma_platdata s3c2443_dma_platdata
= {
503 .num_phy_channels
= 6,
504 .channels
= s3c2443_dma_channels
,
505 .num_channels
= DMACH_MAX
,
508 struct platform_device s3c2443_device_dma
= {
509 .name
= "s3c2443-dma",
511 .num_resources
= ARRAY_SIZE(s3c2443_dma_resource
),
512 .resource
= s3c2443_dma_resource
,
514 .dma_mask
= &s3c24xx_device_dma_mask
,
515 .coherent_dma_mask
= DMA_BIT_MASK(32),
516 .platform_data
= &s3c2443_dma_platdata
,
521 #if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2410)
522 void __init
s3c2410_init_clocks(int xtal
)
524 s3c2410_common_clk_init(NULL
, xtal
, 0, S3C24XX_VA_CLKPWR
);
528 #ifdef CONFIG_CPU_S3C2412
529 void __init
s3c2412_init_clocks(int xtal
)
531 s3c2412_common_clk_init(NULL
, xtal
, 0, S3C24XX_VA_CLKPWR
);
535 #ifdef CONFIG_CPU_S3C2416
536 void __init
s3c2416_init_clocks(int xtal
)
538 s3c2443_common_clk_init(NULL
, xtal
, 0, S3C24XX_VA_CLKPWR
);
542 #if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2440)
543 void __init
s3c2440_init_clocks(int xtal
)
545 s3c2410_common_clk_init(NULL
, xtal
, 1, S3C24XX_VA_CLKPWR
);
549 #if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2442)
550 void __init
s3c2442_init_clocks(int xtal
)
552 s3c2410_common_clk_init(NULL
, xtal
, 2, S3C24XX_VA_CLKPWR
);
556 #ifdef CONFIG_CPU_S3C2443
557 void __init
s3c2443_init_clocks(int xtal
)
559 s3c2443_common_clk_init(NULL
, xtal
, 1, S3C24XX_VA_CLKPWR
);
563 #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2440) || \
564 defined(CONFIG_CPU_S3C2442)
565 static struct resource s3c2410_dclk_resource
[] = {
566 [0] = DEFINE_RES_MEM(0x56000084, 0x4),
569 struct platform_device s3c2410_device_dclk
= {
570 .name
= "s3c2410-dclk",
572 .num_resources
= ARRAY_SIZE(s3c2410_dclk_resource
),
573 .resource
= s3c2410_dclk_resource
,