arch/arm/mach-s3c24xx/common.c

   1 /* linux/arch/arm/plat-s3c24xx/cpu.c
   2  *
   3  * Copyright (c) 2004-2005 Simtec Electronics
   4  *      http://www.simtec.co.uk/products/SWLINUX/
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *
   7  * Common code for S3C24XX machines
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  22 */
  23
  24
  25 #include <linux/init.h>
  26 #include <linux/module.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/ioport.h>
  29 #include <linux/serial_core.h>
  30 #include <linux/serial_s3c.h>
  31 #include <clocksource/samsung_pwm.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/delay.h>
  34 #include <linux/io.h>
  35 #include <linux/platform_data/dma-s3c24xx.h>
  36
  37 #include <mach/hardware.h>
  38 #include <mach/regs-clock.h>
  39 #include <asm/irq.h>
  40 #include <asm/cacheflush.h>
  41 #include <asm/system_info.h>
  42 #include <asm/system_misc.h>
  43
  44 #include <asm/mach/arch.h>
  45 #include <asm/mach/map.h>
  46
  47 #include <mach/regs-gpio.h>
  48 #include <mach/dma.h>
  49
  50 #include <plat/cpu.h>
  51 #include <plat/devs.h>
  52 #include <plat/clock.h>
  53 #include <plat/cpu-freq.h>
  54 #include <plat/pll.h>
  55 #include <plat/pwm-core.h>
  56 #include <plat/watchdog-reset.h>
  57
  58 #include "common.h"
  59
  60 /* table of supported CPUs */
  61
  62 static const char name_s3c2410[]  = "S3C2410";
  63 static const char name_s3c2412[]  = "S3C2412";
  64 static const char name_s3c2416[]  = "S3C2416/S3C2450";
  65 static const char name_s3c2440[]  = "S3C2440";
  66 static const char name_s3c2442[]  = "S3C2442";
  67 static const char name_s3c2442b[]  = "S3C2442B";
  68 static const char name_s3c2443[]  = "S3C2443";
  69 static const char name_s3c2410a[] = "S3C2410A";
  70 static const char name_s3c2440a[] = "S3C2440A";
  71
  72 static struct cpu_table cpu_ids[] __initdata = {
  73         {
  74                 .idcode         = 0x32410000,
  75                 .idmask         = 0xffffffff,
  76                 .map_io         = s3c2410_map_io,
  77                 .init_uarts     = s3c2410_init_uarts,
  78                 .init           = s3c2410_init,
  79                 .name           = name_s3c2410
  80         },
  81         {
  82                 .idcode         = 0x32410002,
  83                 .idmask         = 0xffffffff,
  84                 .map_io         = s3c2410_map_io,
  85                 .init_uarts     = s3c2410_init_uarts,
  86                 .init           = s3c2410a_init,
  87                 .name           = name_s3c2410a
  88         },
  89         {
  90                 .idcode         = 0x32440000,
  91                 .idmask         = 0xffffffff,
  92                 .map_io         = s3c2440_map_io,
  93                 .init_uarts     = s3c244x_init_uarts,
  94                 .init           = s3c2440_init,
  95                 .name           = name_s3c2440
  96         },
  97         {
  98                 .idcode         = 0x32440001,
  99                 .idmask         = 0xffffffff,
 100                 .map_io         = s3c2440_map_io,
 101                 .init_uarts     = s3c244x_init_uarts,
 102                 .init           = s3c2440_init,
 103                 .name           = name_s3c2440a
 104         },
 105         {
 106                 .idcode         = 0x32440aaa,
 107                 .idmask         = 0xffffffff,
 108                 .map_io         = s3c2442_map_io,
 109                 .init_uarts     = s3c244x_init_uarts,
 110                 .init           = s3c2442_init,
 111                 .name           = name_s3c2442
 112         },
 113         {
 114                 .idcode         = 0x32440aab,
 115                 .idmask         = 0xffffffff,
 116                 .map_io         = s3c2442_map_io,
 117                 .init_uarts     = s3c244x_init_uarts,
 118                 .init           = s3c2442_init,
 119                 .name           = name_s3c2442b
 120         },
 121         {
 122                 .idcode         = 0x32412001,
 123                 .idmask         = 0xffffffff,
 124                 .map_io         = s3c2412_map_io,
 125                 .init_uarts     = s3c2412_init_uarts,
 126                 .init           = s3c2412_init,
 127                 .name           = name_s3c2412,
 128         },
 129         {                       /* a newer version of the s3c2412 */
 130                 .idcode         = 0x32412003,
 131                 .idmask         = 0xffffffff,
 132                 .map_io         = s3c2412_map_io,
 133                 .init_uarts     = s3c2412_init_uarts,
 134                 .init           = s3c2412_init,
 135                 .name           = name_s3c2412,
 136         },
 137         {                       /* a strange version of the s3c2416 */
 138                 .idcode         = 0x32450003,
 139                 .idmask         = 0xffffffff,
 140                 .map_io         = s3c2416_map_io,
 141                 .init_uarts     = s3c2416_init_uarts,
 142                 .init           = s3c2416_init,
 143                 .name           = name_s3c2416,
 144         },
 145         {
 146                 .idcode         = 0x32443001,
 147                 .idmask         = 0xffffffff,
 148                 .map_io         = s3c2443_map_io,
 149                 .init_uarts     = s3c2443_init_uarts,
 150                 .init           = s3c2443_init,
 151                 .name           = name_s3c2443,
 152         },
 153 };
 154
 155 /* minimal IO mapping */
 156
 157 static struct map_desc s3c_iodesc[] __initdata = {
 158         IODESC_ENT(GPIO),
 159         IODESC_ENT(IRQ),
 160         IODESC_ENT(MEMCTRL),
 161         IODESC_ENT(UART)
 162 };
 163
 164 /* read cpu identificaiton code */
 165
 166 static unsigned long s3c24xx_read_idcode_v5(void)
 167 {
 168 #if defined(CONFIG_CPU_S3C2416)
 169         /* s3c2416 is v5, with S3C24XX_GSTATUS1 instead of S3C2412_GSTATUS1 */
 170
 171         u32 gs = __raw_readl(S3C24XX_GSTATUS1);
 172
 173         /* test for s3c2416 or similar device */
 174         if ((gs >> 16) == 0x3245)
 175                 return gs;
 176 #endif
 177
 178 #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
 179         return __raw_readl(S3C2412_GSTATUS1);
 180 #else
 181         return 1UL;     /* don't look like an 2400 */
 182 #endif
 183 }
 184
 185 static unsigned long s3c24xx_read_idcode_v4(void)
 186 {
 187         return __raw_readl(S3C2410_GSTATUS1);
 188 }
 189
 190 static void s3c24xx_default_idle(void)
 191 {
 192         unsigned long tmp = 0;
 193         int i;
 194
 195         /* idle the system by using the idle mode which will wait for an
 196          * interrupt to happen before restarting the system.
 197          */
 198
 199         /* Warning: going into idle state upsets jtag scanning */
 200
 201         __raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE,
 202                      S3C2410_CLKCON);
 203
 204         /* the samsung port seems to do a loop and then unset idle.. */
 205         for (i = 0; i < 50; i++)
 206                 tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */
 207
 208         /* this bit is not cleared on re-start... */
 209
 210         __raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE,
 211                      S3C2410_CLKCON);
 212 }
 213
 214 static struct samsung_pwm_variant s3c24xx_pwm_variant = {
 215         .bits           = 16,
 216         .div_base       = 1,
 217         .has_tint_cstat = false,
 218         .tclk_mask      = (1 << 4),
 219 };
 220
 221 void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
 222 {
 223         arm_pm_idle = s3c24xx_default_idle;
 224
 225         /* initialise the io descriptors we need for initialisation */
 226         iotable_init(mach_desc, size);
 227         iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
 228
 229         if (cpu_architecture() >= CPU_ARCH_ARMv5) {
 230                 samsung_cpu_id = s3c24xx_read_idcode_v5();
 231         } else {
 232                 samsung_cpu_id = s3c24xx_read_idcode_v4();
 233         }
 234
 235         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 236
 237         samsung_pwm_set_platdata(&s3c24xx_pwm_variant);
 238 }
 239
 240 void __init samsung_set_timer_source(unsigned int event, unsigned int source)
 241 {
 242         s3c24xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
 243         s3c24xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
 244 }
 245
 246 void __init samsung_timer_init(void)
 247 {
 248         unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
 249                 IRQ_TIMER0, IRQ_TIMER1, IRQ_TIMER2, IRQ_TIMER3, IRQ_TIMER4,
 250         };
 251
 252         samsung_pwm_clocksource_init(S3C_VA_TIMER,
 253                                         timer_irqs, &s3c24xx_pwm_variant);
 254 }
 255
 256 /* Serial port registrations */
 257
 258 #define S3C2410_PA_UART0      (S3C24XX_PA_UART)
 259 #define S3C2410_PA_UART1      (S3C24XX_PA_UART + 0x4000 )
 260 #define S3C2410_PA_UART2      (S3C24XX_PA_UART + 0x8000 )
 261 #define S3C2443_PA_UART3      (S3C24XX_PA_UART + 0xC000 )
 262
 263 static struct resource s3c2410_uart0_resource[] = {
 264         [0] = DEFINE_RES_MEM(S3C2410_PA_UART0, SZ_16K),
 265         [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX0, \
 266                         IRQ_S3CUART_ERR0 - IRQ_S3CUART_RX0 + 1, \
 267                         NULL, IORESOURCE_IRQ)
 268 };
 269
 270 static struct resource s3c2410_uart1_resource[] = {
 271         [0] = DEFINE_RES_MEM(S3C2410_PA_UART1, SZ_16K),
 272         [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX1, \
 273                         IRQ_S3CUART_ERR1 - IRQ_S3CUART_RX1 + 1, \
 274                         NULL, IORESOURCE_IRQ)
 275 };
 276
 277 static struct resource s3c2410_uart2_resource[] = {
 278         [0] = DEFINE_RES_MEM(S3C2410_PA_UART2, SZ_16K),
 279         [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX2, \
 280                         IRQ_S3CUART_ERR2 - IRQ_S3CUART_RX2 + 1, \
 281                         NULL, IORESOURCE_IRQ)
 282 };
 283
 284 static struct resource s3c2410_uart3_resource[] = {
 285         [0] = DEFINE_RES_MEM(S3C2443_PA_UART3, SZ_16K),
 286         [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX3, \
 287                         IRQ_S3CUART_ERR3 - IRQ_S3CUART_RX3 + 1, \
 288                         NULL, IORESOURCE_IRQ)
 289 };
 290
 291 struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
 292         [0] = {
 293                 .resources      = s3c2410_uart0_resource,
 294                 .nr_resources   = ARRAY_SIZE(s3c2410_uart0_resource),
 295         },
 296         [1] = {
 297                 .resources      = s3c2410_uart1_resource,
 298                 .nr_resources   = ARRAY_SIZE(s3c2410_uart1_resource),
 299         },
 300         [2] = {
 301                 .resources      = s3c2410_uart2_resource,
 302                 .nr_resources   = ARRAY_SIZE(s3c2410_uart2_resource),
 303         },
 304         [3] = {
 305                 .resources      = s3c2410_uart3_resource,
 306                 .nr_resources   = ARRAY_SIZE(s3c2410_uart3_resource),
 307         },
 308 };
 309
 310 #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
 311         defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
 312 static struct resource s3c2410_dma_resource[] = {
 313         [0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA),
 314         [1] = DEFINE_RES_IRQ(IRQ_DMA0),
 315         [2] = DEFINE_RES_IRQ(IRQ_DMA1),
 316         [3] = DEFINE_RES_IRQ(IRQ_DMA2),
 317         [4] = DEFINE_RES_IRQ(IRQ_DMA3),
 318 };
 319 #endif
 320
 321 #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2442)
 322 static struct s3c24xx_dma_channel s3c2410_dma_channels[DMACH_MAX] = {
 323         [DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), },
 324         [DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), },
 325         [DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) |
 326                                                 S3C24XX_DMA_CHANREQ(2, 2) |
 327                                                 S3C24XX_DMA_CHANREQ(1, 3),
 328         },
 329         [DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), },
 330         [DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), },
 331         [DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), },
 332         [DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), },
 333         [DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), },
 334         [DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) |
 335                                                  S3C24XX_DMA_CHANREQ(3, 2) |
 336                                                  S3C24XX_DMA_CHANREQ(3, 3),
 337         },
 338         [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) |
 339                                                   S3C24XX_DMA_CHANREQ(1, 2),
 340         },
 341         [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 2), },
 342         [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), },
 343         [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), },
 344         [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), },
 345         [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), },
 346 };
 347
 348 static struct s3c24xx_dma_platdata s3c2410_dma_platdata = {
 349         .num_phy_channels = 4,
 350         .channels = s3c2410_dma_channels,
 351         .num_channels = DMACH_MAX,
 352 };
 353
 354 struct platform_device s3c2410_device_dma = {
 355         .name           = "s3c2410-dma",
 356         .id             = 0,
 357         .num_resources  = ARRAY_SIZE(s3c2410_dma_resource),
 358         .resource       = s3c2410_dma_resource,
 359         .dev    = {
 360                 .platform_data  = &s3c2410_dma_platdata,
 361         },
 362 };
 363 #endif
 364
 365 #ifdef CONFIG_CPU_S3C2412
 366 static struct s3c24xx_dma_channel s3c2412_dma_channels[DMACH_MAX] = {
 367         [DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 },
 368         [DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 },
 369         [DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 },
 370         [DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 },
 371         [DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 },
 372         [DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 },
 373         [DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 },
 374         [DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 },
 375         [DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 },
 376         [DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 },
 377         [DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 },
 378         [DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 },
 379         [DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 },
 380         [DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 },
 381         [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 },
 382         [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 },
 383         [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, 13 },
 384         [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, 14 },
 385         [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, 15 },
 386         [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, 16 },
 387 };
 388
 389 static struct s3c24xx_dma_platdata s3c2412_dma_platdata = {
 390         .num_phy_channels = 4,
 391         .channels = s3c2412_dma_channels,
 392         .num_channels = DMACH_MAX,
 393 };
 394
 395 struct platform_device s3c2412_device_dma = {
 396         .name           = "s3c2412-dma",
 397         .id             = 0,
 398         .num_resources  = ARRAY_SIZE(s3c2410_dma_resource),
 399         .resource       = s3c2410_dma_resource,
 400         .dev    = {
 401                 .platform_data  = &s3c2412_dma_platdata,
 402         },
 403 };
 404 #endif
 405
 406 #if defined(CONFIG_CPU_S3C2440)
 407 static struct s3c24xx_dma_channel s3c2440_dma_channels[DMACH_MAX] = {
 408         [DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), },
 409         [DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), },
 410         [DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) |
 411                                                 S3C24XX_DMA_CHANREQ(6, 1) |
 412                                                 S3C24XX_DMA_CHANREQ(2, 2) |
 413                                                 S3C24XX_DMA_CHANREQ(1, 3),
 414         },
 415         [DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), },
 416         [DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), },
 417         [DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), },
 418         [DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), },
 419         [DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), },
 420         [DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) |
 421                                                  S3C24XX_DMA_CHANREQ(3, 2) |
 422                                                  S3C24XX_DMA_CHANREQ(3, 3),
 423         },
 424         [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) |
 425                                                   S3C24XX_DMA_CHANREQ(1, 2),
 426         },
 427         [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 0) |
 428                                                    S3C24XX_DMA_CHANREQ(0, 2),
 429         },
 430         [DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 0) |
 431                                                   S3C24XX_DMA_CHANREQ(5, 2),
 432         },
 433         [DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 1) |
 434                                                   S3C24XX_DMA_CHANREQ(6, 3),
 435         },
 436         [DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 2) |
 437                                                   S3C24XX_DMA_CHANREQ(5, 3),
 438         },
 439         [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), },
 440         [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), },
 441         [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), },
 442         [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), },
 443 };
 444
 445 static struct s3c24xx_dma_platdata s3c2440_dma_platdata = {
 446         .num_phy_channels = 4,
 447         .channels = s3c2440_dma_channels,
 448         .num_channels = DMACH_MAX,
 449 };
 450
 451 struct platform_device s3c2440_device_dma = {
 452         .name           = "s3c2410-dma",
 453         .id             = 0,
 454         .num_resources  = ARRAY_SIZE(s3c2410_dma_resource),
 455         .resource       = s3c2410_dma_resource,
 456         .dev    = {
 457                 .platform_data  = &s3c2440_dma_platdata,
 458         },
 459 };
 460 #endif
 461
 462 #if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
 463 static struct resource s3c2443_dma_resource[] = {
 464         [0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA),
 465         [1] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA0),
 466         [2] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA1),
 467         [3] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA2),
 468         [4] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA3),
 469         [5] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA4),
 470         [6] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA5),
 471 };
 472
 473 static struct s3c24xx_dma_channel s3c2443_dma_channels[DMACH_MAX] = {
 474         [DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 },
 475         [DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 },
 476         [DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 },
 477         [DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 },
 478         [DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 },
 479         [DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 },
 480         [DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 },
 481         [DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 },
 482         [DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 },
 483         [DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 },
 484         [DMACH_UART3] = { S3C24XX_DMA_APB, true, 25 },
 485         [DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 },
 486         [DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 },
 487         [DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 },
 488         [DMACH_UART3_SRC2] = { S3C24XX_DMA_APB, true, 26 },
 489         [DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 },
 490         [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 },
 491         [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 },
 492         [DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, 28 },
 493         [DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, 27 },
 494         [DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, 29 },
 495 };
 496
 497 static struct s3c24xx_dma_platdata s3c2443_dma_platdata = {
 498         .num_phy_channels = 6,
 499         .channels = s3c2443_dma_channels,
 500         .num_channels = DMACH_MAX,
 501 };
 502
 503 struct platform_device s3c2443_device_dma = {
 504         .name           = "s3c2443-dma",
 505         .id             = 0,
 506         .num_resources  = ARRAY_SIZE(s3c2443_dma_resource),
 507         .resource       = s3c2443_dma_resource,
 508         .dev    = {
 509                 .platform_data  = &s3c2443_dma_platdata,
 510         },
 511 };
 512 #endif
 513
 514 #if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2410)
 515 void __init s3c2410_init_clocks(int xtal)
 516 {
 517         s3c2410_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
 518         samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
 519 }
 520 #endif
 521
 522 #ifdef CONFIG_CPU_S3C2412
 523 void __init s3c2412_init_clocks(int xtal)
 524 {
 525         s3c2412_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
 526 }
 527 #endif
 528
 529 #ifdef CONFIG_CPU_S3C2416
 530 void __init s3c2416_init_clocks(int xtal)
 531 {
 532         s3c2443_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
 533 }
 534 #endif
 535
 536 #if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2440)
 537 void __init s3c2440_init_clocks(int xtal)
 538 {
 539         s3c2410_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR);
 540         samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
 541 }
 542 #endif
 543
 544 #if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2442)
 545 void __init s3c2442_init_clocks(int xtal)
 546 {
 547         s3c2410_common_clk_init(NULL, xtal, 2, S3C24XX_VA_CLKPWR);
 548         samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
 549 }
 550 #endif
 551
 552 #ifdef CONFIG_CPU_S3C2443
 553 void __init s3c2443_init_clocks(int xtal)
 554 {
 555         s3c2443_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR);
 556 }
 557 #endif
 558
 559 #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2440) || \
 560         defined(CONFIG_CPU_S3C2442)
 561 static struct resource s3c2410_dclk_resource[] = {
 562         [0] = DEFINE_RES_MEM(0x56000084, 0x4),
 563 };
 564
 565 struct platform_device s3c2410_device_dclk = {
 566         .name           = "s3c2410-dclk",
 567         .id             = 0,
 568         .num_resources  = ARRAY_SIZE(s3c2410_dclk_resource),
 569         .resource       = s3c2410_dclk_resource,
 570 };
 571 #endif