1 /* linux/arch/arm/mach-s3c2412/dma.c
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2412 DMA selection
8 * http://armlinux.simtec.co.uk/
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/device.h>
18 #include <linux/serial_core.h>
23 #include <plat/dma-s3c24xx.h>
26 #include <plat/regs-serial.h>
27 #include <mach/regs-gpio.h>
28 #include <plat/regs-ac97.h>
29 #include <plat/regs-dma.h>
30 #include <mach/regs-lcd.h>
31 #include <plat/regs-iis.h>
32 #include <plat/regs-spi.h>
34 #define MAP(x) { (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID }
36 static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings
[] = {
39 .channels
= MAP(S3C2412_DMAREQSEL_XDREQ0
),
40 .channels_rx
= MAP(S3C2412_DMAREQSEL_XDREQ0
),
44 .channels
= MAP(S3C2412_DMAREQSEL_XDREQ1
),
45 .channels_rx
= MAP(S3C2412_DMAREQSEL_XDREQ1
),
49 .channels
= MAP(S3C2412_DMAREQSEL_SDI
),
50 .channels_rx
= MAP(S3C2412_DMAREQSEL_SDI
),
54 .channels
= MAP(S3C2412_DMAREQSEL_SPI0TX
),
55 .channels_rx
= MAP(S3C2412_DMAREQSEL_SPI0RX
),
59 .channels
= MAP(S3C2412_DMAREQSEL_SPI1TX
),
60 .channels_rx
= MAP(S3C2412_DMAREQSEL_SPI1RX
),
64 .channels
= MAP(S3C2412_DMAREQSEL_UART0_0
),
65 .channels_rx
= MAP(S3C2412_DMAREQSEL_UART0_0
),
69 .channels
= MAP(S3C2412_DMAREQSEL_UART1_0
),
70 .channels_rx
= MAP(S3C2412_DMAREQSEL_UART1_0
),
74 .channels
= MAP(S3C2412_DMAREQSEL_UART2_0
),
75 .channels_rx
= MAP(S3C2412_DMAREQSEL_UART2_0
),
77 [DMACH_UART0_SRC2
] = {
79 .channels
= MAP(S3C2412_DMAREQSEL_UART0_1
),
80 .channels_rx
= MAP(S3C2412_DMAREQSEL_UART0_1
),
82 [DMACH_UART1_SRC2
] = {
84 .channels
= MAP(S3C2412_DMAREQSEL_UART1_1
),
85 .channels_rx
= MAP(S3C2412_DMAREQSEL_UART1_1
),
87 [DMACH_UART2_SRC2
] = {
89 .channels
= MAP(S3C2412_DMAREQSEL_UART2_1
),
90 .channels_rx
= MAP(S3C2412_DMAREQSEL_UART2_1
),
94 .channels
= MAP(S3C2412_DMAREQSEL_TIMER
),
95 .channels_rx
= MAP(S3C2412_DMAREQSEL_TIMER
),
99 .channels
= MAP(S3C2412_DMAREQSEL_I2SRX
),
100 .channels_rx
= MAP(S3C2412_DMAREQSEL_I2SRX
),
104 .channels
= MAP(S3C2412_DMAREQSEL_I2STX
),
105 .channels_rx
= MAP(S3C2412_DMAREQSEL_I2STX
),
109 .channels
= MAP(S3C2412_DMAREQSEL_USBEP1
),
110 .channels_rx
= MAP(S3C2412_DMAREQSEL_USBEP1
),
114 .channels
= MAP(S3C2412_DMAREQSEL_USBEP2
),
115 .channels_rx
= MAP(S3C2412_DMAREQSEL_USBEP2
),
119 .channels
= MAP(S3C2412_DMAREQSEL_USBEP3
),
120 .channels_rx
= MAP(S3C2412_DMAREQSEL_USBEP3
),
124 .channels
= MAP(S3C2412_DMAREQSEL_USBEP4
),
125 .channels_rx
= MAP(S3C2412_DMAREQSEL_USBEP4
),
129 static void s3c2412_dma_direction(struct s3c2410_dma_chan
*chan
,
130 struct s3c24xx_dma_map
*map
,
131 enum dma_data_direction dir
)
135 if (dir
== DMA_FROM_DEVICE
)
136 chsel
= map
->channels_rx
[0];
138 chsel
= map
->channels
[0];
140 chsel
&= ~DMA_CH_VALID
;
141 chsel
|= S3C2412_DMAREQSEL_HW
;
143 writel(chsel
, chan
->regs
+ S3C2412_DMA_DMAREQSEL
);
146 static void s3c2412_dma_select(struct s3c2410_dma_chan
*chan
,
147 struct s3c24xx_dma_map
*map
)
149 s3c2412_dma_direction(chan
, map
, chan
->source
);
152 static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel
= {
153 .select
= s3c2412_dma_select
,
154 .direction
= s3c2412_dma_direction
,
156 .map
= s3c2412_dma_mappings
,
157 .map_size
= ARRAY_SIZE(s3c2412_dma_mappings
),
160 static int __init
s3c2412_dma_add(struct device
*dev
,
161 struct subsys_interface
*sif
)
164 return s3c24xx_dma_init_map(&s3c2412_dma_sel
);
167 static struct subsys_interface s3c2412_dma_interface
= {
168 .name
= "s3c2412_dma",
169 .subsys
= &s3c2412_subsys
,
170 .add_dev
= s3c2412_dma_add
,
173 static int __init
s3c2412_dma_init(void)
175 return subsys_interface_register(&s3c2412_dma_interface
);
178 arch_initcall(s3c2412_dma_init
);