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Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
[deliverable/linux.git] / arch / arm / mach-s3c24xx / irq.c
1 /*
2 * S3C24XX IRQ handling
3 *
4 * Copyright (c) 2003-2004 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19 #include <linux/init.h>
20 #include <linux/slab.h>
21 #include <linux/module.h>
22 #include <linux/io.h>
23 #include <linux/err.h>
24 #include <linux/interrupt.h>
25 #include <linux/ioport.h>
26 #include <linux/device.h>
27 #include <linux/irqdomain.h>
28 #include <linux/irqchip/chained_irq.h>
29
30 #include <asm/mach/irq.h>
31
32 #include <mach/regs-irq.h>
33 #include <mach/regs-gpio.h>
34
35 #include <plat/cpu.h>
36 #include <plat/regs-irqtype.h>
37 #include <plat/pm.h>
38
39 #define S3C_IRQTYPE_NONE 0
40 #define S3C_IRQTYPE_EINT 1
41 #define S3C_IRQTYPE_EDGE 2
42 #define S3C_IRQTYPE_LEVEL 3
43
44 struct s3c_irq_data {
45 unsigned int type;
46 unsigned long parent_irq;
47
48 /* data gets filled during init */
49 struct s3c_irq_intc *intc;
50 unsigned long sub_bits;
51 struct s3c_irq_intc *sub_intc;
52 };
53
54 /*
55 * Sructure holding the controller data
56 * @reg_pending register holding pending irqs
57 * @reg_intpnd special register intpnd in main intc
58 * @reg_mask mask register
59 * @domain irq_domain of the controller
60 * @parent parent controller for ext and sub irqs
61 * @irqs irq-data, always s3c_irq_data[32]
62 */
63 struct s3c_irq_intc {
64 void __iomem *reg_pending;
65 void __iomem *reg_intpnd;
66 void __iomem *reg_mask;
67 struct irq_domain *domain;
68 struct s3c_irq_intc *parent;
69 struct s3c_irq_data *irqs;
70 };
71
72 static void s3c_irq_mask(struct irq_data *data)
73 {
74 struct s3c_irq_intc *intc = data->domain->host_data;
75 struct s3c_irq_intc *parent_intc = intc->parent;
76 struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq];
77 struct s3c_irq_data *parent_data;
78 unsigned long mask;
79 unsigned int irqno;
80
81 mask = __raw_readl(intc->reg_mask);
82 mask |= (1UL << data->hwirq);
83 __raw_writel(mask, intc->reg_mask);
84
85 if (parent_intc && irq_data->parent_irq) {
86 parent_data = &parent_intc->irqs[irq_data->parent_irq];
87
88 /* check to see if we need to mask the parent IRQ */
89 if ((mask & parent_data->sub_bits) == parent_data->sub_bits) {
90 irqno = irq_find_mapping(parent_intc->domain,
91 irq_data->parent_irq);
92 s3c_irq_mask(irq_get_irq_data(irqno));
93 }
94 }
95 }
96
97 static void s3c_irq_unmask(struct irq_data *data)
98 {
99 struct s3c_irq_intc *intc = data->domain->host_data;
100 struct s3c_irq_intc *parent_intc = intc->parent;
101 struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq];
102 unsigned long mask;
103 unsigned int irqno;
104
105 mask = __raw_readl(intc->reg_mask);
106 mask &= ~(1UL << data->hwirq);
107 __raw_writel(mask, intc->reg_mask);
108
109 if (parent_intc && irq_data->parent_irq) {
110 irqno = irq_find_mapping(parent_intc->domain,
111 irq_data->parent_irq);
112 s3c_irq_unmask(irq_get_irq_data(irqno));
113 }
114 }
115
116 static inline void s3c_irq_ack(struct irq_data *data)
117 {
118 struct s3c_irq_intc *intc = data->domain->host_data;
119 unsigned long bitval = 1UL << data->hwirq;
120
121 __raw_writel(bitval, intc->reg_pending);
122 if (intc->reg_intpnd)
123 __raw_writel(bitval, intc->reg_intpnd);
124 }
125
126 static int s3c_irqext_type_set(void __iomem *gpcon_reg,
127 void __iomem *extint_reg,
128 unsigned long gpcon_offset,
129 unsigned long extint_offset,
130 unsigned int type)
131 {
132 unsigned long newvalue = 0, value;
133
134 /* Set the GPIO to external interrupt mode */
135 value = __raw_readl(gpcon_reg);
136 value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
137 __raw_writel(value, gpcon_reg);
138
139 /* Set the external interrupt to pointed trigger type */
140 switch (type)
141 {
142 case IRQ_TYPE_NONE:
143 pr_warn("No edge setting!\n");
144 break;
145
146 case IRQ_TYPE_EDGE_RISING:
147 newvalue = S3C2410_EXTINT_RISEEDGE;
148 break;
149
150 case IRQ_TYPE_EDGE_FALLING:
151 newvalue = S3C2410_EXTINT_FALLEDGE;
152 break;
153
154 case IRQ_TYPE_EDGE_BOTH:
155 newvalue = S3C2410_EXTINT_BOTHEDGE;
156 break;
157
158 case IRQ_TYPE_LEVEL_LOW:
159 newvalue = S3C2410_EXTINT_LOWLEV;
160 break;
161
162 case IRQ_TYPE_LEVEL_HIGH:
163 newvalue = S3C2410_EXTINT_HILEV;
164 break;
165
166 default:
167 pr_err("No such irq type %d", type);
168 return -EINVAL;
169 }
170
171 value = __raw_readl(extint_reg);
172 value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
173 __raw_writel(value, extint_reg);
174
175 return 0;
176 }
177
178 static int s3c_irqext_type(struct irq_data *data, unsigned int type)
179 {
180 void __iomem *extint_reg;
181 void __iomem *gpcon_reg;
182 unsigned long gpcon_offset, extint_offset;
183
184 if ((data->hwirq >= 4) && (data->hwirq <= 7)) {
185 gpcon_reg = S3C2410_GPFCON;
186 extint_reg = S3C24XX_EXTINT0;
187 gpcon_offset = (data->hwirq) * 2;
188 extint_offset = (data->hwirq) * 4;
189 } else if ((data->hwirq >= 8) && (data->hwirq <= 15)) {
190 gpcon_reg = S3C2410_GPGCON;
191 extint_reg = S3C24XX_EXTINT1;
192 gpcon_offset = (data->hwirq - 8) * 2;
193 extint_offset = (data->hwirq - 8) * 4;
194 } else if ((data->hwirq >= 16) && (data->hwirq <= 23)) {
195 gpcon_reg = S3C2410_GPGCON;
196 extint_reg = S3C24XX_EXTINT2;
197 gpcon_offset = (data->hwirq - 8) * 2;
198 extint_offset = (data->hwirq - 16) * 4;
199 } else {
200 return -EINVAL;
201 }
202
203 return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
204 extint_offset, type);
205 }
206
207 static int s3c_irqext0_type(struct irq_data *data, unsigned int type)
208 {
209 void __iomem *extint_reg;
210 void __iomem *gpcon_reg;
211 unsigned long gpcon_offset, extint_offset;
212
213 if ((data->hwirq >= 0) && (data->hwirq <= 3)) {
214 gpcon_reg = S3C2410_GPFCON;
215 extint_reg = S3C24XX_EXTINT0;
216 gpcon_offset = (data->hwirq) * 2;
217 extint_offset = (data->hwirq) * 4;
218 } else {
219 return -EINVAL;
220 }
221
222 return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
223 extint_offset, type);
224 }
225
226 static struct irq_chip s3c_irq_chip = {
227 .name = "s3c",
228 .irq_ack = s3c_irq_ack,
229 .irq_mask = s3c_irq_mask,
230 .irq_unmask = s3c_irq_unmask,
231 .irq_set_wake = s3c_irq_wake
232 };
233
234 static struct irq_chip s3c_irq_level_chip = {
235 .name = "s3c-level",
236 .irq_mask = s3c_irq_mask,
237 .irq_unmask = s3c_irq_unmask,
238 .irq_ack = s3c_irq_ack,
239 };
240
241 static struct irq_chip s3c_irqext_chip = {
242 .name = "s3c-ext",
243 .irq_mask = s3c_irq_mask,
244 .irq_unmask = s3c_irq_unmask,
245 .irq_ack = s3c_irq_ack,
246 .irq_set_type = s3c_irqext_type,
247 .irq_set_wake = s3c_irqext_wake
248 };
249
250 static struct irq_chip s3c_irq_eint0t4 = {
251 .name = "s3c-ext0",
252 .irq_ack = s3c_irq_ack,
253 .irq_mask = s3c_irq_mask,
254 .irq_unmask = s3c_irq_unmask,
255 .irq_set_wake = s3c_irq_wake,
256 .irq_set_type = s3c_irqext0_type,
257 };
258
259 static void s3c_irq_demux(unsigned int irq, struct irq_desc *desc)
260 {
261 struct irq_chip *chip = irq_desc_get_chip(desc);
262 struct s3c_irq_intc *intc = desc->irq_data.domain->host_data;
263 struct s3c_irq_data *irq_data = &intc->irqs[desc->irq_data.hwirq];
264 struct s3c_irq_intc *sub_intc = irq_data->sub_intc;
265 unsigned long src;
266 unsigned long msk;
267 unsigned int n;
268
269 chained_irq_enter(chip, desc);
270
271 src = __raw_readl(sub_intc->reg_pending);
272 msk = __raw_readl(sub_intc->reg_mask);
273
274 src &= ~msk;
275 src &= irq_data->sub_bits;
276
277 while (src) {
278 n = __ffs(src);
279 src &= ~(1 << n);
280 generic_handle_irq(irq_find_mapping(sub_intc->domain, n));
281 }
282
283 chained_irq_exit(chip, desc);
284 }
285
286 #ifdef CONFIG_FIQ
287 /**
288 * s3c24xx_set_fiq - set the FIQ routing
289 * @irq: IRQ number to route to FIQ on processor.
290 * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
291 *
292 * Change the state of the IRQ to FIQ routing depending on @irq and @on. If
293 * @on is true, the @irq is checked to see if it can be routed and the
294 * interrupt controller updated to route the IRQ. If @on is false, the FIQ
295 * routing is cleared, regardless of which @irq is specified.
296 */
297 int s3c24xx_set_fiq(unsigned int irq, bool on)
298 {
299 u32 intmod;
300 unsigned offs;
301
302 if (on) {
303 offs = irq - FIQ_START;
304 if (offs > 31)
305 return -EINVAL;
306
307 intmod = 1 << offs;
308 } else {
309 intmod = 0;
310 }
311
312 __raw_writel(intmod, S3C2410_INTMOD);
313 return 0;
314 }
315
316 EXPORT_SYMBOL_GPL(s3c24xx_set_fiq);
317 #endif
318
319 static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq,
320 irq_hw_number_t hw)
321 {
322 struct s3c_irq_intc *intc = h->host_data;
323 struct s3c_irq_data *irq_data = &intc->irqs[hw];
324 struct s3c_irq_intc *parent_intc;
325 struct s3c_irq_data *parent_irq_data;
326 unsigned int irqno;
327
328 if (!intc) {
329 pr_err("irq-s3c24xx: no controller found for hwirq %lu\n", hw);
330 return -EINVAL;
331 }
332
333 if (!irq_data) {
334 pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n", hw);
335 return -EINVAL;
336 }
337
338 /* attach controller pointer to irq_data */
339 irq_data->intc = intc;
340
341 /* set handler and flags */
342 switch (irq_data->type) {
343 case S3C_IRQTYPE_NONE:
344 return 0;
345 case S3C_IRQTYPE_EINT:
346 if (irq_data->parent_irq)
347 irq_set_chip_and_handler(virq, &s3c_irqext_chip,
348 handle_edge_irq);
349 else
350 irq_set_chip_and_handler(virq, &s3c_irq_eint0t4,
351 handle_edge_irq);
352 break;
353 case S3C_IRQTYPE_EDGE:
354 if (irq_data->parent_irq ||
355 intc->reg_pending == S3C2416_SRCPND2)
356 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
357 handle_edge_irq);
358 else
359 irq_set_chip_and_handler(virq, &s3c_irq_chip,
360 handle_edge_irq);
361 break;
362 case S3C_IRQTYPE_LEVEL:
363 if (irq_data->parent_irq)
364 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
365 handle_level_irq);
366 else
367 irq_set_chip_and_handler(virq, &s3c_irq_chip,
368 handle_level_irq);
369 break;
370 default:
371 pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type);
372 return -EINVAL;
373 }
374 set_irq_flags(virq, IRQF_VALID);
375
376 if (irq_data->parent_irq) {
377 parent_intc = intc->parent;
378 if (!parent_intc) {
379 pr_err("irq-s3c24xx: no parent controller found for hwirq %lu\n",
380 hw);
381 goto err;
382 }
383
384 parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
385 if (!irq_data) {
386 pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n",
387 hw);
388 goto err;
389 }
390
391 parent_irq_data->sub_intc = intc;
392 parent_irq_data->sub_bits |= (1UL << hw);
393
394 /* attach the demuxer to the parent irq */
395 irqno = irq_find_mapping(parent_intc->domain,
396 irq_data->parent_irq);
397 if (!irqno) {
398 pr_err("irq-s3c24xx: could not find mapping for parent irq %lu\n",
399 irq_data->parent_irq);
400 goto err;
401 }
402 irq_set_chained_handler(irqno, s3c_irq_demux);
403 }
404
405 return 0;
406
407 err:
408 set_irq_flags(virq, 0);
409
410 /* the only error can result from bad mapping data*/
411 return -EINVAL;
412 }
413
414 static struct irq_domain_ops s3c24xx_irq_ops = {
415 .map = s3c24xx_irq_map,
416 .xlate = irq_domain_xlate_twocell,
417 };
418
419 static void s3c24xx_clear_intc(struct s3c_irq_intc *intc)
420 {
421 void __iomem *reg_source;
422 unsigned long pend;
423 unsigned long last;
424 int i;
425
426 /* if intpnd is set, read the next pending irq from there */
427 reg_source = intc->reg_intpnd ? intc->reg_intpnd : intc->reg_pending;
428
429 last = 0;
430 for (i = 0; i < 4; i++) {
431 pend = __raw_readl(reg_source);
432
433 if (pend == 0 || pend == last)
434 break;
435
436 __raw_writel(pend, intc->reg_pending);
437 if (intc->reg_intpnd)
438 __raw_writel(pend, intc->reg_intpnd);
439
440 pr_info("irq: clearing pending status %08x\n", (int)pend);
441 last = pend;
442 }
443 }
444
445 struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np,
446 struct s3c_irq_data *irq_data,
447 struct s3c_irq_intc *parent,
448 unsigned long address)
449 {
450 struct s3c_irq_intc *intc;
451 void __iomem *base = (void *)0xf6000000; /* static mapping */
452 int irq_num;
453 int irq_start;
454 int irq_offset;
455 int ret;
456
457 intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
458 if (!intc)
459 return ERR_PTR(-ENOMEM);
460
461 intc->irqs = irq_data;
462
463 if (parent)
464 intc->parent = parent;
465
466 /* select the correct data for the controller.
467 * Need to hard code the irq num start and offset
468 * to preserve the static mapping for now
469 */
470 switch (address) {
471 case 0x4a000000:
472 pr_debug("irq: found main intc\n");
473 intc->reg_pending = base;
474 intc->reg_mask = base + 0x08;
475 intc->reg_intpnd = base + 0x10;
476 irq_num = 32;
477 irq_start = S3C2410_IRQ(0);
478 irq_offset = 0;
479 break;
480 case 0x4a000018:
481 pr_debug("irq: found subintc\n");
482 intc->reg_pending = base + 0x18;
483 intc->reg_mask = base + 0x1c;
484 irq_num = 29;
485 irq_start = S3C2410_IRQSUB(0);
486 irq_offset = 0;
487 break;
488 case 0x4a000040:
489 pr_debug("irq: found intc2\n");
490 intc->reg_pending = base + 0x40;
491 intc->reg_mask = base + 0x48;
492 intc->reg_intpnd = base + 0x50;
493 irq_num = 8;
494 irq_start = S3C2416_IRQ(0);
495 irq_offset = 0;
496 break;
497 case 0x560000a4:
498 pr_debug("irq: found eintc\n");
499 base = (void *)0xfd000000;
500
501 intc->reg_mask = base + 0xa4;
502 intc->reg_pending = base + 0xa8;
503 irq_num = 20;
504 irq_start = S3C2410_IRQ(32);
505 irq_offset = 4;
506 break;
507 default:
508 pr_err("irq: unsupported controller address\n");
509 ret = -EINVAL;
510 goto err;
511 }
512
513 /* now that all the data is complete, init the irq-domain */
514 s3c24xx_clear_intc(intc);
515 intc->domain = irq_domain_add_legacy(np, irq_num, irq_start,
516 irq_offset, &s3c24xx_irq_ops,
517 intc);
518 if (!intc->domain) {
519 pr_err("irq: could not create irq-domain\n");
520 ret = -EINVAL;
521 goto err;
522 }
523
524 return intc;
525
526 err:
527 kfree(intc);
528 return ERR_PTR(ret);
529 }
530
531 /* s3c24xx_init_irq
532 *
533 * Initialise S3C2410 IRQ system
534 */
535
536 static struct s3c_irq_data init_base[32] = {
537 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
538 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
539 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
540 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
541 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
542 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
543 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
544 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
545 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
546 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
547 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
548 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
549 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
550 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
551 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
552 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
553 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
554 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
555 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
556 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
557 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
558 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
559 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
560 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
561 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
562 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
563 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
564 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
565 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
566 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
567 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
568 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
569 };
570
571 static struct s3c_irq_data init_eint[32] = {
572 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
573 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
574 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
575 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
576 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
577 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
578 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
579 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
580 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
581 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
582 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
583 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
584 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
585 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
586 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
587 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
588 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
589 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
590 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
591 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
592 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
593 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
594 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
595 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
596 };
597
598 static struct s3c_irq_data init_subint[32] = {
599 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
600 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
601 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
602 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
603 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
604 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
605 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
606 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
607 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
608 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
609 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
610 };
611
612 void __init s3c24xx_init_irq(void)
613 {
614 struct s3c_irq_intc *main_intc;
615
616 #ifdef CONFIG_FIQ
617 init_FIQ(FIQ_START);
618 #endif
619
620 main_intc = s3c24xx_init_intc(NULL, &init_base[0], NULL, 0x4a000000);
621 if (IS_ERR(main_intc)) {
622 pr_err("irq: could not create main interrupt controller\n");
623 return;
624 }
625
626 s3c24xx_init_intc(NULL, &init_subint[0], main_intc, 0x4a000018);
627 s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
628 }
629
630 #ifdef CONFIG_CPU_S3C2416
631 static struct s3c_irq_data init_s3c2416base[32] = {
632 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
633 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
634 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
635 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
636 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
637 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
638 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
639 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
640 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
641 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
642 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
643 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
644 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
645 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
646 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
647 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
648 { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
649 { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
650 { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
651 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
652 { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
653 { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
654 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
655 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
656 { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
657 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
658 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
659 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
660 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
661 { .type = S3C_IRQTYPE_NONE, },
662 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
663 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
664 };
665
666 static struct s3c_irq_data init_s3c2416subint[32] = {
667 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
668 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
669 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
670 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
671 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
672 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
673 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
674 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
675 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
676 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
677 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
678 { .type = S3C_IRQTYPE_NONE }, /* reserved */
679 { .type = S3C_IRQTYPE_NONE }, /* reserved */
680 { .type = S3C_IRQTYPE_NONE }, /* reserved */
681 { .type = S3C_IRQTYPE_NONE }, /* reserved */
682 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
683 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
684 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
685 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
686 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
687 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
688 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
689 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
690 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
691 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
692 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
693 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
694 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
695 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
696 };
697
698 static struct s3c_irq_data init_s3c2416_second[32] = {
699 { .type = S3C_IRQTYPE_EDGE }, /* 2D */
700 { .type = S3C_IRQTYPE_EDGE }, /* IIC1 */
701 { .type = S3C_IRQTYPE_NONE }, /* reserved */
702 { .type = S3C_IRQTYPE_NONE }, /* reserved */
703 { .type = S3C_IRQTYPE_EDGE }, /* PCM0 */
704 { .type = S3C_IRQTYPE_EDGE }, /* PCM1 */
705 { .type = S3C_IRQTYPE_EDGE }, /* I2S0 */
706 { .type = S3C_IRQTYPE_EDGE }, /* I2S1 */
707 };
708
709 void __init s3c2416_init_irq(void)
710 {
711 struct s3c_irq_intc *main_intc;
712
713 pr_info("S3C2416: IRQ Support\n");
714
715 #ifdef CONFIG_FIQ
716 init_FIQ(FIQ_START);
717 #endif
718
719 main_intc = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL, 0x4a000000);
720 if (IS_ERR(main_intc)) {
721 pr_err("irq: could not create main interrupt controller\n");
722 return;
723 }
724
725 s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
726 s3c24xx_init_intc(NULL, &init_s3c2416subint[0], main_intc, 0x4a000018);
727
728 s3c24xx_init_intc(NULL, &init_s3c2416_second[0], NULL, 0x4a000040);
729 }
730
731 #endif
732
733 #ifdef CONFIG_CPU_S3C2443
734 static struct s3c_irq_data init_s3c2443base[32] = {
735 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
736 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
737 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
738 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
739 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
740 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
741 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
742 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
743 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
744 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
745 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
746 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
747 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
748 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
749 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
750 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
751 { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
752 { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
753 { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
754 { .type = S3C_IRQTYPE_EDGE, }, /* CFON */
755 { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
756 { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
757 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
758 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
759 { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
760 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
761 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
762 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
763 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
764 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
765 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
766 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
767 };
768
769
770 static struct s3c_irq_data init_s3c2443subint[32] = {
771 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
772 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
773 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
774 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
775 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
776 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
777 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
778 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
779 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
780 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
781 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
782 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
783 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
784 { .type = S3C_IRQTYPE_NONE }, /* reserved */
785 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD1 */
786 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
787 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
788 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
789 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
790 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
791 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
792 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
793 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
794 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
795 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
796 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
797 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
798 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
799 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
800 };
801
802 void __init s3c2443_init_irq(void)
803 {
804 struct s3c_irq_intc *main_intc;
805
806 pr_info("S3C2443: IRQ Support\n");
807
808 #ifdef CONFIG_FIQ
809 init_FIQ(FIQ_START);
810 #endif
811
812 main_intc = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL, 0x4a000000);
813 if (IS_ERR(main_intc)) {
814 pr_err("irq: could not create main interrupt controller\n");
815 return;
816 }
817
818 s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
819 s3c24xx_init_intc(NULL, &init_s3c2443subint[0], main_intc, 0x4a000018);
820 }
821 #endif
Linux kernel - Deliverables
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