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arm: Move chained_irq_(enter|exit) to a generic file
[deliverable/linux.git] / arch / arm / mach-s3c24xx / irq.c
1 /*
2 * S3C24XX IRQ handling
3 *
4 * Copyright (c) 2003-2004 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19 #include <linux/init.h>
20 #include <linux/slab.h>
21 #include <linux/module.h>
22 #include <linux/io.h>
23 #include <linux/err.h>
24 #include <linux/interrupt.h>
25 #include <linux/ioport.h>
26 #include <linux/device.h>
27 #include <linux/irqdomain.h>
28 #include <linux/irqchip/chained_irq.h>
29
30 #include <asm/mach/irq.h>
31
32 #include <mach/regs-irq.h>
33 #include <mach/regs-gpio.h>
34
35 #include <plat/cpu.h>
36 #include <plat/regs-irqtype.h>
37 #include <plat/pm.h>
38 #include <plat/irq.h>
39
40 #define S3C_IRQTYPE_NONE 0
41 #define S3C_IRQTYPE_EINT 1
42 #define S3C_IRQTYPE_EDGE 2
43 #define S3C_IRQTYPE_LEVEL 3
44
45 struct s3c_irq_data {
46 unsigned int type;
47 unsigned long parent_irq;
48
49 /* data gets filled during init */
50 struct s3c_irq_intc *intc;
51 unsigned long sub_bits;
52 struct s3c_irq_intc *sub_intc;
53 };
54
55 /*
56 * Sructure holding the controller data
57 * @reg_pending register holding pending irqs
58 * @reg_intpnd special register intpnd in main intc
59 * @reg_mask mask register
60 * @domain irq_domain of the controller
61 * @parent parent controller for ext and sub irqs
62 * @irqs irq-data, always s3c_irq_data[32]
63 */
64 struct s3c_irq_intc {
65 void __iomem *reg_pending;
66 void __iomem *reg_intpnd;
67 void __iomem *reg_mask;
68 struct irq_domain *domain;
69 struct s3c_irq_intc *parent;
70 struct s3c_irq_data *irqs;
71 };
72
73 static void s3c_irq_mask(struct irq_data *data)
74 {
75 struct s3c_irq_intc *intc = data->domain->host_data;
76 struct s3c_irq_intc *parent_intc = intc->parent;
77 struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq];
78 struct s3c_irq_data *parent_data;
79 unsigned long mask;
80 unsigned int irqno;
81
82 mask = __raw_readl(intc->reg_mask);
83 mask |= (1UL << data->hwirq);
84 __raw_writel(mask, intc->reg_mask);
85
86 if (parent_intc && irq_data->parent_irq) {
87 parent_data = &parent_intc->irqs[irq_data->parent_irq];
88
89 /* check to see if we need to mask the parent IRQ */
90 if ((mask & parent_data->sub_bits) == parent_data->sub_bits) {
91 irqno = irq_find_mapping(parent_intc->domain,
92 irq_data->parent_irq);
93 s3c_irq_mask(irq_get_irq_data(irqno));
94 }
95 }
96 }
97
98 static void s3c_irq_unmask(struct irq_data *data)
99 {
100 struct s3c_irq_intc *intc = data->domain->host_data;
101 struct s3c_irq_intc *parent_intc = intc->parent;
102 struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq];
103 unsigned long mask;
104 unsigned int irqno;
105
106 mask = __raw_readl(intc->reg_mask);
107 mask &= ~(1UL << data->hwirq);
108 __raw_writel(mask, intc->reg_mask);
109
110 if (parent_intc && irq_data->parent_irq) {
111 irqno = irq_find_mapping(parent_intc->domain,
112 irq_data->parent_irq);
113 s3c_irq_unmask(irq_get_irq_data(irqno));
114 }
115 }
116
117 static inline void s3c_irq_ack(struct irq_data *data)
118 {
119 struct s3c_irq_intc *intc = data->domain->host_data;
120 unsigned long bitval = 1UL << data->hwirq;
121
122 __raw_writel(bitval, intc->reg_pending);
123 if (intc->reg_intpnd)
124 __raw_writel(bitval, intc->reg_intpnd);
125 }
126
127 static int s3c_irqext_type_set(void __iomem *gpcon_reg,
128 void __iomem *extint_reg,
129 unsigned long gpcon_offset,
130 unsigned long extint_offset,
131 unsigned int type)
132 {
133 unsigned long newvalue = 0, value;
134
135 /* Set the GPIO to external interrupt mode */
136 value = __raw_readl(gpcon_reg);
137 value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
138 __raw_writel(value, gpcon_reg);
139
140 /* Set the external interrupt to pointed trigger type */
141 switch (type)
142 {
143 case IRQ_TYPE_NONE:
144 pr_warn("No edge setting!\n");
145 break;
146
147 case IRQ_TYPE_EDGE_RISING:
148 newvalue = S3C2410_EXTINT_RISEEDGE;
149 break;
150
151 case IRQ_TYPE_EDGE_FALLING:
152 newvalue = S3C2410_EXTINT_FALLEDGE;
153 break;
154
155 case IRQ_TYPE_EDGE_BOTH:
156 newvalue = S3C2410_EXTINT_BOTHEDGE;
157 break;
158
159 case IRQ_TYPE_LEVEL_LOW:
160 newvalue = S3C2410_EXTINT_LOWLEV;
161 break;
162
163 case IRQ_TYPE_LEVEL_HIGH:
164 newvalue = S3C2410_EXTINT_HILEV;
165 break;
166
167 default:
168 pr_err("No such irq type %d", type);
169 return -EINVAL;
170 }
171
172 value = __raw_readl(extint_reg);
173 value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
174 __raw_writel(value, extint_reg);
175
176 return 0;
177 }
178
179 /* FIXME: make static when it's out of plat-samsung/irq.h */
180 int s3c_irqext_type(struct irq_data *data, unsigned int type)
181 {
182 void __iomem *extint_reg;
183 void __iomem *gpcon_reg;
184 unsigned long gpcon_offset, extint_offset;
185
186 if ((data->hwirq >= 4) && (data->hwirq <= 7)) {
187 gpcon_reg = S3C2410_GPFCON;
188 extint_reg = S3C24XX_EXTINT0;
189 gpcon_offset = (data->hwirq) * 2;
190 extint_offset = (data->hwirq) * 4;
191 } else if ((data->hwirq >= 8) && (data->hwirq <= 15)) {
192 gpcon_reg = S3C2410_GPGCON;
193 extint_reg = S3C24XX_EXTINT1;
194 gpcon_offset = (data->hwirq - 8) * 2;
195 extint_offset = (data->hwirq - 8) * 4;
196 } else if ((data->hwirq >= 16) && (data->hwirq <= 23)) {
197 gpcon_reg = S3C2410_GPGCON;
198 extint_reg = S3C24XX_EXTINT2;
199 gpcon_offset = (data->hwirq - 8) * 2;
200 extint_offset = (data->hwirq - 16) * 4;
201 } else {
202 return -EINVAL;
203 }
204
205 return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
206 extint_offset, type);
207 }
208
209 static int s3c_irqext0_type(struct irq_data *data, unsigned int type)
210 {
211 void __iomem *extint_reg;
212 void __iomem *gpcon_reg;
213 unsigned long gpcon_offset, extint_offset;
214
215 if ((data->hwirq >= 0) && (data->hwirq <= 3)) {
216 gpcon_reg = S3C2410_GPFCON;
217 extint_reg = S3C24XX_EXTINT0;
218 gpcon_offset = (data->hwirq) * 2;
219 extint_offset = (data->hwirq) * 4;
220 } else {
221 return -EINVAL;
222 }
223
224 return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
225 extint_offset, type);
226 }
227
228 struct irq_chip s3c_irq_chip = {
229 .name = "s3c",
230 .irq_ack = s3c_irq_ack,
231 .irq_mask = s3c_irq_mask,
232 .irq_unmask = s3c_irq_unmask,
233 .irq_set_wake = s3c_irq_wake
234 };
235
236 struct irq_chip s3c_irq_level_chip = {
237 .name = "s3c-level",
238 .irq_mask = s3c_irq_mask,
239 .irq_unmask = s3c_irq_unmask,
240 .irq_ack = s3c_irq_ack,
241 };
242
243 static struct irq_chip s3c_irqext_chip = {
244 .name = "s3c-ext",
245 .irq_mask = s3c_irq_mask,
246 .irq_unmask = s3c_irq_unmask,
247 .irq_ack = s3c_irq_ack,
248 .irq_set_type = s3c_irqext_type,
249 .irq_set_wake = s3c_irqext_wake
250 };
251
252 static struct irq_chip s3c_irq_eint0t4 = {
253 .name = "s3c-ext0",
254 .irq_ack = s3c_irq_ack,
255 .irq_mask = s3c_irq_mask,
256 .irq_unmask = s3c_irq_unmask,
257 .irq_set_wake = s3c_irq_wake,
258 .irq_set_type = s3c_irqext0_type,
259 };
260
261 static void s3c_irq_demux(unsigned int irq, struct irq_desc *desc)
262 {
263 struct irq_chip *chip = irq_desc_get_chip(desc);
264 struct s3c_irq_intc *intc = desc->irq_data.domain->host_data;
265 struct s3c_irq_data *irq_data = &intc->irqs[desc->irq_data.hwirq];
266 struct s3c_irq_intc *sub_intc = irq_data->sub_intc;
267 unsigned long src;
268 unsigned long msk;
269 unsigned int n;
270
271 chained_irq_enter(chip, desc);
272
273 src = __raw_readl(sub_intc->reg_pending);
274 msk = __raw_readl(sub_intc->reg_mask);
275
276 src &= ~msk;
277 src &= irq_data->sub_bits;
278
279 while (src) {
280 n = __ffs(src);
281 src &= ~(1 << n);
282 generic_handle_irq(irq_find_mapping(sub_intc->domain, n));
283 }
284
285 chained_irq_exit(chip, desc);
286 }
287
288 #ifdef CONFIG_FIQ
289 /**
290 * s3c24xx_set_fiq - set the FIQ routing
291 * @irq: IRQ number to route to FIQ on processor.
292 * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
293 *
294 * Change the state of the IRQ to FIQ routing depending on @irq and @on. If
295 * @on is true, the @irq is checked to see if it can be routed and the
296 * interrupt controller updated to route the IRQ. If @on is false, the FIQ
297 * routing is cleared, regardless of which @irq is specified.
298 */
299 int s3c24xx_set_fiq(unsigned int irq, bool on)
300 {
301 u32 intmod;
302 unsigned offs;
303
304 if (on) {
305 offs = irq - FIQ_START;
306 if (offs > 31)
307 return -EINVAL;
308
309 intmod = 1 << offs;
310 } else {
311 intmod = 0;
312 }
313
314 __raw_writel(intmod, S3C2410_INTMOD);
315 return 0;
316 }
317
318 EXPORT_SYMBOL_GPL(s3c24xx_set_fiq);
319 #endif
320
321 static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq,
322 irq_hw_number_t hw)
323 {
324 struct s3c_irq_intc *intc = h->host_data;
325 struct s3c_irq_data *irq_data = &intc->irqs[hw];
326 struct s3c_irq_intc *parent_intc;
327 struct s3c_irq_data *parent_irq_data;
328 unsigned int irqno;
329
330 if (!intc) {
331 pr_err("irq-s3c24xx: no controller found for hwirq %lu\n", hw);
332 return -EINVAL;
333 }
334
335 if (!irq_data) {
336 pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n", hw);
337 return -EINVAL;
338 }
339
340 /* attach controller pointer to irq_data */
341 irq_data->intc = intc;
342
343 /* set handler and flags */
344 switch (irq_data->type) {
345 case S3C_IRQTYPE_NONE:
346 return 0;
347 case S3C_IRQTYPE_EINT:
348 if (irq_data->parent_irq)
349 irq_set_chip_and_handler(virq, &s3c_irqext_chip,
350 handle_edge_irq);
351 else
352 irq_set_chip_and_handler(virq, &s3c_irq_eint0t4,
353 handle_edge_irq);
354 break;
355 case S3C_IRQTYPE_EDGE:
356 if (irq_data->parent_irq ||
357 intc->reg_pending == S3C2416_SRCPND2)
358 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
359 handle_edge_irq);
360 else
361 irq_set_chip_and_handler(virq, &s3c_irq_chip,
362 handle_edge_irq);
363 break;
364 case S3C_IRQTYPE_LEVEL:
365 if (irq_data->parent_irq)
366 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
367 handle_level_irq);
368 else
369 irq_set_chip_and_handler(virq, &s3c_irq_chip,
370 handle_level_irq);
371 break;
372 default:
373 pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type);
374 return -EINVAL;
375 }
376 set_irq_flags(virq, IRQF_VALID);
377
378 if (irq_data->parent_irq) {
379 parent_intc = intc->parent;
380 if (!parent_intc) {
381 pr_err("irq-s3c24xx: no parent controller found for hwirq %lu\n",
382 hw);
383 goto err;
384 }
385
386 parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
387 if (!irq_data) {
388 pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n",
389 hw);
390 goto err;
391 }
392
393 parent_irq_data->sub_intc = intc;
394 parent_irq_data->sub_bits |= (1UL << hw);
395
396 /* attach the demuxer to the parent irq */
397 irqno = irq_find_mapping(parent_intc->domain,
398 irq_data->parent_irq);
399 if (!irqno) {
400 pr_err("irq-s3c24xx: could not find mapping for parent irq %lu\n",
401 irq_data->parent_irq);
402 goto err;
403 }
404 irq_set_chained_handler(irqno, s3c_irq_demux);
405 }
406
407 return 0;
408
409 err:
410 set_irq_flags(virq, 0);
411
412 /* the only error can result from bad mapping data*/
413 return -EINVAL;
414 }
415
416 static struct irq_domain_ops s3c24xx_irq_ops = {
417 .map = s3c24xx_irq_map,
418 .xlate = irq_domain_xlate_twocell,
419 };
420
421 static void s3c24xx_clear_intc(struct s3c_irq_intc *intc)
422 {
423 void __iomem *reg_source;
424 unsigned long pend;
425 unsigned long last;
426 int i;
427
428 /* if intpnd is set, read the next pending irq from there */
429 reg_source = intc->reg_intpnd ? intc->reg_intpnd : intc->reg_pending;
430
431 last = 0;
432 for (i = 0; i < 4; i++) {
433 pend = __raw_readl(reg_source);
434
435 if (pend == 0 || pend == last)
436 break;
437
438 __raw_writel(pend, intc->reg_pending);
439 if (intc->reg_intpnd)
440 __raw_writel(pend, intc->reg_intpnd);
441
442 pr_info("irq: clearing pending status %08x\n", (int)pend);
443 last = pend;
444 }
445 }
446
447 struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np,
448 struct s3c_irq_data *irq_data,
449 struct s3c_irq_intc *parent,
450 unsigned long address)
451 {
452 struct s3c_irq_intc *intc;
453 void __iomem *base = (void *)0xf6000000; /* static mapping */
454 int irq_num;
455 int irq_start;
456 int irq_offset;
457 int ret;
458
459 intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
460 if (!intc)
461 return ERR_PTR(-ENOMEM);
462
463 intc->irqs = irq_data;
464
465 if (parent)
466 intc->parent = parent;
467
468 /* select the correct data for the controller.
469 * Need to hard code the irq num start and offset
470 * to preserve the static mapping for now
471 */
472 switch (address) {
473 case 0x4a000000:
474 pr_debug("irq: found main intc\n");
475 intc->reg_pending = base;
476 intc->reg_mask = base + 0x08;
477 intc->reg_intpnd = base + 0x10;
478 irq_num = 32;
479 irq_start = S3C2410_IRQ(0);
480 irq_offset = 0;
481 break;
482 case 0x4a000018:
483 pr_debug("irq: found subintc\n");
484 intc->reg_pending = base + 0x18;
485 intc->reg_mask = base + 0x1c;
486 irq_num = 29;
487 irq_start = S3C2410_IRQSUB(0);
488 irq_offset = 0;
489 break;
490 case 0x4a000040:
491 pr_debug("irq: found intc2\n");
492 intc->reg_pending = base + 0x40;
493 intc->reg_mask = base + 0x48;
494 intc->reg_intpnd = base + 0x50;
495 irq_num = 8;
496 irq_start = S3C2416_IRQ(0);
497 irq_offset = 0;
498 break;
499 case 0x560000a4:
500 pr_debug("irq: found eintc\n");
501 base = (void *)0xfd000000;
502
503 intc->reg_mask = base + 0xa4;
504 intc->reg_pending = base + 0x08;
505 irq_num = 20;
506 irq_start = S3C2410_IRQ(32);
507 irq_offset = 4;
508 break;
509 default:
510 pr_err("irq: unsupported controller address\n");
511 ret = -EINVAL;
512 goto err;
513 }
514
515 /* now that all the data is complete, init the irq-domain */
516 s3c24xx_clear_intc(intc);
517 intc->domain = irq_domain_add_legacy(np, irq_num, irq_start,
518 irq_offset, &s3c24xx_irq_ops,
519 intc);
520 if (!intc->domain) {
521 pr_err("irq: could not create irq-domain\n");
522 ret = -EINVAL;
523 goto err;
524 }
525
526 return intc;
527
528 err:
529 kfree(intc);
530 return ERR_PTR(ret);
531 }
532
533 /* s3c24xx_init_irq
534 *
535 * Initialise S3C2410 IRQ system
536 */
537
538 static struct s3c_irq_data init_base[32] = {
539 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
540 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
541 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
542 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
543 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
544 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
545 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
546 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
547 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
548 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
549 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
550 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
551 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
552 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
553 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
554 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
555 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
556 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
557 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
558 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
559 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
560 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
561 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
562 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
563 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
564 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
565 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
566 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
567 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
568 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
569 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
570 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
571 };
572
573 static struct s3c_irq_data init_eint[32] = {
574 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
575 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
576 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
577 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
578 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
579 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
580 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
581 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
582 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
583 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
584 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
585 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
586 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
587 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
588 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
589 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
590 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
591 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
592 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
593 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
594 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
595 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
596 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
597 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
598 };
599
600 static struct s3c_irq_data init_subint[32] = {
601 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
602 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
603 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
604 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
605 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
606 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
607 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
608 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
609 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
610 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
611 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
612 };
613
614 void __init s3c24xx_init_irq(void)
615 {
616 struct s3c_irq_intc *main_intc;
617
618 #ifdef CONFIG_FIQ
619 init_FIQ(FIQ_START);
620 #endif
621
622 main_intc = s3c24xx_init_intc(NULL, &init_base[0], NULL, 0x4a000000);
623 if (IS_ERR(main_intc)) {
624 pr_err("irq: could not create main interrupt controller\n");
625 return;
626 }
627
628 s3c24xx_init_intc(NULL, &init_subint[0], main_intc, 0x4a000018);
629 s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
630 }
631
632 #ifdef CONFIG_CPU_S3C2416
633 static struct s3c_irq_data init_s3c2416base[32] = {
634 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
635 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
636 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
637 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
638 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
639 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
640 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
641 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
642 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
643 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
644 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
645 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
646 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
647 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
648 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
649 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
650 { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
651 { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
652 { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
653 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
654 { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
655 { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
656 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
657 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
658 { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
659 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
660 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
661 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
662 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
663 { .type = S3C_IRQTYPE_NONE, },
664 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
665 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
666 };
667
668 static struct s3c_irq_data init_s3c2416subint[32] = {
669 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
670 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
671 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
672 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
673 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
674 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
675 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
676 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
677 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
678 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
679 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
680 { .type = S3C_IRQTYPE_NONE }, /* reserved */
681 { .type = S3C_IRQTYPE_NONE }, /* reserved */
682 { .type = S3C_IRQTYPE_NONE }, /* reserved */
683 { .type = S3C_IRQTYPE_NONE }, /* reserved */
684 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
685 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
686 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
687 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
688 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
689 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
690 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
691 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
692 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
693 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
694 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
695 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
696 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
697 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
698 };
699
700 static struct s3c_irq_data init_s3c2416_second[32] = {
701 { .type = S3C_IRQTYPE_EDGE }, /* 2D */
702 { .type = S3C_IRQTYPE_EDGE }, /* IIC1 */
703 { .type = S3C_IRQTYPE_NONE }, /* reserved */
704 { .type = S3C_IRQTYPE_NONE }, /* reserved */
705 { .type = S3C_IRQTYPE_EDGE }, /* PCM0 */
706 { .type = S3C_IRQTYPE_EDGE }, /* PCM1 */
707 { .type = S3C_IRQTYPE_EDGE }, /* I2S0 */
708 { .type = S3C_IRQTYPE_EDGE }, /* I2S1 */
709 };
710
711 void __init s3c2416_init_irq(void)
712 {
713 struct s3c_irq_intc *main_intc;
714
715 pr_info("S3C2416: IRQ Support\n");
716
717 #ifdef CONFIG_FIQ
718 init_FIQ(FIQ_START);
719 #endif
720
721 main_intc = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL, 0x4a000000);
722 if (IS_ERR(main_intc)) {
723 pr_err("irq: could not create main interrupt controller\n");
724 return;
725 }
726
727 s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
728 s3c24xx_init_intc(NULL, &init_s3c2416subint[0], main_intc, 0x4a000018);
729
730 s3c24xx_init_intc(NULL, &init_s3c2416_second[0], NULL, 0x4a000040);
731 }
732
733 #endif
734
735 #ifdef CONFIG_CPU_S3C2443
736 static struct s3c_irq_data init_s3c2443base[32] = {
737 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
738 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
739 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
740 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
741 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
742 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
743 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
744 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
745 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
746 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
747 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
748 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
749 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
750 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
751 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
752 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
753 { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
754 { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
755 { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
756 { .type = S3C_IRQTYPE_EDGE, }, /* CFON */
757 { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
758 { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
759 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
760 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
761 { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
762 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
763 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
764 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
765 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
766 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
767 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
768 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
769 };
770
771
772 static struct s3c_irq_data init_s3c2443subint[32] = {
773 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
774 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
775 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
776 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
777 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
778 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
779 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
780 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
781 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
782 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
783 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
784 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
785 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
786 { .type = S3C_IRQTYPE_NONE }, /* reserved */
787 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD1 */
788 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
789 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
790 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
791 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
792 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
793 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
794 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
795 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
796 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
797 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
798 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
799 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
800 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
801 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
802 };
803
804 void __init s3c2443_init_irq(void)
805 {
806 struct s3c_irq_intc *main_intc;
807
808 pr_info("S3C2443: IRQ Support\n");
809
810 #ifdef CONFIG_FIQ
811 init_FIQ(FIQ_START);
812 #endif
813
814 main_intc = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL, 0x4a000000);
815 if (IS_ERR(main_intc)) {
816 pr_err("irq: could not create main interrupt controller\n");
817 return;
818 }
819
820 s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
821 s3c24xx_init_intc(NULL, &init_s3c2443subint[0], main_intc, 0x4a000018);
822 }
823 #endif
Linux kernel - Deliverables
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