arch/arm/mach-s3c24xx/s3c2412.c

   1 /*
   2  * Copyright (c) 2006 Simtec Electronics
   3  *      Ben Dooks <ben@simtec.co.uk>
   4  *
   5  * http://armlinux.simtec.co.uk/.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/types.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/list.h>
  16 #include <linux/timer.h>
  17 #include <linux/init.h>
  18 #include <linux/clk.h>
  19 #include <linux/delay.h>
  20 #include <linux/device.h>
  21 #include <linux/syscore_ops.h>
  22 #include <linux/serial_core.h>
  23 #include <linux/serial_s3c.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/io.h>
  26 #include <linux/reboot.h>
  27
  28 #include <asm/mach/arch.h>
  29 #include <asm/mach/map.h>
  30 #include <asm/mach/irq.h>
  31
  32 #include <asm/proc-fns.h>
  33 #include <asm/irq.h>
  34 #include <asm/system_misc.h>
  35
  36 #include <mach/hardware.h>
  37 #include <mach/regs-clock.h>
  38 #include <mach/regs-gpio.h>
  39
  40 #include <plat/cpu.h>
  41 #include <plat/cpu-freq.h>
  42 #include <plat/devs.h>
  43 #include <plat/nand-core.h>
  44 #include <plat/pm.h>
  45 #include <plat/regs-spi.h>
  46
  47 #include "common.h"
  48 #include "regs-dsc.h"
  49 #include "s3c2412-power.h"
  50
  51 #define S3C2412_SWRST                   (S3C24XX_VA_CLKPWR + 0x30)
  52 #define S3C2412_SWRST_RESET             (0x533C2412)
  53
  54 #ifndef CONFIG_CPU_S3C2412_ONLY
  55 void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;
  56
  57 static inline void s3c2412_init_gpio2(void)
  58 {
  59         s3c24xx_va_gpio2 = S3C24XX_VA_GPIO + 0x10;
  60 }
  61 #else
  62 #define s3c2412_init_gpio2() do { } while(0)
  63 #endif
  64
  65 /* Initial IO mappings */
  66
  67 static struct map_desc s3c2412_iodesc[] __initdata = {
  68         IODESC_ENT(CLKPWR),
  69         IODESC_ENT(TIMER),
  70         IODESC_ENT(WATCHDOG),
  71         {
  72                 .virtual = (unsigned long)S3C2412_VA_SSMC,
  73                 .pfn     = __phys_to_pfn(S3C2412_PA_SSMC),
  74                 .length  = SZ_1M,
  75                 .type    = MT_DEVICE,
  76         },
  77         {
  78                 .virtual = (unsigned long)S3C2412_VA_EBI,
  79                 .pfn     = __phys_to_pfn(S3C2412_PA_EBI),
  80                 .length  = SZ_1M,
  81                 .type    = MT_DEVICE,
  82         },
  83 };
  84
  85 /* uart registration process */
  86
  87 void __init s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no)
  88 {
  89         s3c24xx_init_uartdevs("s3c2412-uart", s3c2410_uart_resources, cfg, no);
  90
  91         /* rename devices that are s3c2412/s3c2413 specific */
  92         s3c_device_sdi.name  = "s3c2412-sdi";
  93         s3c_device_lcd.name  = "s3c2412-lcd";
  94         s3c_nand_setname("s3c2412-nand");
  95
  96         /* alter IRQ of SDI controller */
  97
  98         s3c_device_sdi.resource[1].start = IRQ_S3C2412_SDI;
  99         s3c_device_sdi.resource[1].end   = IRQ_S3C2412_SDI;
 100
 101         /* spi channel related changes, s3c2412/13 specific */
 102         s3c_device_spi0.name = "s3c2412-spi";
 103         s3c_device_spi0.resource[0].end = S3C24XX_PA_SPI + 0x24;
 104         s3c_device_spi1.name = "s3c2412-spi";
 105         s3c_device_spi1.resource[0].start = S3C24XX_PA_SPI + S3C2412_SPI1;
 106         s3c_device_spi1.resource[0].end = S3C24XX_PA_SPI + S3C2412_SPI1 + 0x24;
 107
 108 }
 109
 110 /* s3c2412_idle
 111  *
 112  * use the standard idle call by ensuring the idle mode
 113  * in power config, then issuing the idle co-processor
 114  * instruction
 115 */
 116
 117 static void s3c2412_idle(void)
 118 {
 119         unsigned long tmp;
 120
 121         /* ensure our idle mode is to go to idle */
 122
 123         tmp = __raw_readl(S3C2412_PWRCFG);
 124         tmp &= ~S3C2412_PWRCFG_STANDBYWFI_MASK;
 125         tmp |= S3C2412_PWRCFG_STANDBYWFI_IDLE;
 126         __raw_writel(tmp, S3C2412_PWRCFG);
 127
 128         cpu_do_idle();
 129 }
 130
 131 void s3c2412_restart(enum reboot_mode mode, const char *cmd)
 132 {
 133         if (mode == REBOOT_SOFT)
 134                 soft_restart(0);
 135
 136         /* errata "Watch-dog/Software Reset Problem" specifies that
 137          * this reset must be done with the SYSCLK sourced from
 138          * EXTCLK instead of FOUT to avoid a glitch in the reset
 139          * mechanism.
 140          *
 141          * See the watchdog section of the S3C2412 manual for more
 142          * information on this fix.
 143          */
 144
 145         __raw_writel(0x00, S3C2412_CLKSRC);
 146         __raw_writel(S3C2412_SWRST_RESET, S3C2412_SWRST);
 147
 148         mdelay(1);
 149 }
 150
 151 /* s3c2412_map_io
 152  *
 153  * register the standard cpu IO areas, and any passed in from the
 154  * machine specific initialisation.
 155 */
 156
 157 void __init s3c2412_map_io(void)
 158 {
 159         /* move base of IO */
 160
 161         s3c2412_init_gpio2();
 162
 163         /* set our idle function */
 164
 165         arm_pm_idle = s3c2412_idle;
 166
 167         /* register our io-tables */
 168
 169         iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc));
 170 }
 171
 172 /* need to register the subsystem before we actually register the device, and
 173  * we also need to ensure that it has been initialised before any of the
 174  * drivers even try to use it (even if not on an s3c2412 based system)
 175  * as a driver which may support both 2410 and 2440 may try and use it.
 176 */
 177
 178 struct bus_type s3c2412_subsys = {
 179         .name = "s3c2412-core",
 180         .dev_name = "s3c2412-core",
 181 };
 182
 183 static int __init s3c2412_core_init(void)
 184 {
 185         return subsys_system_register(&s3c2412_subsys, NULL);
 186 }
 187
 188 core_initcall(s3c2412_core_init);
 189
 190 static struct device s3c2412_dev = {
 191         .bus            = &s3c2412_subsys,
 192 };
 193
 194 int __init s3c2412_init(void)
 195 {
 196         printk("S3C2412: Initialising architecture\n");
 197
 198 #ifdef CONFIG_PM
 199         register_syscore_ops(&s3c2412_pm_syscore_ops);
 200         register_syscore_ops(&s3c24xx_irq_syscore_ops);
 201 #endif
 202
 203         return device_register(&s3c2412_dev);
 204 }