arch/arm/mach-s3c24xx/s3c2442.c

   1 /* linux/arch/arm/mach-s3c2442/s3c2442.c
   2  *
   3  * Copyright (c) 2004-2005 Simtec Electronics
   4  *      http://armlinux.simtec.co.uk/
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *
   7  * S3C2442 core and lock support
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  22 */
  23
  24 #include <linux/init.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/list.h>
  28 #include <linux/errno.h>
  29 #include <linux/err.h>
  30 #include <linux/device.h>
  31 #include <linux/syscore_ops.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/ioport.h>
  34 #include <linux/mutex.h>
  35 #include <linux/gpio.h>
  36 #include <linux/clk.h>
  37 #include <linux/io.h>
  38
  39 #include <mach/hardware.h>
  40 #include <linux/atomic.h>
  41 #include <asm/irq.h>
  42
  43 #include <mach/regs-clock.h>
  44
  45 #include <plat/clock.h>
  46 #include <plat/cpu.h>
  47 #include <plat/s3c244x.h>
  48 #include <plat/pm.h>
  49
  50 #include <plat/gpio-core.h>
  51 #include <plat/gpio-cfg.h>
  52 #include <plat/gpio-cfg-helpers.h>
  53
  54 #include "common.h"
  55
  56 /* S3C2442 extended clock support */
  57
  58 static unsigned long s3c2442_camif_upll_round(struct clk *clk,
  59                                               unsigned long rate)
  60 {
  61         unsigned long parent_rate = clk_get_rate(clk->parent);
  62         int div;
  63
  64         if (rate > parent_rate)
  65                 return parent_rate;
  66
  67         div = parent_rate / rate;
  68
  69         if (div == 3)
  70                 return parent_rate / 3;
  71
  72         /* note, we remove the +/- 1 calculations for the divisor */
  73
  74         div /= 2;
  75
  76         if (div < 1)
  77                 div = 1;
  78         else if (div > 16)
  79                 div = 16;
  80
  81         return parent_rate / (div * 2);
  82 }
  83
  84 static int s3c2442_camif_upll_setrate(struct clk *clk, unsigned long rate)
  85 {
  86         unsigned long parent_rate = clk_get_rate(clk->parent);
  87         unsigned long camdivn =  __raw_readl(S3C2440_CAMDIVN);
  88
  89         rate = s3c2442_camif_upll_round(clk, rate);
  90
  91         camdivn &= ~S3C2442_CAMDIVN_CAMCLK_DIV3;
  92
  93         if (rate == parent_rate) {
  94                 camdivn &= ~S3C2440_CAMDIVN_CAMCLK_SEL;
  95         } else if ((parent_rate / rate) == 3) {
  96                 camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
  97                 camdivn |= S3C2442_CAMDIVN_CAMCLK_DIV3;
  98         } else {
  99                 camdivn &= ~S3C2440_CAMDIVN_CAMCLK_MASK;
 100                 camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
 101                 camdivn |= (((parent_rate / rate) / 2) - 1);
 102         }
 103
 104         __raw_writel(camdivn, S3C2440_CAMDIVN);
 105
 106         return 0;
 107 }
 108
 109 /* Extra S3C2442 clocks */
 110
 111 static struct clk s3c2442_clk_cam = {
 112         .name           = "camif",
 113         .id             = -1,
 114         .enable         = s3c2410_clkcon_enable,
 115         .ctrlbit        = S3C2440_CLKCON_CAMERA,
 116 };
 117
 118 static struct clk s3c2442_clk_cam_upll = {
 119         .name           = "camif-upll",
 120         .id             = -1,
 121         .ops            = &(struct clk_ops) {
 122                 .set_rate       = s3c2442_camif_upll_setrate,
 123                 .round_rate     = s3c2442_camif_upll_round,
 124         },
 125 };
 126
 127 static int s3c2442_clk_add(struct device *dev, struct subsys_interface *sif)
 128 {
 129         struct clk *clock_upll;
 130         struct clk *clock_h;
 131         struct clk *clock_p;
 132
 133         clock_p = clk_get(NULL, "pclk");
 134         clock_h = clk_get(NULL, "hclk");
 135         clock_upll = clk_get(NULL, "upll");
 136
 137         if (IS_ERR(clock_p) || IS_ERR(clock_h) || IS_ERR(clock_upll)) {
 138                 printk(KERN_ERR "S3C2442: Failed to get parent clocks\n");
 139                 return -EINVAL;
 140         }
 141
 142         s3c2442_clk_cam.parent = clock_h;
 143         s3c2442_clk_cam_upll.parent = clock_upll;
 144
 145         s3c24xx_register_clock(&s3c2442_clk_cam);
 146         s3c24xx_register_clock(&s3c2442_clk_cam_upll);
 147
 148         clk_disable(&s3c2442_clk_cam);
 149
 150         return 0;
 151 }
 152
 153 static struct subsys_interface s3c2442_clk_interface = {
 154         .name           = "s3c2442_clk",
 155         .subsys         = &s3c2442_subsys,
 156         .add_dev        = s3c2442_clk_add,
 157 };
 158
 159 static __init int s3c2442_clk_init(void)
 160 {
 161         return subsys_interface_register(&s3c2442_clk_interface);
 162 }
 163
 164 arch_initcall(s3c2442_clk_init);
 165
 166
 167 static struct device s3c2442_dev = {
 168         .bus            = &s3c2442_subsys,
 169 };
 170
 171 int __init s3c2442_init(void)
 172 {
 173         printk("S3C2442: Initialising architecture\n");
 174
 175 #ifdef CONFIG_PM
 176         register_syscore_ops(&s3c2410_pm_syscore_ops);
 177         register_syscore_ops(&s3c24xx_irq_syscore_ops);
 178 #endif
 179         register_syscore_ops(&s3c244x_pm_syscore_ops);
 180
 181         return device_register(&s3c2442_dev);
 182 }
 183
 184 void __init s3c2442_map_io(void)
 185 {
 186         s3c244x_map_io();
 187
 188         s3c24xx_gpiocfg_default.set_pull = s3c24xx_gpio_setpull_1down;
 189         s3c24xx_gpiocfg_default.get_pull = s3c24xx_gpio_getpull_1down;
 190 }