arch/arm/mach-s3c64xx/include/mach/dma.h

   1 /* linux/arch/arm/mach-s3c6400/include/mach/dma.h
   2  *
   3  * Copyright 2008 Openmoko, Inc.
   4  * Copyright 2008 Simtec Electronics
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *      http://armlinux.simtec.co.uk/
   7  *
   8  * S3C6400 - DMA support
   9  */
  10
  11 #ifndef __ASM_ARCH_DMA_H
  12 #define __ASM_ARCH_DMA_H __FILE__
  13
  14 #define S3C_DMA_CHANNELS        (16)
  15
  16 /* see mach-s3c2410/dma.h for notes on dma channel numbers */
  17
  18 /* Note, for the S3C64XX architecture we keep the DMACH_
  19  * defines in the order they are allocated to [S]DMA0/[S]DMA1
  20  * so that is easy to do DHACH_ -> DMA controller conversion
  21  */
  22 enum dma_ch {
  23         /* DMA0/SDMA0 */
  24         DMACH_UART0 = 0,
  25         DMACH_UART0_SRC2,
  26         DMACH_UART1,
  27         DMACH_UART1_SRC2,
  28         DMACH_UART2,
  29         DMACH_UART2_SRC2,
  30         DMACH_UART3,
  31         DMACH_UART3_SRC2,
  32         DMACH_PCM0_TX,
  33         DMACH_PCM0_RX,
  34         DMACH_I2S0_OUT,
  35         DMACH_I2S0_IN,
  36         DMACH_SPI0_TX,
  37         DMACH_SPI0_RX,
  38         DMACH_HSI_I2SV40_TX,
  39         DMACH_HSI_I2SV40_RX,
  40
  41         /* DMA1/SDMA1 */
  42         DMACH_PCM1_TX = 16,
  43         DMACH_PCM1_RX,
  44         DMACH_I2S1_OUT,
  45         DMACH_I2S1_IN,
  46         DMACH_SPI1_TX,
  47         DMACH_SPI1_RX,
  48         DMACH_AC97_PCMOUT,
  49         DMACH_AC97_PCMIN,
  50         DMACH_AC97_MICIN,
  51         DMACH_PWM,
  52         DMACH_IRDA,
  53         DMACH_EXTERNAL,
  54         DMACH_RES1,
  55         DMACH_RES2,
  56         DMACH_SECURITY_RX,      /* SDMA1 only */
  57         DMACH_SECURITY_TX,      /* SDMA1 only */
  58         DMACH_MAX               /* the end */
  59 };
  60
  61 static __inline__ bool s3c_dma_has_circular(void)
  62 {
  63         return true;
  64 }
  65
  66 #define S3C2410_DMAF_CIRCULAR           (1 << 0)
  67
  68 #include <plat/dma.h>
  69
  70 #define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
  71
  72 struct s3c64xx_dma_buff;
  73
  74 /** s3c64xx_dma_buff - S3C64XX DMA buffer descriptor
  75  * @next: Pointer to next buffer in queue or ring.
  76  * @pw: Client provided identifier
  77  * @lli: Pointer to hardware descriptor this buffer is associated with.
  78  * @lli_dma: Hardare address of the descriptor.
  79  */
  80 struct s3c64xx_dma_buff {
  81         struct s3c64xx_dma_buff *next;
  82
  83         void                    *pw;
  84         struct pl080s_lli       *lli;
  85         dma_addr_t               lli_dma;
  86 };
  87
  88 struct s3c64xx_dmac;
  89
  90 struct s3c2410_dma_chan {
  91         unsigned char            number;      /* number of this dma channel */
  92         unsigned char            in_use;      /* channel allocated */
  93         unsigned char            bit;         /* bit for enable/disable/etc */
  94         unsigned char            hw_width;
  95         unsigned char            peripheral;
  96
  97         unsigned int             flags;
  98         enum s3c2410_dmasrc      source;
  99
 100
 101         dma_addr_t              dev_addr;
 102
 103         struct s3c2410_dma_client *client;
 104         struct s3c64xx_dmac     *dmac;          /* pointer to controller */
 105
 106         void __iomem            *regs;
 107
 108         /* cdriver callbacks */
 109         s3c2410_dma_cbfn_t       callback_fn;   /* buffer done callback */
 110         s3c2410_dma_opfn_t       op_fn;         /* channel op callback */
 111
 112         /* buffer list and information */
 113         struct s3c64xx_dma_buff *curr;          /* current dma buffer */
 114         struct s3c64xx_dma_buff *next;          /* next buffer to load */
 115         struct s3c64xx_dma_buff *end;           /* end of queue */
 116
 117         /* note, when channel is running in circular mode, curr is the
 118          * first buffer enqueued, end is the last and curr is where the
 119          * last buffer-done event is set-at. The buffers are not freed
 120          * and the last buffer hardware descriptor points back to the
 121          * first.
 122          */
 123 };
 124
 125 #include <plat/dma-core.h>
 126
 127 #endif /* __ASM_ARCH_IRQ_H */