arch/arm/mach-s3c64xx/include/mach/regs-clock.h

   1 /* arch/arm/plat-s3c64xx/include/plat/regs-clock.h
   2  *
   3  * Copyright 2008 Openmoko, Inc.
   4  * Copyright 2008 Simtec Electronics
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *      http://armlinux.simtec.co.uk/
   7  *
   8  * S3C64XX clock register definitions
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13 */
  14
  15 #ifndef __PLAT_REGS_CLOCK_H
  16 #define __PLAT_REGS_CLOCK_H __FILE__
  17
  18 #define S3C_CLKREG(x)           (S3C_VA_SYS + (x))
  19
  20 #define S3C_APLL_LOCK           S3C_CLKREG(0x00)
  21 #define S3C_MPLL_LOCK           S3C_CLKREG(0x04)
  22 #define S3C_EPLL_LOCK           S3C_CLKREG(0x08)
  23 #define S3C_APLL_CON            S3C_CLKREG(0x0C)
  24 #define S3C_MPLL_CON            S3C_CLKREG(0x10)
  25 #define S3C_EPLL_CON0           S3C_CLKREG(0x14)
  26 #define S3C_EPLL_CON1           S3C_CLKREG(0x18)
  27 #define S3C_CLK_SRC             S3C_CLKREG(0x1C)
  28 #define S3C_CLK_DIV0            S3C_CLKREG(0x20)
  29 #define S3C_CLK_DIV1            S3C_CLKREG(0x24)
  30 #define S3C_CLK_DIV2            S3C_CLKREG(0x28)
  31 #define S3C_CLK_OUT             S3C_CLKREG(0x2C)
  32 #define S3C_HCLK_GATE           S3C_CLKREG(0x30)
  33 #define S3C_PCLK_GATE           S3C_CLKREG(0x34)
  34 #define S3C_SCLK_GATE           S3C_CLKREG(0x38)
  35 #define S3C_MEM0_GATE           S3C_CLKREG(0x3C)
  36
  37 /* CLKDIV0 */
  38 #define S3C6400_CLKDIV0_PCLK_MASK       (0xf << 12)
  39 #define S3C6400_CLKDIV0_PCLK_SHIFT      (12)
  40 #define S3C6400_CLKDIV0_HCLK2_MASK      (0x7 << 9)
  41 #define S3C6400_CLKDIV0_HCLK2_SHIFT     (9)
  42 #define S3C6400_CLKDIV0_HCLK_MASK       (0x1 << 8)
  43 #define S3C6400_CLKDIV0_HCLK_SHIFT      (8)
  44 #define S3C6400_CLKDIV0_MPLL_MASK       (0x1 << 4)
  45 #define S3C6400_CLKDIV0_MPLL_SHIFT      (4)
  46
  47 #define S3C6400_CLKDIV0_ARM_MASK        (0x7 << 0)
  48 #define S3C6410_CLKDIV0_ARM_MASK        (0xf << 0)
  49 #define S3C6400_CLKDIV0_ARM_SHIFT       (0)
  50
  51 /* HCLK GATE Registers */
  52 #define S3C_CLKCON_HCLK_3DSE    (1<<31)
  53 #define S3C_CLKCON_HCLK_UHOST   (1<<29)
  54 #define S3C_CLKCON_HCLK_SECUR   (1<<28)
  55 #define S3C_CLKCON_HCLK_SDMA1   (1<<27)
  56 #define S3C_CLKCON_HCLK_SDMA0   (1<<26)
  57 #define S3C_CLKCON_HCLK_IROM    (1<<25)
  58 #define S3C_CLKCON_HCLK_DDR1    (1<<24)
  59 #define S3C_CLKCON_HCLK_DDR0    (1<<23)
  60 #define S3C_CLKCON_HCLK_MEM1    (1<<22)
  61 #define S3C_CLKCON_HCLK_MEM0    (1<<21)
  62 #define S3C_CLKCON_HCLK_USB     (1<<20)
  63 #define S3C_CLKCON_HCLK_HSMMC2  (1<<19)
  64 #define S3C_CLKCON_HCLK_HSMMC1  (1<<18)
  65 #define S3C_CLKCON_HCLK_HSMMC0  (1<<17)
  66 #define S3C_CLKCON_HCLK_MDP     (1<<16)
  67 #define S3C_CLKCON_HCLK_DHOST   (1<<15)
  68 #define S3C_CLKCON_HCLK_IHOST   (1<<14)
  69 #define S3C_CLKCON_HCLK_DMA1    (1<<13)
  70 #define S3C_CLKCON_HCLK_DMA0    (1<<12)
  71 #define S3C_CLKCON_HCLK_JPEG    (1<<11)
  72 #define S3C_CLKCON_HCLK_CAMIF   (1<<10)
  73 #define S3C_CLKCON_HCLK_SCALER  (1<<9)
  74 #define S3C_CLKCON_HCLK_2D      (1<<8)
  75 #define S3C_CLKCON_HCLK_TV      (1<<7)
  76 #define S3C_CLKCON_HCLK_POST0   (1<<5)
  77 #define S3C_CLKCON_HCLK_ROT     (1<<4)
  78 #define S3C_CLKCON_HCLK_LCD     (1<<3)
  79 #define S3C_CLKCON_HCLK_TZIC    (1<<2)
  80 #define S3C_CLKCON_HCLK_INTC    (1<<1)
  81 #define S3C_CLKCON_HCLK_MFC     (1<<0)
  82
  83 /* PCLK GATE Registers */
  84 #define S3C6410_CLKCON_PCLK_I2C1        (1<<27)
  85 #define S3C6410_CLKCON_PCLK_IIS2        (1<<26)
  86 #define S3C_CLKCON_PCLK_SKEY            (1<<24)
  87 #define S3C_CLKCON_PCLK_CHIPID          (1<<23)
  88 #define S3C_CLKCON_PCLK_SPI1            (1<<22)
  89 #define S3C_CLKCON_PCLK_SPI0            (1<<21)
  90 #define S3C_CLKCON_PCLK_HSIRX           (1<<20)
  91 #define S3C_CLKCON_PCLK_HSITX           (1<<19)
  92 #define S3C_CLKCON_PCLK_GPIO            (1<<18)
  93 #define S3C_CLKCON_PCLK_IIC             (1<<17)
  94 #define S3C_CLKCON_PCLK_IIS1            (1<<16)
  95 #define S3C_CLKCON_PCLK_IIS0            (1<<15)
  96 #define S3C_CLKCON_PCLK_AC97            (1<<14)
  97 #define S3C_CLKCON_PCLK_TZPC            (1<<13)
  98 #define S3C_CLKCON_PCLK_TSADC           (1<<12)
  99 #define S3C_CLKCON_PCLK_KEYPAD          (1<<11)
 100 #define S3C_CLKCON_PCLK_IRDA            (1<<10)
 101 #define S3C_CLKCON_PCLK_PCM1            (1<<9)
 102 #define S3C_CLKCON_PCLK_PCM0            (1<<8)
 103 #define S3C_CLKCON_PCLK_PWM             (1<<7)
 104 #define S3C_CLKCON_PCLK_RTC             (1<<6)
 105 #define S3C_CLKCON_PCLK_WDT             (1<<5)
 106 #define S3C_CLKCON_PCLK_UART3           (1<<4)
 107 #define S3C_CLKCON_PCLK_UART2           (1<<3)
 108 #define S3C_CLKCON_PCLK_UART1           (1<<2)
 109 #define S3C_CLKCON_PCLK_UART0           (1<<1)
 110 #define S3C_CLKCON_PCLK_MFC             (1<<0)
 111
 112 /* SCLK GATE Registers */
 113 #define S3C_CLKCON_SCLK_UHOST           (1<<30)
 114 #define S3C_CLKCON_SCLK_MMC2_48         (1<<29)
 115 #define S3C_CLKCON_SCLK_MMC1_48         (1<<28)
 116 #define S3C_CLKCON_SCLK_MMC0_48         (1<<27)
 117 #define S3C_CLKCON_SCLK_MMC2            (1<<26)
 118 #define S3C_CLKCON_SCLK_MMC1            (1<<25)
 119 #define S3C_CLKCON_SCLK_MMC0            (1<<24)
 120 #define S3C_CLKCON_SCLK_SPI1_48         (1<<23)
 121 #define S3C_CLKCON_SCLK_SPI0_48         (1<<22)
 122 #define S3C_CLKCON_SCLK_SPI1            (1<<21)
 123 #define S3C_CLKCON_SCLK_SPI0            (1<<20)
 124 #define S3C_CLKCON_SCLK_DAC27           (1<<19)
 125 #define S3C_CLKCON_SCLK_TV27            (1<<18)
 126 #define S3C_CLKCON_SCLK_SCALER27        (1<<17)
 127 #define S3C_CLKCON_SCLK_SCALER          (1<<16)
 128 #define S3C_CLKCON_SCLK_LCD27           (1<<15)
 129 #define S3C_CLKCON_SCLK_LCD             (1<<14)
 130 #define S3C6400_CLKCON_SCLK_POST1_27    (1<<13)
 131 #define S3C6410_CLKCON_FIMC             (1<<13)
 132 #define S3C_CLKCON_SCLK_POST0_27        (1<<12)
 133 #define S3C6400_CLKCON_SCLK_POST1       (1<<11)
 134 #define S3C6410_CLKCON_SCLK_AUDIO2      (1<<11)
 135 #define S3C_CLKCON_SCLK_POST0           (1<<10)
 136 #define S3C_CLKCON_SCLK_AUDIO1          (1<<9)
 137 #define S3C_CLKCON_SCLK_AUDIO0          (1<<8)
 138 #define S3C_CLKCON_SCLK_SECUR           (1<<7)
 139 #define S3C_CLKCON_SCLK_IRDA            (1<<6)
 140 #define S3C_CLKCON_SCLK_UART            (1<<5)
 141 #define S3C_CLKCON_SCLK_ONENAND         (1<<4)
 142 #define S3C_CLKCON_SCLK_MFC             (1<<3)
 143 #define S3C_CLKCON_SCLK_CAM             (1<<2)
 144 #define S3C_CLKCON_SCLK_JPEG            (1<<1)
 145
 146 /* CLKSRC */
 147
 148 #define S3C6400_CLKSRC_APLL_MOUT        (1 << 0)
 149 #define S3C6400_CLKSRC_MPLL_MOUT        (1 << 1)
 150 #define S3C6400_CLKSRC_EPLL_MOUT        (1 << 2)
 151 #define S3C6400_CLKSRC_APLL_MOUT_SHIFT  (0)
 152 #define S3C6400_CLKSRC_MPLL_MOUT_SHIFT  (1)
 153 #define S3C6400_CLKSRC_EPLL_MOUT_SHIFT  (2)
 154 #define S3C6400_CLKSRC_MFC              (1 << 4)
 155
 156 #endif /* _PLAT_REGS_CLOCK_H */