Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
[deliverable/linux.git] / arch / arm / mach-s3c64xx / mach-mini6410.c
1 /* linux/arch/arm/mach-s3c64xx/mach-mini6410.c
2 *
3 * Copyright 2010 Darius Augulis <augulis.darius@gmail.com>
4 * Copyright 2008 Openmoko, Inc.
5 * Copyright 2008 Simtec Electronics
6 * Ben Dooks <ben@simtec.co.uk>
7 * http://armlinux.simtec.co.uk/
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/fb.h>
18 #include <linux/gpio.h>
19 #include <linux/kernel.h>
20 #include <linux/list.h>
21 #include <linux/dm9000.h>
22 #include <linux/mtd/mtd.h>
23 #include <linux/mtd/partitions.h>
24 #include <linux/serial_core.h>
25 #include <linux/types.h>
26
27 #include <asm/mach-types.h>
28 #include <asm/mach/arch.h>
29 #include <asm/mach/map.h>
30
31 #include <mach/map.h>
32 #include <mach/regs-gpio.h>
33
34 #include <plat/adc.h>
35 #include <plat/cpu.h>
36 #include <plat/devs.h>
37 #include <plat/fb.h>
38 #include <linux/platform_data/mtd-nand-s3c2410.h>
39 #include <plat/regs-serial.h>
40 #include <linux/platform_data/touchscreen-s3c2410.h>
41
42 #include <video/platform_lcd.h>
43 #include <video/samsung_fimd.h>
44
45 #include "common.h"
46 #include "regs-modem.h"
47 #include "regs-srom.h"
48
49 #define UCON S3C2410_UCON_DEFAULT
50 #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
51 #define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
52
53 static struct s3c2410_uartcfg mini6410_uartcfgs[] __initdata = {
54 [0] = {
55 .hwport = 0,
56 .flags = 0,
57 .ucon = UCON,
58 .ulcon = ULCON,
59 .ufcon = UFCON,
60 },
61 [1] = {
62 .hwport = 1,
63 .flags = 0,
64 .ucon = UCON,
65 .ulcon = ULCON,
66 .ufcon = UFCON,
67 },
68 [2] = {
69 .hwport = 2,
70 .flags = 0,
71 .ucon = UCON,
72 .ulcon = ULCON,
73 .ufcon = UFCON,
74 },
75 [3] = {
76 .hwport = 3,
77 .flags = 0,
78 .ucon = UCON,
79 .ulcon = ULCON,
80 .ufcon = UFCON,
81 },
82 };
83
84 /* DM9000AEP 10/100 ethernet controller */
85
86 static struct resource mini6410_dm9k_resource[] = {
87 [0] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN1, 2),
88 [1] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN1 + 4, 2),
89 [2] = DEFINE_RES_NAMED(S3C_EINT(7), 1, NULL, IORESOURCE_IRQ \
90 | IORESOURCE_IRQ_HIGHLEVEL),
91 };
92
93 static struct dm9000_plat_data mini6410_dm9k_pdata = {
94 .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
95 };
96
97 static struct platform_device mini6410_device_eth = {
98 .name = "dm9000",
99 .id = -1,
100 .num_resources = ARRAY_SIZE(mini6410_dm9k_resource),
101 .resource = mini6410_dm9k_resource,
102 .dev = {
103 .platform_data = &mini6410_dm9k_pdata,
104 },
105 };
106
107 static struct mtd_partition mini6410_nand_part[] = {
108 [0] = {
109 .name = "uboot",
110 .size = SZ_1M,
111 .offset = 0,
112 },
113 [1] = {
114 .name = "kernel",
115 .size = SZ_2M,
116 .offset = SZ_1M,
117 },
118 [2] = {
119 .name = "rootfs",
120 .size = MTDPART_SIZ_FULL,
121 .offset = SZ_1M + SZ_2M,
122 },
123 };
124
125 static struct s3c2410_nand_set mini6410_nand_sets[] = {
126 [0] = {
127 .name = "nand",
128 .nr_chips = 1,
129 .nr_partitions = ARRAY_SIZE(mini6410_nand_part),
130 .partitions = mini6410_nand_part,
131 },
132 };
133
134 static struct s3c2410_platform_nand mini6410_nand_info = {
135 .tacls = 25,
136 .twrph0 = 55,
137 .twrph1 = 40,
138 .nr_sets = ARRAY_SIZE(mini6410_nand_sets),
139 .sets = mini6410_nand_sets,
140 };
141
142 static struct s3c_fb_pd_win mini6410_lcd_type0_fb_win = {
143 .max_bpp = 32,
144 .default_bpp = 16,
145 .xres = 480,
146 .yres = 272,
147 };
148
149 static struct fb_videomode mini6410_lcd_type0_timing = {
150 /* 4.3" 480x272 */
151 .left_margin = 3,
152 .right_margin = 2,
153 .upper_margin = 1,
154 .lower_margin = 1,
155 .hsync_len = 40,
156 .vsync_len = 1,
157 .xres = 480,
158 .yres = 272,
159 };
160
161 static struct s3c_fb_pd_win mini6410_lcd_type1_fb_win = {
162 .max_bpp = 32,
163 .default_bpp = 16,
164 .xres = 800,
165 .yres = 480,
166 };
167
168 static struct fb_videomode mini6410_lcd_type1_timing = {
169 /* 7.0" 800x480 */
170 .left_margin = 8,
171 .right_margin = 13,
172 .upper_margin = 7,
173 .lower_margin = 5,
174 .hsync_len = 3,
175 .vsync_len = 1,
176 .xres = 800,
177 .yres = 480,
178 };
179
180 static struct s3c_fb_platdata mini6410_lcd_pdata[] __initdata = {
181 {
182 .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
183 .vtiming = &mini6410_lcd_type0_timing,
184 .win[0] = &mini6410_lcd_type0_fb_win,
185 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
186 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
187 }, {
188 .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
189 .vtiming = &mini6410_lcd_type1_timing,
190 .win[0] = &mini6410_lcd_type1_fb_win,
191 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
192 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
193 },
194 { },
195 };
196
197 static void mini6410_lcd_power_set(struct plat_lcd_data *pd,
198 unsigned int power)
199 {
200 if (power)
201 gpio_direction_output(S3C64XX_GPE(0), 1);
202 else
203 gpio_direction_output(S3C64XX_GPE(0), 0);
204 }
205
206 static struct plat_lcd_data mini6410_lcd_power_data = {
207 .set_power = mini6410_lcd_power_set,
208 };
209
210 static struct platform_device mini6410_lcd_powerdev = {
211 .name = "platform-lcd",
212 .dev.parent = &s3c_device_fb.dev,
213 .dev.platform_data = &mini6410_lcd_power_data,
214 };
215
216 static struct platform_device *mini6410_devices[] __initdata = {
217 &mini6410_device_eth,
218 &s3c_device_hsmmc0,
219 &s3c_device_hsmmc1,
220 &s3c_device_ohci,
221 &s3c_device_nand,
222 &s3c_device_fb,
223 &mini6410_lcd_powerdev,
224 &s3c_device_adc,
225 &s3c_device_ts,
226 };
227
228 static void __init mini6410_map_io(void)
229 {
230 u32 tmp;
231
232 s3c64xx_init_io(NULL, 0);
233 s3c24xx_init_clocks(12000000);
234 s3c24xx_init_uarts(mini6410_uartcfgs, ARRAY_SIZE(mini6410_uartcfgs));
235
236 /* set the LCD type */
237 tmp = __raw_readl(S3C64XX_SPCON);
238 tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
239 tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
240 __raw_writel(tmp, S3C64XX_SPCON);
241
242 /* remove the LCD bypass */
243 tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
244 tmp &= ~MIFPCON_LCD_BYPASS;
245 __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
246 }
247
248 /*
249 * mini6410_features string
250 *
251 * 0-9 LCD configuration
252 *
253 */
254 static char mini6410_features_str[12] __initdata = "0";
255
256 static int __init mini6410_features_setup(char *str)
257 {
258 if (str)
259 strlcpy(mini6410_features_str, str,
260 sizeof(mini6410_features_str));
261 return 1;
262 }
263
264 __setup("mini6410=", mini6410_features_setup);
265
266 #define FEATURE_SCREEN (1 << 0)
267
268 struct mini6410_features_t {
269 int done;
270 int lcd_index;
271 };
272
273 static void mini6410_parse_features(
274 struct mini6410_features_t *features,
275 const char *features_str)
276 {
277 const char *fp = features_str;
278
279 features->done = 0;
280 features->lcd_index = 0;
281
282 while (*fp) {
283 char f = *fp++;
284
285 switch (f) {
286 case '0'...'9': /* tft screen */
287 if (features->done & FEATURE_SCREEN) {
288 printk(KERN_INFO "MINI6410: '%c' ignored, "
289 "screen type already set\n", f);
290 } else {
291 int li = f - '0';
292 if (li >= ARRAY_SIZE(mini6410_lcd_pdata))
293 printk(KERN_INFO "MINI6410: '%c' out "
294 "of range LCD mode\n", f);
295 else {
296 features->lcd_index = li;
297 }
298 }
299 features->done |= FEATURE_SCREEN;
300 break;
301 }
302 }
303 }
304
305 static void __init mini6410_machine_init(void)
306 {
307 u32 cs1;
308 struct mini6410_features_t features = { 0 };
309
310 printk(KERN_INFO "MINI6410: Option string mini6410=%s\n",
311 mini6410_features_str);
312
313 /* Parse the feature string */
314 mini6410_parse_features(&features, mini6410_features_str);
315
316 printk(KERN_INFO "MINI6410: selected LCD display is %dx%d\n",
317 mini6410_lcd_pdata[features.lcd_index].win[0]->xres,
318 mini6410_lcd_pdata[features.lcd_index].win[0]->yres);
319
320 s3c_nand_set_platdata(&mini6410_nand_info);
321 s3c_fb_set_platdata(&mini6410_lcd_pdata[features.lcd_index]);
322 s3c24xx_ts_set_platdata(NULL);
323
324 /* configure nCS1 width to 16 bits */
325
326 cs1 = __raw_readl(S3C64XX_SROM_BW) &
327 ~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
328 cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) |
329 (1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) |
330 (1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
331 S3C64XX_SROM_BW__NCS1__SHIFT;
332 __raw_writel(cs1, S3C64XX_SROM_BW);
333
334 /* set timing for nCS1 suitable for ethernet chip */
335
336 __raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
337 (6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
338 (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
339 (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
340 (13 << S3C64XX_SROM_BCX__TACC__SHIFT) |
341 (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
342 (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
343
344 gpio_request(S3C64XX_GPF(15), "LCD power");
345 gpio_request(S3C64XX_GPE(0), "LCD power");
346
347 platform_add_devices(mini6410_devices, ARRAY_SIZE(mini6410_devices));
348 }
349
350 MACHINE_START(MINI6410, "MINI6410")
351 /* Maintainer: Darius Augulis <augulis.darius@gmail.com> */
352 .atag_offset = 0x100,
353 .init_irq = s3c6410_init_irq,
354 .map_io = mini6410_map_io,
355 .init_machine = mini6410_machine_init,
356 .init_late = s3c64xx_init_late,
357 .init_time = s3c24xx_timer_init,
358 .restart = s3c64xx_restart,
359 MACHINE_END
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