arch/arm/mach-s5pc100/clock.c

   1 /* linux/arch/arm/mach-s5pc100/clock.c
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com/
   5  *
   6  * S5PC100 - Clock support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/init.h>
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/list.h>
  17 #include <linux/err.h>
  18 #include <linux/clk.h>
  19 #include <linux/io.h>
  20
  21 #include <mach/map.h>
  22
  23 #include <plat/cpu-freq.h>
  24 #include <mach/regs-clock.h>
  25 #include <plat/clock.h>
  26 #include <plat/cpu.h>
  27 #include <plat/pll.h>
  28 #include <plat/s5p-clock.h>
  29 #include <plat/clock-clksrc.h>
  30 #include <plat/s5pc100.h>
  31
  32 static struct clk s5p_clk_otgphy = {
  33         .name           = "otg_phy",
  34 };
  35
  36 static struct clk dummy_apb_pclk = {
  37         .name           = "apb_pclk",
  38         .id             = -1,
  39 };
  40
  41 static struct clk *clk_src_mout_href_list[] = {
  42         [0] = &s5p_clk_27m,
  43         [1] = &clk_fin_hpll,
  44 };
  45
  46 static struct clksrc_sources clk_src_mout_href = {
  47         .sources        = clk_src_mout_href_list,
  48         .nr_sources     = ARRAY_SIZE(clk_src_mout_href_list),
  49 };
  50
  51 static struct clksrc_clk clk_mout_href = {
  52         .clk = {
  53                 .name           = "mout_href",
  54         },
  55         .sources        = &clk_src_mout_href,
  56         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
  57 };
  58
  59 static struct clk *clk_src_mout_48m_list[] = {
  60         [0] = &clk_xusbxti,
  61         [1] = &s5p_clk_otgphy,
  62 };
  63
  64 static struct clksrc_sources clk_src_mout_48m = {
  65         .sources        = clk_src_mout_48m_list,
  66         .nr_sources     = ARRAY_SIZE(clk_src_mout_48m_list),
  67 };
  68
  69 static struct clksrc_clk clk_mout_48m = {
  70         .clk = {
  71                 .name           = "mout_48m",
  72         },
  73         .sources        = &clk_src_mout_48m,
  74         .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 1 },
  75 };
  76
  77 static struct clksrc_clk clk_mout_mpll = {
  78         .clk = {
  79                 .name           = "mout_mpll",
  80         },
  81         .sources        = &clk_src_mpll,
  82         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
  83 };
  84
  85
  86 static struct clksrc_clk clk_mout_apll = {
  87         .clk    = {
  88                 .name           = "mout_apll",
  89         },
  90         .sources        = &clk_src_apll,
  91         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
  92 };
  93
  94 static struct clksrc_clk clk_mout_epll = {
  95         .clk    = {
  96                 .name           = "mout_epll",
  97         },
  98         .sources        = &clk_src_epll,
  99         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
 100 };
 101
 102 static struct clk *clk_src_mout_hpll_list[] = {
 103         [0] = &s5p_clk_27m,
 104 };
 105
 106 static struct clksrc_sources clk_src_mout_hpll = {
 107         .sources        = clk_src_mout_hpll_list,
 108         .nr_sources     = ARRAY_SIZE(clk_src_mout_hpll_list),
 109 };
 110
 111 static struct clksrc_clk clk_mout_hpll = {
 112         .clk    = {
 113                 .name           = "mout_hpll",
 114         },
 115         .sources        = &clk_src_mout_hpll,
 116         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
 117 };
 118
 119 static struct clksrc_clk clk_div_apll = {
 120         .clk    = {
 121                 .name   = "div_apll",
 122                 .parent = &clk_mout_apll.clk,
 123         },
 124         .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 },
 125 };
 126
 127 static struct clksrc_clk clk_div_arm = {
 128         .clk    = {
 129                 .name   = "div_arm",
 130                 .parent = &clk_div_apll.clk,
 131         },
 132         .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
 133 };
 134
 135 static struct clksrc_clk clk_div_d0_bus = {
 136         .clk    = {
 137                 .name   = "div_d0_bus",
 138                 .parent = &clk_div_arm.clk,
 139         },
 140         .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
 141 };
 142
 143 static struct clksrc_clk clk_div_pclkd0 = {
 144         .clk    = {
 145                 .name   = "div_pclkd0",
 146                 .parent = &clk_div_d0_bus.clk,
 147         },
 148         .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
 149 };
 150
 151 static struct clksrc_clk clk_div_secss = {
 152         .clk    = {
 153                 .name   = "div_secss",
 154                 .parent = &clk_div_d0_bus.clk,
 155         },
 156         .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 },
 157 };
 158
 159 static struct clksrc_clk clk_div_apll2 = {
 160         .clk    = {
 161                 .name   = "div_apll2",
 162                 .parent = &clk_mout_apll.clk,
 163         },
 164         .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 },
 165 };
 166
 167 static struct clk *clk_src_mout_am_list[] = {
 168         [0] = &clk_mout_mpll.clk,
 169         [1] = &clk_div_apll2.clk,
 170 };
 171
 172 struct clksrc_sources clk_src_mout_am = {
 173         .sources        = clk_src_mout_am_list,
 174         .nr_sources     = ARRAY_SIZE(clk_src_mout_am_list),
 175 };
 176
 177 static struct clksrc_clk clk_mout_am = {
 178         .clk    = {
 179                 .name   = "mout_am",
 180         },
 181         .sources = &clk_src_mout_am,
 182         .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
 183 };
 184
 185 static struct clksrc_clk clk_div_d1_bus = {
 186         .clk    = {
 187                 .name   = "div_d1_bus",
 188                 .parent = &clk_mout_am.clk,
 189         },
 190         .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 },
 191 };
 192
 193 static struct clksrc_clk clk_div_mpll2 = {
 194         .clk    = {
 195                 .name   = "div_mpll2",
 196                 .parent = &clk_mout_am.clk,
 197         },
 198         .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 },
 199 };
 200
 201 static struct clksrc_clk clk_div_mpll = {
 202         .clk    = {
 203                 .name   = "div_mpll",
 204                 .parent = &clk_mout_am.clk,
 205         },
 206         .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 },
 207 };
 208
 209 static struct clk *clk_src_mout_onenand_list[] = {
 210         [0] = &clk_div_d0_bus.clk,
 211         [1] = &clk_div_d1_bus.clk,
 212 };
 213
 214 struct clksrc_sources clk_src_mout_onenand = {
 215         .sources        = clk_src_mout_onenand_list,
 216         .nr_sources     = ARRAY_SIZE(clk_src_mout_onenand_list),
 217 };
 218
 219 static struct clksrc_clk clk_mout_onenand = {
 220         .clk    = {
 221                 .name   = "mout_onenand",
 222         },
 223         .sources = &clk_src_mout_onenand,
 224         .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
 225 };
 226
 227 static struct clksrc_clk clk_div_onenand = {
 228         .clk    = {
 229                 .name   = "div_onenand",
 230                 .parent = &clk_mout_onenand.clk,
 231         },
 232         .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 },
 233 };
 234
 235 static struct clksrc_clk clk_div_pclkd1 = {
 236         .clk    = {
 237                 .name   = "div_pclkd1",
 238                 .parent = &clk_div_d1_bus.clk,
 239         },
 240         .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 3 },
 241 };
 242
 243 static struct clksrc_clk clk_div_cam = {
 244         .clk    = {
 245                 .name   = "div_cam",
 246                 .parent = &clk_div_mpll2.clk,
 247         },
 248         .reg_div = { .reg = S5P_CLK_DIV1, .shift = 24, .size = 5 },
 249 };
 250
 251 static struct clksrc_clk clk_div_hdmi = {
 252         .clk    = {
 253                 .name   = "div_hdmi",
 254                 .parent = &clk_mout_hpll.clk,
 255         },
 256         .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 },
 257 };
 258
 259 static u32 epll_div[][4] = {
 260         { 32750000,     131, 3, 4 },
 261         { 32768000,     131, 3, 4 },
 262         { 36000000,     72,  3, 3 },
 263         { 45000000,     90,  3, 3 },
 264         { 45158000,     90,  3, 3 },
 265         { 45158400,     90,  3, 3 },
 266         { 48000000,     96,  3, 3 },
 267         { 49125000,     131, 4, 3 },
 268         { 49152000,     131, 4, 3 },
 269         { 60000000,     120, 3, 3 },
 270         { 67737600,     226, 5, 3 },
 271         { 67738000,     226, 5, 3 },
 272         { 73800000,     246, 5, 3 },
 273         { 73728000,     246, 5, 3 },
 274         { 72000000,     144, 3, 3 },
 275         { 84000000,     168, 3, 3 },
 276         { 96000000,     96,  3, 2 },
 277         { 144000000,    144, 3, 2 },
 278         { 192000000,    96,  3, 1 }
 279 };
 280
 281 static int s5pc100_epll_set_rate(struct clk *clk, unsigned long rate)
 282 {
 283         unsigned int epll_con;
 284         unsigned int i;
 285
 286         if (clk->rate == rate)  /* Return if nothing changed */
 287                 return 0;
 288
 289         epll_con = __raw_readl(S5P_EPLL_CON);
 290
 291         epll_con &= ~(PLL65XX_MDIV_MASK | PLL65XX_PDIV_MASK | PLL65XX_SDIV_MASK);
 292
 293         for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
 294                 if (epll_div[i][0] == rate) {
 295                         epll_con |= (epll_div[i][1] << PLL65XX_MDIV_SHIFT) |
 296                                     (epll_div[i][2] << PLL65XX_PDIV_SHIFT) |
 297                                     (epll_div[i][3] << PLL65XX_SDIV_SHIFT);
 298                         break;
 299                 }
 300         }
 301
 302         if (i == ARRAY_SIZE(epll_div)) {
 303                 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
 304                 return -EINVAL;
 305         }
 306
 307         __raw_writel(epll_con, S5P_EPLL_CON);
 308
 309         printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
 310                         clk->rate, rate);
 311
 312         clk->rate = rate;
 313
 314         return 0;
 315 }
 316
 317 static struct clk_ops s5pc100_epll_ops = {
 318         .get_rate = s5p_epll_get_rate,
 319         .set_rate = s5pc100_epll_set_rate,
 320 };
 321
 322 static int s5pc100_d0_0_ctrl(struct clk *clk, int enable)
 323 {
 324         return s5p_gatectrl(S5P_CLKGATE_D00, clk, enable);
 325 }
 326
 327 static int s5pc100_d0_1_ctrl(struct clk *clk, int enable)
 328 {
 329         return s5p_gatectrl(S5P_CLKGATE_D01, clk, enable);
 330 }
 331
 332 static int s5pc100_d0_2_ctrl(struct clk *clk, int enable)
 333 {
 334         return s5p_gatectrl(S5P_CLKGATE_D02, clk, enable);
 335 }
 336
 337 static int s5pc100_d1_0_ctrl(struct clk *clk, int enable)
 338 {
 339         return s5p_gatectrl(S5P_CLKGATE_D10, clk, enable);
 340 }
 341
 342 static int s5pc100_d1_1_ctrl(struct clk *clk, int enable)
 343 {
 344         return s5p_gatectrl(S5P_CLKGATE_D11, clk, enable);
 345 }
 346
 347 static int s5pc100_d1_2_ctrl(struct clk *clk, int enable)
 348 {
 349         return s5p_gatectrl(S5P_CLKGATE_D12, clk, enable);
 350 }
 351
 352 static int s5pc100_d1_3_ctrl(struct clk *clk, int enable)
 353 {
 354         return s5p_gatectrl(S5P_CLKGATE_D13, clk, enable);
 355 }
 356
 357 static int s5pc100_d1_4_ctrl(struct clk *clk, int enable)
 358 {
 359         return s5p_gatectrl(S5P_CLKGATE_D14, clk, enable);
 360 }
 361
 362 static int s5pc100_d1_5_ctrl(struct clk *clk, int enable)
 363 {
 364         return s5p_gatectrl(S5P_CLKGATE_D15, clk, enable);
 365 }
 366
 367 static int s5pc100_sclk0_ctrl(struct clk *clk, int enable)
 368 {
 369         return s5p_gatectrl(S5P_CLKGATE_SCLK0, clk, enable);
 370 }
 371
 372 static int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
 373 {
 374         return s5p_gatectrl(S5P_CLKGATE_SCLK1, clk, enable);
 375 }
 376
 377 /*
 378  * The following clocks will be disabled during clock initialization. It is
 379  * recommended to keep the following clocks disabled until the driver requests
 380  * for enabling the clock.
 381  */
 382 static struct clk init_clocks_off[] = {
 383         {
 384                 .name           = "cssys",
 385                 .parent         = &clk_div_d0_bus.clk,
 386                 .enable         = s5pc100_d0_0_ctrl,
 387                 .ctrlbit        = (1 << 6),
 388         }, {
 389                 .name           = "secss",
 390                 .parent         = &clk_div_d0_bus.clk,
 391                 .enable         = s5pc100_d0_0_ctrl,
 392                 .ctrlbit        = (1 << 5),
 393         }, {
 394                 .name           = "g2d",
 395                 .parent         = &clk_div_d0_bus.clk,
 396                 .enable         = s5pc100_d0_0_ctrl,
 397                 .ctrlbit        = (1 << 4),
 398         }, {
 399                 .name           = "mdma",
 400                 .parent         = &clk_div_d0_bus.clk,
 401                 .enable         = s5pc100_d0_0_ctrl,
 402                 .ctrlbit        = (1 << 3),
 403         }, {
 404                 .name           = "cfcon",
 405                 .parent         = &clk_div_d0_bus.clk,
 406                 .enable         = s5pc100_d0_0_ctrl,
 407                 .ctrlbit        = (1 << 2),
 408         }, {
 409                 .name           = "nfcon",
 410                 .parent         = &clk_div_d0_bus.clk,
 411                 .enable         = s5pc100_d0_1_ctrl,
 412                 .ctrlbit        = (1 << 3),
 413         }, {
 414                 .name           = "onenandc",
 415                 .parent         = &clk_div_d0_bus.clk,
 416                 .enable         = s5pc100_d0_1_ctrl,
 417                 .ctrlbit        = (1 << 2),
 418         }, {
 419                 .name           = "sdm",
 420                 .parent         = &clk_div_d0_bus.clk,
 421                 .enable         = s5pc100_d0_2_ctrl,
 422                 .ctrlbit        = (1 << 2),
 423         }, {
 424                 .name           = "seckey",
 425                 .parent         = &clk_div_d0_bus.clk,
 426                 .enable         = s5pc100_d0_2_ctrl,
 427                 .ctrlbit        = (1 << 1),
 428         }, {
 429                 .name           = "hsmmc",
 430                 .devname        = "s3c-sdhci.2",
 431                 .parent         = &clk_div_d1_bus.clk,
 432                 .enable         = s5pc100_d1_0_ctrl,
 433                 .ctrlbit        = (1 << 7),
 434         }, {
 435                 .name           = "hsmmc",
 436                 .devname        = "s3c-sdhci.1",
 437                 .parent         = &clk_div_d1_bus.clk,
 438                 .enable         = s5pc100_d1_0_ctrl,
 439                 .ctrlbit        = (1 << 6),
 440         }, {
 441                 .name           = "hsmmc",
 442                 .devname        = "s3c-sdhci.0",
 443                 .parent         = &clk_div_d1_bus.clk,
 444                 .enable         = s5pc100_d1_0_ctrl,
 445                 .ctrlbit        = (1 << 5),
 446         }, {
 447                 .name           = "modemif",
 448                 .parent         = &clk_div_d1_bus.clk,
 449                 .enable         = s5pc100_d1_0_ctrl,
 450                 .ctrlbit        = (1 << 4),
 451         }, {
 452                 .name           = "otg",
 453                 .parent         = &clk_div_d1_bus.clk,
 454                 .enable         = s5pc100_d1_0_ctrl,
 455                 .ctrlbit        = (1 << 3),
 456         }, {
 457                 .name           = "usbhost",
 458                 .parent         = &clk_div_d1_bus.clk,
 459                 .enable         = s5pc100_d1_0_ctrl,
 460                 .ctrlbit        = (1 << 2),
 461         }, {
 462                 .name           = "dma",
 463                 .devname        = "s3c-pl330.1",
 464                 .parent         = &clk_div_d1_bus.clk,
 465                 .enable         = s5pc100_d1_0_ctrl,
 466                 .ctrlbit        = (1 << 1),
 467         }, {
 468                 .name           = "dma",
 469                 .devname        = "s3c-pl330.0",
 470                 .parent         = &clk_div_d1_bus.clk,
 471                 .enable         = s5pc100_d1_0_ctrl,
 472                 .ctrlbit        = (1 << 0),
 473         }, {
 474                 .name           = "lcd",
 475                 .parent         = &clk_div_d1_bus.clk,
 476                 .enable         = s5pc100_d1_1_ctrl,
 477                 .ctrlbit        = (1 << 0),
 478         }, {
 479                 .name           = "rotator",
 480                 .parent         = &clk_div_d1_bus.clk,
 481                 .enable         = s5pc100_d1_1_ctrl,
 482                 .ctrlbit        = (1 << 1),
 483         }, {
 484                 .name           = "fimc",
 485                 .devname        = "s5p-fimc.0",
 486                 .parent         = &clk_div_d1_bus.clk,
 487                 .enable         = s5pc100_d1_1_ctrl,
 488                 .ctrlbit        = (1 << 2),
 489         }, {
 490                 .name           = "fimc",
 491                 .devname        = "s5p-fimc.1",
 492                 .parent         = &clk_div_d1_bus.clk,
 493                 .enable         = s5pc100_d1_1_ctrl,
 494                 .ctrlbit        = (1 << 3),
 495         }, {
 496                 .name           = "fimc",
 497                 .devname        = "s5p-fimc.2",
 498                 .enable         = s5pc100_d1_1_ctrl,
 499                 .ctrlbit        = (1 << 4),
 500         }, {
 501                 .name           = "jpeg",
 502                 .parent         = &clk_div_d1_bus.clk,
 503                 .enable         = s5pc100_d1_1_ctrl,
 504                 .ctrlbit        = (1 << 5),
 505         }, {
 506                 .name           = "mipi-dsim",
 507                 .parent         = &clk_div_d1_bus.clk,
 508                 .enable         = s5pc100_d1_1_ctrl,
 509                 .ctrlbit        = (1 << 6),
 510         }, {
 511                 .name           = "mipi-csis",
 512                 .parent         = &clk_div_d1_bus.clk,
 513                 .enable         = s5pc100_d1_1_ctrl,
 514                 .ctrlbit        = (1 << 7),
 515         }, {
 516                 .name           = "g3d",
 517                 .parent         = &clk_div_d1_bus.clk,
 518                 .enable         = s5pc100_d1_0_ctrl,
 519                 .ctrlbit        = (1 << 8),
 520         }, {
 521                 .name           = "tv",
 522                 .parent         = &clk_div_d1_bus.clk,
 523                 .enable         = s5pc100_d1_2_ctrl,
 524                 .ctrlbit        = (1 << 0),
 525         }, {
 526                 .name           = "vp",
 527                 .parent         = &clk_div_d1_bus.clk,
 528                 .enable         = s5pc100_d1_2_ctrl,
 529                 .ctrlbit        = (1 << 1),
 530         }, {
 531                 .name           = "mixer",
 532                 .parent         = &clk_div_d1_bus.clk,
 533                 .enable         = s5pc100_d1_2_ctrl,
 534                 .ctrlbit        = (1 << 2),
 535         }, {
 536                 .name           = "hdmi",
 537                 .parent         = &clk_div_d1_bus.clk,
 538                 .enable         = s5pc100_d1_2_ctrl,
 539                 .ctrlbit        = (1 << 3),
 540         }, {
 541                 .name           = "mfc",
 542                 .parent         = &clk_div_d1_bus.clk,
 543                 .enable         = s5pc100_d1_2_ctrl,
 544                 .ctrlbit        = (1 << 4),
 545         }, {
 546                 .name           = "apc",
 547                 .parent         = &clk_div_d1_bus.clk,
 548                 .enable         = s5pc100_d1_3_ctrl,
 549                 .ctrlbit        = (1 << 2),
 550         }, {
 551                 .name           = "iec",
 552                 .parent         = &clk_div_d1_bus.clk,
 553                 .enable         = s5pc100_d1_3_ctrl,
 554                 .ctrlbit        = (1 << 3),
 555         }, {
 556                 .name           = "systimer",
 557                 .parent         = &clk_div_d1_bus.clk,
 558                 .enable         = s5pc100_d1_3_ctrl,
 559                 .ctrlbit        = (1 << 7),
 560         }, {
 561                 .name           = "watchdog",
 562                 .parent         = &clk_div_d1_bus.clk,
 563                 .enable         = s5pc100_d1_3_ctrl,
 564                 .ctrlbit        = (1 << 8),
 565         }, {
 566                 .name           = "rtc",
 567                 .parent         = &clk_div_d1_bus.clk,
 568                 .enable         = s5pc100_d1_3_ctrl,
 569                 .ctrlbit        = (1 << 9),
 570         }, {
 571                 .name           = "i2c",
 572                 .devname        = "s3c2440-i2c.0",
 573                 .parent         = &clk_div_d1_bus.clk,
 574                 .enable         = s5pc100_d1_4_ctrl,
 575                 .ctrlbit        = (1 << 4),
 576         }, {
 577                 .name           = "i2c",
 578                 .devname        = "s3c2440-i2c.1",
 579                 .parent         = &clk_div_d1_bus.clk,
 580                 .enable         = s5pc100_d1_4_ctrl,
 581                 .ctrlbit        = (1 << 5),
 582         }, {
 583                 .name           = "spi",
 584                 .devname        = "s3c64xx-spi.0",
 585                 .parent         = &clk_div_d1_bus.clk,
 586                 .enable         = s5pc100_d1_4_ctrl,
 587                 .ctrlbit        = (1 << 6),
 588         }, {
 589                 .name           = "spi",
 590                 .devname        = "s3c64xx-spi.1",
 591                 .parent         = &clk_div_d1_bus.clk,
 592                 .enable         = s5pc100_d1_4_ctrl,
 593                 .ctrlbit        = (1 << 7),
 594         }, {
 595                 .name           = "spi",
 596                 .devname        = "s3c64xx-spi.2",
 597                 .parent         = &clk_div_d1_bus.clk,
 598                 .enable         = s5pc100_d1_4_ctrl,
 599                 .ctrlbit        = (1 << 8),
 600         }, {
 601                 .name           = "irda",
 602                 .parent         = &clk_div_d1_bus.clk,
 603                 .enable         = s5pc100_d1_4_ctrl,
 604                 .ctrlbit        = (1 << 9),
 605         }, {
 606                 .name           = "ccan",
 607                 .parent         = &clk_div_d1_bus.clk,
 608                 .enable         = s5pc100_d1_4_ctrl,
 609                 .ctrlbit        = (1 << 10),
 610         }, {
 611                 .name           = "ccan",
 612                 .parent         = &clk_div_d1_bus.clk,
 613                 .enable         = s5pc100_d1_4_ctrl,
 614                 .ctrlbit        = (1 << 11),
 615         }, {
 616                 .name           = "hsitx",
 617                 .parent         = &clk_div_d1_bus.clk,
 618                 .enable         = s5pc100_d1_4_ctrl,
 619                 .ctrlbit        = (1 << 12),
 620         }, {
 621                 .name           = "hsirx",
 622                 .parent         = &clk_div_d1_bus.clk,
 623                 .enable         = s5pc100_d1_4_ctrl,
 624                 .ctrlbit        = (1 << 13),
 625         }, {
 626                 .name           = "iis",
 627                 .devname        = "samsung-i2s.0",
 628                 .parent         = &clk_div_pclkd1.clk,
 629                 .enable         = s5pc100_d1_5_ctrl,
 630                 .ctrlbit        = (1 << 0),
 631         }, {
 632                 .name           = "iis",
 633                 .devname        = "samsung-i2s.1",
 634                 .parent         = &clk_div_pclkd1.clk,
 635                 .enable         = s5pc100_d1_5_ctrl,
 636                 .ctrlbit        = (1 << 1),
 637         }, {
 638                 .name           = "iis",
 639                 .devname        = "samsung-i2s.2",
 640                 .parent         = &clk_div_pclkd1.clk,
 641                 .enable         = s5pc100_d1_5_ctrl,
 642                 .ctrlbit        = (1 << 2),
 643         }, {
 644                 .name           = "ac97",
 645                 .parent         = &clk_div_pclkd1.clk,
 646                 .enable         = s5pc100_d1_5_ctrl,
 647                 .ctrlbit        = (1 << 3),
 648         }, {
 649                 .name           = "pcm",
 650                 .devname        = "samsung-pcm.0",
 651                 .parent         = &clk_div_pclkd1.clk,
 652                 .enable         = s5pc100_d1_5_ctrl,
 653                 .ctrlbit        = (1 << 4),
 654         }, {
 655                 .name           = "pcm",
 656                 .devname        = "samsung-pcm.1",
 657                 .parent         = &clk_div_pclkd1.clk,
 658                 .enable         = s5pc100_d1_5_ctrl,
 659                 .ctrlbit        = (1 << 5),
 660         }, {
 661                 .name           = "spdif",
 662                 .parent         = &clk_div_pclkd1.clk,
 663                 .enable         = s5pc100_d1_5_ctrl,
 664                 .ctrlbit        = (1 << 6),
 665         }, {
 666                 .name           = "adc",
 667                 .parent         = &clk_div_pclkd1.clk,
 668                 .enable         = s5pc100_d1_5_ctrl,
 669                 .ctrlbit        = (1 << 7),
 670         }, {
 671                 .name           = "keypad",
 672                 .parent         = &clk_div_pclkd1.clk,
 673                 .enable         = s5pc100_d1_5_ctrl,
 674                 .ctrlbit        = (1 << 8),
 675         }, {
 676                 .name           = "spi_48m",
 677                 .devname        = "s3c64xx-spi.0",
 678                 .parent         = &clk_mout_48m.clk,
 679                 .enable         = s5pc100_sclk0_ctrl,
 680                 .ctrlbit        = (1 << 7),
 681         }, {
 682                 .name           = "spi_48m",
 683                 .devname        = "s3c64xx-spi.1",
 684                 .parent         = &clk_mout_48m.clk,
 685                 .enable         = s5pc100_sclk0_ctrl,
 686                 .ctrlbit        = (1 << 8),
 687         }, {
 688                 .name           = "spi_48m",
 689                 .devname        = "s3c64xx-spi.2",
 690                 .parent         = &clk_mout_48m.clk,
 691                 .enable         = s5pc100_sclk0_ctrl,
 692                 .ctrlbit        = (1 << 9),
 693         }, {
 694                 .name           = "mmc_48m",
 695                 .devname        = "s3c-sdhci.0",
 696                 .parent         = &clk_mout_48m.clk,
 697                 .enable         = s5pc100_sclk0_ctrl,
 698                 .ctrlbit        = (1 << 15),
 699         }, {
 700                 .name           = "mmc_48m",
 701                 .devname        = "s3c-sdhci.1",
 702                 .parent         = &clk_mout_48m.clk,
 703                 .enable         = s5pc100_sclk0_ctrl,
 704                 .ctrlbit        = (1 << 16),
 705         }, {
 706                 .name           = "mmc_48m",
 707                 .devname        = "s3c-sdhci.2",
 708                 .parent         = &clk_mout_48m.clk,
 709                 .enable         = s5pc100_sclk0_ctrl,
 710                 .ctrlbit        = (1 << 17),
 711         },
 712 };
 713
 714 static struct clk clk_vclk54m = {
 715         .name           = "vclk_54m",
 716         .rate           = 54000000,
 717 };
 718
 719 static struct clk clk_i2scdclk0 = {
 720         .name           = "i2s_cdclk0",
 721 };
 722
 723 static struct clk clk_i2scdclk1 = {
 724         .name           = "i2s_cdclk1",
 725 };
 726
 727 static struct clk clk_i2scdclk2 = {
 728         .name           = "i2s_cdclk2",
 729 };
 730
 731 static struct clk clk_pcmcdclk0 = {
 732         .name           = "pcm_cdclk0",
 733 };
 734
 735 static struct clk clk_pcmcdclk1 = {
 736         .name           = "pcm_cdclk1",
 737 };
 738
 739 static struct clk *clk_src_group1_list[] = {
 740         [0] = &clk_mout_epll.clk,
 741         [1] = &clk_div_mpll2.clk,
 742         [2] = &clk_fin_epll,
 743         [3] = &clk_mout_hpll.clk,
 744 };
 745
 746 struct clksrc_sources clk_src_group1 = {
 747         .sources        = clk_src_group1_list,
 748         .nr_sources     = ARRAY_SIZE(clk_src_group1_list),
 749 };
 750
 751 static struct clk *clk_src_group2_list[] = {
 752         [0] = &clk_mout_epll.clk,
 753         [1] = &clk_div_mpll.clk,
 754 };
 755
 756 struct clksrc_sources clk_src_group2 = {
 757         .sources        = clk_src_group2_list,
 758         .nr_sources     = ARRAY_SIZE(clk_src_group2_list),
 759 };
 760
 761 static struct clk *clk_src_group3_list[] = {
 762         [0] = &clk_mout_epll.clk,
 763         [1] = &clk_div_mpll.clk,
 764         [2] = &clk_fin_epll,
 765         [3] = &clk_i2scdclk0,
 766         [4] = &clk_pcmcdclk0,
 767         [5] = &clk_mout_hpll.clk,
 768 };
 769
 770 struct clksrc_sources clk_src_group3 = {
 771         .sources        = clk_src_group3_list,
 772         .nr_sources     = ARRAY_SIZE(clk_src_group3_list),
 773 };
 774
 775 static struct clksrc_clk clk_sclk_audio0 = {
 776         .clk    = {
 777                 .name           = "sclk_audio",
 778                 .devname        = "samsung-pcm.0",
 779                 .ctrlbit        = (1 << 8),
 780                 .enable         = s5pc100_sclk1_ctrl,
 781         },
 782         .sources = &clk_src_group3,
 783         .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 3 },
 784         .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
 785 };
 786
 787 static struct clk *clk_src_group4_list[] = {
 788         [0] = &clk_mout_epll.clk,
 789         [1] = &clk_div_mpll.clk,
 790         [2] = &clk_fin_epll,
 791         [3] = &clk_i2scdclk1,
 792         [4] = &clk_pcmcdclk1,
 793         [5] = &clk_mout_hpll.clk,
 794 };
 795
 796 struct clksrc_sources clk_src_group4 = {
 797         .sources        = clk_src_group4_list,
 798         .nr_sources     = ARRAY_SIZE(clk_src_group4_list),
 799 };
 800
 801 static struct clksrc_clk clk_sclk_audio1 = {
 802         .clk    = {
 803                 .name           = "sclk_audio",
 804                 .devname        = "samsung-pcm.1",
 805                 .ctrlbit        = (1 << 9),
 806                 .enable         = s5pc100_sclk1_ctrl,
 807         },
 808         .sources = &clk_src_group4,
 809         .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 3 },
 810         .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
 811 };
 812
 813 static struct clk *clk_src_group5_list[] = {
 814         [0] = &clk_mout_epll.clk,
 815         [1] = &clk_div_mpll.clk,
 816         [2] = &clk_fin_epll,
 817         [3] = &clk_i2scdclk2,
 818         [4] = &clk_mout_hpll.clk,
 819 };
 820
 821 struct clksrc_sources clk_src_group5 = {
 822         .sources        = clk_src_group5_list,
 823         .nr_sources     = ARRAY_SIZE(clk_src_group5_list),
 824 };
 825
 826 static struct clksrc_clk clk_sclk_audio2 = {
 827         .clk    = {
 828                 .name           = "sclk_audio",
 829                 .devname        = "samsung-pcm.2",
 830                 .ctrlbit        = (1 << 10),
 831                 .enable         = s5pc100_sclk1_ctrl,
 832         },
 833         .sources = &clk_src_group5,
 834         .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 3 },
 835         .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
 836 };
 837
 838 static struct clk *clk_src_group6_list[] = {
 839         [0] = &s5p_clk_27m,
 840         [1] = &clk_vclk54m,
 841         [2] = &clk_div_hdmi.clk,
 842 };
 843
 844 struct clksrc_sources clk_src_group6 = {
 845         .sources        = clk_src_group6_list,
 846         .nr_sources     = ARRAY_SIZE(clk_src_group6_list),
 847 };
 848
 849 static struct clk *clk_src_group7_list[] = {
 850         [0] = &clk_mout_epll.clk,
 851         [1] = &clk_div_mpll.clk,
 852         [2] = &clk_mout_hpll.clk,
 853         [3] = &clk_vclk54m,
 854 };
 855
 856 struct clksrc_sources clk_src_group7 = {
 857         .sources        = clk_src_group7_list,
 858         .nr_sources     = ARRAY_SIZE(clk_src_group7_list),
 859 };
 860
 861 static struct clk *clk_src_mmc0_list[] = {
 862         [0] = &clk_mout_epll.clk,
 863         [1] = &clk_div_mpll.clk,
 864         [2] = &clk_fin_epll,
 865 };
 866
 867 struct clksrc_sources clk_src_mmc0 = {
 868         .sources        = clk_src_mmc0_list,
 869         .nr_sources     = ARRAY_SIZE(clk_src_mmc0_list),
 870 };
 871
 872 static struct clk *clk_src_mmc12_list[] = {
 873         [0] = &clk_mout_epll.clk,
 874         [1] = &clk_div_mpll.clk,
 875         [2] = &clk_fin_epll,
 876         [3] = &clk_mout_hpll.clk,
 877 };
 878
 879 struct clksrc_sources clk_src_mmc12 = {
 880         .sources        = clk_src_mmc12_list,
 881         .nr_sources     = ARRAY_SIZE(clk_src_mmc12_list),
 882 };
 883
 884 static struct clk *clk_src_irda_usb_list[] = {
 885         [0] = &clk_mout_epll.clk,
 886         [1] = &clk_div_mpll.clk,
 887         [2] = &clk_fin_epll,
 888         [3] = &clk_mout_hpll.clk,
 889 };
 890
 891 struct clksrc_sources clk_src_irda_usb = {
 892         .sources        = clk_src_irda_usb_list,
 893         .nr_sources     = ARRAY_SIZE(clk_src_irda_usb_list),
 894 };
 895
 896 static struct clk *clk_src_pwi_list[] = {
 897         [0] = &clk_fin_epll,
 898         [1] = &clk_mout_epll.clk,
 899         [2] = &clk_div_mpll.clk,
 900 };
 901
 902 struct clksrc_sources clk_src_pwi = {
 903         .sources        = clk_src_pwi_list,
 904         .nr_sources     = ARRAY_SIZE(clk_src_pwi_list),
 905 };
 906
 907 static struct clk *clk_sclk_spdif_list[] = {
 908         [0] = &clk_sclk_audio0.clk,
 909         [1] = &clk_sclk_audio1.clk,
 910         [2] = &clk_sclk_audio2.clk,
 911 };
 912
 913 struct clksrc_sources clk_src_sclk_spdif = {
 914         .sources        = clk_sclk_spdif_list,
 915         .nr_sources     = ARRAY_SIZE(clk_sclk_spdif_list),
 916 };
 917
 918 static struct clksrc_clk clk_sclk_spdif = {
 919         .clk    = {
 920                 .name           = "sclk_spdif",
 921                 .ctrlbit        = (1 << 11),
 922                 .enable         = s5pc100_sclk1_ctrl,
 923                 .ops            = &s5p_sclk_spdif_ops,
 924         },
 925         .sources = &clk_src_sclk_spdif,
 926         .reg_src = { .reg = S5P_CLK_SRC3, .shift = 24, .size = 2 },
 927 };
 928
 929 static struct clksrc_clk clksrcs[] = {
 930         {
 931                 .clk    = {
 932                         .name           = "sclk_spi",
 933                         .devname        = "s3c64xx-spi.0",
 934                         .ctrlbit        = (1 << 4),
 935                         .enable         = s5pc100_sclk0_ctrl,
 936
 937                 },
 938                 .sources = &clk_src_group1,
 939                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
 940                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
 941         }, {
 942                 .clk    = {
 943                         .name           = "sclk_spi",
 944                         .devname        = "s3c64xx-spi.1",
 945                         .ctrlbit        = (1 << 5),
 946                         .enable         = s5pc100_sclk0_ctrl,
 947
 948                 },
 949                 .sources = &clk_src_group1,
 950                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
 951                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
 952         }, {
 953                 .clk    = {
 954                         .name           = "sclk_spi",
 955                         .devname        = "s3c64xx-spi.2",
 956                         .ctrlbit        = (1 << 6),
 957                         .enable         = s5pc100_sclk0_ctrl,
 958
 959                 },
 960                 .sources = &clk_src_group1,
 961                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
 962                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
 963         }, {
 964                 .clk    = {
 965                         .name           = "uclk1",
 966                         .ctrlbit        = (1 << 3),
 967                         .enable         = s5pc100_sclk0_ctrl,
 968
 969                 },
 970                 .sources = &clk_src_group2,
 971                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
 972                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
 973         }, {
 974                 .clk    = {
 975                         .name           = "sclk_mixer",
 976                         .ctrlbit        = (1 << 6),
 977                         .enable         = s5pc100_sclk0_ctrl,
 978
 979                 },
 980                 .sources = &clk_src_group6,
 981                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 28, .size = 2 },
 982         }, {
 983                 .clk    = {
 984                         .name           = "sclk_lcd",
 985                         .ctrlbit        = (1 << 0),
 986                         .enable         = s5pc100_sclk1_ctrl,
 987
 988                 },
 989                 .sources = &clk_src_group7,
 990                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 12, .size = 2 },
 991                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
 992         }, {
 993                 .clk    = {
 994                         .name           = "sclk_fimc",
 995                         .devname        = "s5p-fimc.0",
 996                         .ctrlbit        = (1 << 1),
 997                         .enable         = s5pc100_sclk1_ctrl,
 998
 999                 },
1000                 .sources = &clk_src_group7,
1001                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 16, .size = 2 },
1002                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
1003         }, {
1004                 .clk    = {
1005                         .name           = "sclk_fimc",
1006                         .devname        = "s5p-fimc.1",
1007                         .ctrlbit        = (1 << 2),
1008                         .enable         = s5pc100_sclk1_ctrl,
1009
1010                 },
1011                 .sources = &clk_src_group7,
1012                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 20, .size = 2 },
1013                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
1014         }, {
1015                 .clk    = {
1016                         .name           = "sclk_fimc",
1017                         .devname        = "s5p-fimc.2",
1018                         .ctrlbit        = (1 << 3),
1019                         .enable         = s5pc100_sclk1_ctrl,
1020
1021                 },
1022                 .sources = &clk_src_group7,
1023                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 24, .size = 2 },
1024                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 },
1025         }, {
1026                 .clk    = {
1027                         .name           = "sclk_mmc",
1028                         .devname        = "s3c-sdhci.0",
1029                         .ctrlbit        = (1 << 12),
1030                         .enable         = s5pc100_sclk1_ctrl,
1031
1032                 },
1033                 .sources = &clk_src_mmc0,
1034                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
1035                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
1036         }, {
1037                 .clk    = {
1038                         .name           = "sclk_mmc",
1039                         .devname        = "s3c-sdhci.1",
1040                         .ctrlbit        = (1 << 13),
1041                         .enable         = s5pc100_sclk1_ctrl,
1042
1043                 },
1044                 .sources = &clk_src_mmc12,
1045                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
1046                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
1047         }, {
1048                 .clk    = {
1049                         .name           = "sclk_mmc",
1050                         .devname        = "s3c-sdhci.2",
1051                         .ctrlbit        = (1 << 14),
1052                         .enable         = s5pc100_sclk1_ctrl,
1053
1054                 },
1055                 .sources = &clk_src_mmc12,
1056                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1057                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1058         }, {
1059                 .clk    = {
1060                         .name           = "sclk_irda",
1061                         .ctrlbit        = (1 << 10),
1062                         .enable         = s5pc100_sclk0_ctrl,
1063
1064                 },
1065                 .sources = &clk_src_irda_usb,
1066                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1067                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1068         }, {
1069                 .clk    = {
1070                         .name           = "sclk_irda",
1071                         .ctrlbit        = (1 << 10),
1072                         .enable         = s5pc100_sclk0_ctrl,
1073
1074                 },
1075                 .sources = &clk_src_mmc12,
1076                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 2 },
1077                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 16, .size = 4 },
1078         }, {
1079                 .clk    = {
1080                         .name           = "sclk_pwi",
1081                         .ctrlbit        = (1 << 1),
1082                         .enable         = s5pc100_sclk0_ctrl,
1083
1084                 },
1085                 .sources = &clk_src_pwi,
1086                 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 0, .size = 2 },
1087                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 3 },
1088         }, {
1089                 .clk    = {
1090                         .name           = "sclk_uhost",
1091                         .ctrlbit        = (1 << 11),
1092                         .enable         = s5pc100_sclk0_ctrl,
1093
1094                 },
1095                 .sources = &clk_src_irda_usb,
1096                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 2 },
1097                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 20, .size = 4 },
1098         },
1099 };
1100
1101 /* Clock initialisation code */
1102 static struct clksrc_clk *sysclks[] = {
1103         &clk_mout_apll,
1104         &clk_mout_epll,
1105         &clk_mout_mpll,
1106         &clk_mout_hpll,
1107         &clk_mout_href,
1108         &clk_mout_48m,
1109         &clk_div_apll,
1110         &clk_div_arm,
1111         &clk_div_d0_bus,
1112         &clk_div_pclkd0,
1113         &clk_div_secss,
1114         &clk_div_apll2,
1115         &clk_mout_am,
1116         &clk_div_d1_bus,
1117         &clk_div_mpll2,
1118         &clk_div_mpll,
1119         &clk_mout_onenand,
1120         &clk_div_onenand,
1121         &clk_div_pclkd1,
1122         &clk_div_cam,
1123         &clk_div_hdmi,
1124         &clk_sclk_audio0,
1125         &clk_sclk_audio1,
1126         &clk_sclk_audio2,
1127         &clk_sclk_spdif,
1128 };
1129
1130 void __init_or_cpufreq s5pc100_setup_clocks(void)
1131 {
1132         unsigned long xtal;
1133         unsigned long arm;
1134         unsigned long hclkd0;
1135         unsigned long hclkd1;
1136         unsigned long pclkd0;
1137         unsigned long pclkd1;
1138         unsigned long apll;
1139         unsigned long mpll;
1140         unsigned long epll;
1141         unsigned long hpll;
1142         unsigned int ptr;
1143
1144         /* Set S5PC100 functions for clk_fout_epll */
1145         clk_fout_epll.enable = s5p_epll_enable;
1146         clk_fout_epll.ops = &s5pc100_epll_ops;
1147
1148         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1149
1150         xtal = clk_get_rate(&clk_xtal);
1151
1152         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1153
1154         apll = s5p_get_pll65xx(xtal, __raw_readl(S5P_APLL_CON));
1155         mpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_MPLL_CON));
1156         epll = s5p_get_pll65xx(xtal, __raw_readl(S5P_EPLL_CON));
1157         hpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_HPLL_CON));
1158
1159         printk(KERN_INFO "S5PC100: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz, E=%ld.%ldMHz, H=%ld.%ldMHz\n",
1160                         print_mhz(apll), print_mhz(mpll), print_mhz(epll), print_mhz(hpll));
1161
1162         clk_fout_apll.rate = apll;
1163         clk_fout_mpll.rate = mpll;
1164         clk_fout_epll.rate = epll;
1165         clk_mout_hpll.clk.rate = hpll;
1166
1167         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1168                 s3c_set_clksrc(&clksrcs[ptr], true);
1169
1170         arm = clk_get_rate(&clk_div_arm.clk);
1171         hclkd0 = clk_get_rate(&clk_div_d0_bus.clk);
1172         pclkd0 = clk_get_rate(&clk_div_pclkd0.clk);
1173         hclkd1 = clk_get_rate(&clk_div_d1_bus.clk);
1174         pclkd1 = clk_get_rate(&clk_div_pclkd1.clk);
1175
1176         printk(KERN_INFO "S5PC100: HCLKD0=%ld.%ldMHz, HCLKD1=%ld.%ldMHz, PCLKD0=%ld.%ldMHz, PCLKD1=%ld.%ldMHz\n",
1177                         print_mhz(hclkd0), print_mhz(hclkd1), print_mhz(pclkd0), print_mhz(pclkd1));
1178
1179         clk_f.rate = arm;
1180         clk_h.rate = hclkd1;
1181         clk_p.rate = pclkd1;
1182 }
1183
1184 /*
1185  * The following clocks will be enabled during clock initialization.
1186  */
1187 static struct clk init_clocks[] = {
1188         {
1189                 .name           = "tzic",
1190                 .parent         = &clk_div_d0_bus.clk,
1191                 .enable         = s5pc100_d0_0_ctrl,
1192                 .ctrlbit        = (1 << 1),
1193         }, {
1194                 .name           = "intc",
1195                 .parent         = &clk_div_d0_bus.clk,
1196                 .enable         = s5pc100_d0_0_ctrl,
1197                 .ctrlbit        = (1 << 0),
1198         }, {
1199                 .name           = "ebi",
1200                 .parent         = &clk_div_d0_bus.clk,
1201                 .enable         = s5pc100_d0_1_ctrl,
1202                 .ctrlbit        = (1 << 5),
1203         }, {
1204                 .name           = "intmem",
1205                 .parent         = &clk_div_d0_bus.clk,
1206                 .enable         = s5pc100_d0_1_ctrl,
1207                 .ctrlbit        = (1 << 4),
1208         }, {
1209                 .name           = "sromc",
1210                 .parent         = &clk_div_d0_bus.clk,
1211                 .enable         = s5pc100_d0_1_ctrl,
1212                 .ctrlbit        = (1 << 1),
1213         }, {
1214                 .name           = "dmc",
1215                 .parent         = &clk_div_d0_bus.clk,
1216                 .enable         = s5pc100_d0_1_ctrl,
1217                 .ctrlbit        = (1 << 0),
1218         }, {
1219                 .name           = "chipid",
1220                 .parent         = &clk_div_d0_bus.clk,
1221                 .enable         = s5pc100_d0_1_ctrl,
1222                 .ctrlbit        = (1 << 0),
1223         }, {
1224                 .name           = "gpio",
1225                 .parent         = &clk_div_d1_bus.clk,
1226                 .enable         = s5pc100_d1_3_ctrl,
1227                 .ctrlbit        = (1 << 1),
1228         }, {
1229                 .name           = "uart",
1230                 .devname        = "s3c6400-uart.0",
1231                 .parent         = &clk_div_d1_bus.clk,
1232                 .enable         = s5pc100_d1_4_ctrl,
1233                 .ctrlbit        = (1 << 0),
1234         }, {
1235                 .name           = "uart",
1236                 .devname        = "s3c6400-uart.1",
1237                 .parent         = &clk_div_d1_bus.clk,
1238                 .enable         = s5pc100_d1_4_ctrl,
1239                 .ctrlbit        = (1 << 1),
1240         }, {
1241                 .name           = "uart",
1242                 .devname        = "s3c6400-uart.2",
1243                 .parent         = &clk_div_d1_bus.clk,
1244                 .enable         = s5pc100_d1_4_ctrl,
1245                 .ctrlbit        = (1 << 2),
1246         }, {
1247                 .name           = "uart",
1248                 .devname        = "s3c6400-uart.3",
1249                 .parent         = &clk_div_d1_bus.clk,
1250                 .enable         = s5pc100_d1_4_ctrl,
1251                 .ctrlbit        = (1 << 3),
1252         }, {
1253                 .name           = "timers",
1254                 .parent         = &clk_div_d1_bus.clk,
1255                 .enable         = s5pc100_d1_3_ctrl,
1256                 .ctrlbit        = (1 << 6),
1257         },
1258 };
1259
1260 static struct clk *clks[] __initdata = {
1261         &clk_ext,
1262         &clk_i2scdclk0,
1263         &clk_i2scdclk1,
1264         &clk_i2scdclk2,
1265         &clk_pcmcdclk0,
1266         &clk_pcmcdclk1,
1267 };
1268
1269 void __init s5pc100_register_clocks(void)
1270 {
1271         int ptr;
1272
1273         s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1274
1275         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1276                 s3c_register_clksrc(sysclks[ptr], 1);
1277
1278         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1279         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1280
1281         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1282         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1283
1284         s3c24xx_register_clock(&dummy_apb_pclk);
1285
1286         s3c_pwmclk_init();
1287 }