arch/arm/mach-s5pc100/include/mach/map.h

   1 /* linux/arch/arm/mach-s5pc100/include/mach/map.h
   2  *
   3  * Copyright 2009 Samsung Electronics Co.
   4  *      Byungho Min <bhmin@samsung.com>
   5  *
   6  * S5PC100 - Memory map definitions
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #ifndef __ASM_ARCH_MAP_H
  14 #define __ASM_ARCH_MAP_H __FILE__
  15
  16 #include <plat/map-base.h>
  17 #include <plat/map-s5p.h>
  18
  19 /*
  20  * map-base.h has already defined virtual memory address
  21  * S3C_VA_IRQ           S3C_ADDR(0x00000000)    irq controller(s)
  22  * S3C_VA_SYS           S3C_ADDR(0x00100000)    system control
  23  * S3C_VA_MEM           S3C_ADDR(0x00200000)    system control (not used)
  24  * S3C_VA_TIMER         S3C_ADDR(0x00300000)    timer block
  25  * S3C_VA_WATCHDOG      S3C_ADDR(0x00400000)    watchdog
  26  * S3C_VA_UART          S3C_ADDR(0x01000000)    UART
  27  *
  28  * S5PC100 specific virtual memory address can be defined here
  29  * S5PC1XX_VA_GPIO      S3C_ADDR(0x00500000)    GPIO
  30  *
  31  */
  32
  33 #define S5PC100_PA_ONENAND_BUF  (0xB0000000)
  34 #define S5PC100_SZ_ONENAND_BUF  (SZ_256M - SZ_32M)
  35
  36 /* Chip ID */
  37
  38 #define S5PC100_PA_CHIPID       (0xE0000000)
  39 #define S5P_PA_CHIPID           S5PC100_PA_CHIPID
  40
  41 #define S5PC100_PA_SYSCON       (0xE0100000)
  42 #define S5P_PA_SYSCON           S5PC100_PA_SYSCON
  43
  44 #define S5PC100_PA_OTHERS       (0xE0200000)
  45 #define S5PC100_VA_OTHERS       (S3C_VA_SYS + 0x10000)
  46
  47 #define S5P_PA_GPIO             (0xE0300000)
  48 #define S5PC1XX_VA_GPIO         S3C_ADDR(0x00500000)
  49
  50 /* Interrupt */
  51 #define S5PC100_PA_VIC          (0xE4000000)
  52 #define S5PC100_VA_VIC          S3C_VA_IRQ
  53 #define S5PC100_PA_VIC_OFFSET   0x100000
  54 #define S5PC100_VA_VIC_OFFSET   0x10000
  55 #define S5PC1XX_PA_VIC(x)       (S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET))
  56 #define S5PC1XX_VA_VIC(x)       (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET))
  57 #define S5P_PA_VIC0             S5PC1XX_PA_VIC(0)
  58 #define S5P_PA_VIC1             S5PC1XX_PA_VIC(1)
  59 #define S5P_PA_VIC2             S5PC1XX_PA_VIC(2)
  60
  61
  62 #define S5PC100_PA_ONENAND      (0xE7100000)
  63
  64 /* DMA */
  65 #define S5PC100_PA_MDMA         (0xE8100000)
  66 #define S5PC100_PA_PDMA0        (0xE9000000)
  67 #define S5PC100_PA_PDMA1        (0xE9200000)
  68
  69 /* Timer */
  70 #define S5PC100_PA_TIMER        (0xEA000000)
  71 #define S5P_PA_TIMER            S5PC100_PA_TIMER
  72
  73 #define S5PC100_PA_SYSTIMER     (0xEA100000)
  74
  75 #define S5PC100_PA_UART         (0xEC000000)
  76
  77 #define S5P_PA_UART0            (S5PC100_PA_UART + 0x0)
  78 #define S5P_PA_UART1            (S5PC100_PA_UART + 0x400)
  79 #define S5P_PA_UART2            (S5PC100_PA_UART + 0x800)
  80 #define S5P_PA_UART3            (S5PC100_PA_UART + 0xC00)
  81 #define S5P_SZ_UART             SZ_256
  82
  83 #define S5PC100_PA_IIC0         (0xEC100000)
  84 #define S5PC100_PA_IIC1         (0xEC200000)
  85
  86 /* SPI */
  87 #define S5PC100_PA_SPI0         0xEC300000
  88 #define S5PC100_PA_SPI1         0xEC400000
  89 #define S5PC100_PA_SPI2         0xEC500000
  90
  91 /* USB HS OTG */
  92 #define S5PC100_PA_USB_HSOTG    (0xED200000)
  93 #define S5PC100_PA_USB_HSPHY    (0xED300000)
  94
  95 #define S5PC100_PA_FB           (0xEE000000)
  96
  97 #define S5PC100_PA_I2S0         (0xF2000000)
  98 #define S5PC100_PA_I2S1         (0xF2100000)
  99 #define S5PC100_PA_I2S2         (0xF2200000)
 100
 101 #define S5PC100_PA_AC97         0xF2300000
 102
 103 /* PCM */
 104 #define S5PC100_PA_PCM0         0xF2400000
 105 #define S5PC100_PA_PCM1         0xF2500000
 106
 107 /* KEYPAD */
 108 #define S5PC100_PA_KEYPAD       (0xF3100000)
 109
 110 #define S5PC100_PA_HSMMC(x)     (0xED800000 + ((x) * 0x100000))
 111
 112 #define S5PC100_PA_SDRAM        (0x20000000)
 113 #define S5P_PA_SDRAM            S5PC100_PA_SDRAM
 114
 115 /* compatibiltiy defines. */
 116 #define S3C_PA_UART             S5PC100_PA_UART
 117 #define S3C_PA_IIC              S5PC100_PA_IIC0
 118 #define S3C_PA_IIC1             S5PC100_PA_IIC1
 119 #define S3C_PA_FB               S5PC100_PA_FB
 120 #define S3C_PA_G2D              S5PC100_PA_G2D
 121 #define S3C_PA_G3D              S5PC100_PA_G3D
 122 #define S3C_PA_JPEG             S5PC100_PA_JPEG
 123 #define S3C_PA_ROTATOR          S5PC100_PA_ROTATOR
 124 #define S5P_VA_VIC0             S5PC1XX_VA_VIC(0)
 125 #define S5P_VA_VIC1             S5PC1XX_VA_VIC(1)
 126 #define S5P_VA_VIC2             S5PC1XX_VA_VIC(2)
 127 #define S3C_PA_USB_HSOTG        S5PC100_PA_USB_HSOTG
 128 #define S3C_PA_USB_HSPHY        S5PC100_PA_USB_HSPHY
 129 #define S3C_PA_HSMMC0           S5PC100_PA_HSMMC(0)
 130 #define S3C_PA_HSMMC1           S5PC100_PA_HSMMC(1)
 131 #define S3C_PA_HSMMC2           S5PC100_PA_HSMMC(2)
 132 #define S3C_PA_KEYPAD           S5PC100_PA_KEYPAD
 133 #define S3C_PA_TSADC            S5PC100_PA_TSADC
 134 #define S3C_PA_ONENAND          S5PC100_PA_ONENAND
 135 #define S3C_PA_ONENAND_BUF      S5PC100_PA_ONENAND_BUF
 136 #define S3C_SZ_ONENAND_BUF      S5PC100_SZ_ONENAND_BUF
 137
 138 #endif /* __ASM_ARCH_C100_MAP_H */