arch/arm/mach-s5pv310/include/mach/entry-macro.S

   1 /* arch/arm/mach-s5pv310/include/mach/entry-macro.S
   2  *
   3  * Cloned from arch/arm/mach-realview/include/mach/entry-macro.S
   4  *
   5  * Low-level IRQ helper macros for S5PV310 platforms
   6  *
   7  * This file is licensed under  the terms of the GNU General Public
   8  * License version 2. This program is licensed "as is" without any
   9  * warranty of any kind, whether express or implied.
  10 */
  11
  12 #include <mach/hardware.h>
  13 #include <asm/hardware/gic.h>
  14
  15                 .macro  disable_fiq
  16                 .endm
  17
  18                 .macro  get_irqnr_preamble, base, tmp
  19                 ldr     \base, =gic_cpu_base_addr
  20                 ldr     \base, [\base]
  21                 .endm
  22
  23                 .macro  arch_ret_to_user, tmp1, tmp2
  24                 .endm
  25
  26                 /*
  27                  * The interrupt numbering scheme is defined in the
  28                  * interrupt controller spec.  To wit:
  29                  *
  30                  * Interrupts 0-15 are IPI
  31                  * 16-28 are reserved
  32                  * 29-31 are local.  We allow 30 to be used for the watchdog.
  33                  * 32-1020 are global
  34                  * 1021-1022 are reserved
  35                  * 1023 is "spurious" (no interrupt)
  36                  *
  37                  * For now, we ignore all local interrupts so only return an interrupt if it's
  38                  * between 30 and 1020.  The test_for_ipi routine below will pick up on IPIs.
  39                  *
  40                  * A simple read from the controller will tell us the number of the highest
  41                  * priority enabled interrupt.  We then just need to check whether it is in the
  42                  * valid range for an IRQ (30-1020 inclusive).
  43                  */
  44
  45                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
  46
  47                 ldr     \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
  48
  49                 ldr     \tmp, =1021
  50
  51                 bic     \irqnr, \irqstat, #0x1c00
  52
  53                 cmp     \irqnr, #29
  54                 cmpcc   \irqnr, \irqnr
  55                 cmpne   \irqnr, \tmp
  56                 cmpcs   \irqnr, \irqnr
  57                 addne   \irqnr, \irqnr, #32
  58
  59                 .endm
  60
  61                 /* We assume that irqstat (the raw value of the IRQ acknowledge
  62                  * register) is preserved from the macro above.
  63                  * If there is an IPI, we immediately signal end of interrupt on the
  64                  * controller, since this requires the original irqstat value which
  65                  * we won't easily be able to recreate later.
  66                  */
  67
  68                 .macro test_for_ipi, irqnr, irqstat, base, tmp
  69                 bic     \irqnr, \irqstat, #0x1c00
  70                 cmp     \irqnr, #16
  71                 strcc   \irqstat, [\base, #GIC_CPU_EOI]
  72                 cmpcs   \irqnr, \irqnr
  73                 .endm
  74
  75                 /* As above, this assumes that irqstat and base are preserved.. */
  76
  77                 .macro test_for_ltirq, irqnr, irqstat, base, tmp
  78                 bic     \irqnr, \irqstat, #0x1c00
  79                 mov     \tmp, #0
  80                 cmp     \irqnr, #29
  81                 moveq   \tmp, #1
  82                 streq   \irqstat, [\base, #GIC_CPU_EOI]
  83                 cmp     \tmp, #0
  84                 .endm