1 /* linux/arch/arm/mach-s5pv310/platsmp.c
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
6 * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
8 * Copyright (C) 2002 ARM Ltd.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/delay.h>
19 #include <linux/device.h>
20 #include <linux/jiffies.h>
21 #include <linux/smp.h>
24 #include <asm/cacheflush.h>
25 #include <asm/smp_scu.h>
26 #include <asm/unified.h>
28 #include <mach/hardware.h>
29 #include <mach/regs-clock.h>
31 extern void s5pv310_secondary_startup(void);
34 * control for which core is the next to come out of the secondary
38 volatile int __cpuinitdata pen_release
= -1;
40 static void __iomem
*scu_base_addr(void)
42 return (void __iomem
*)(S5P_VA_SCU
);
45 static DEFINE_SPINLOCK(boot_lock
);
47 void __cpuinit
platform_secondary_init(unsigned int cpu
)
52 * if any interrupts are already enabled for the primary
53 * core (e.g. timer irq), then they will not have been enabled
56 gic_cpu_init(0, gic_cpu_base_addr
);
59 * let the primary processor know we're out of the
60 * pen, then head off into the C entry point
66 * Synchronise with the boot thread.
68 spin_lock(&boot_lock
);
69 spin_unlock(&boot_lock
);
72 int __cpuinit
boot_secondary(unsigned int cpu
, struct task_struct
*idle
)
74 unsigned long timeout
;
77 * Set synchronisation state between this boot processor
78 * and the secondary one
80 spin_lock(&boot_lock
);
83 * The secondary processor is waiting to be released from
84 * the holding pen - release it, then wait for it to flag
85 * that it has been released by resetting pen_release.
87 * Note that "pen_release" is the hardware CPU ID, whereas
88 * "cpu" is Linux's internal ID.
91 __cpuc_flush_dcache_area((void *)&pen_release
, sizeof(pen_release
));
92 outer_clean_range(__pa(&pen_release
), __pa(&pen_release
+ 1));
95 * Send the secondary CPU a soft interrupt, thereby causing
96 * the boot monitor to read the system wide flags register,
97 * and branch to the address found there.
99 smp_cross_call(cpumask_of(cpu
), 1);
101 timeout
= jiffies
+ (1 * HZ
);
102 while (time_before(jiffies
, timeout
)) {
104 if (pen_release
== -1)
111 * now the secondary core is starting up let it run its
112 * calibrations, then wait for it to finish
114 spin_unlock(&boot_lock
);
116 return pen_release
!= -1 ? -ENOSYS
: 0;
120 * Initialise the CPU possible map early - this describes the CPUs
121 * which may be present or become present in the system.
124 void __init
smp_init_cpus(void)
126 void __iomem
*scu_base
= scu_base_addr();
127 unsigned int i
, ncores
;
129 ncores
= scu_base
? scu_get_core_count(scu_base
) : 1;
132 if (ncores
> NR_CPUS
) {
134 "S5PV310: no. of cores (%d) greater than configured "
135 "maximum of %d - clipping\n",
140 for (i
= 0; i
< ncores
; i
++)
141 set_cpu_possible(i
, true);
144 void __init
platform_smp_prepare_cpus(unsigned int max_cpus
)
149 * Initialise the present map, which describes the set of CPUs
150 * actually populated at the present time.
152 for (i
= 0; i
< max_cpus
; i
++)
153 set_cpu_present(i
, true);
155 scu_enable(scu_base_addr());
158 * Write the address of secondary startup into the
159 * system-wide flags register. The boot monitor waits
160 * until it receives a soft interrupt, and then the
161 * secondary CPU branches to this address.
163 __raw_writel(BSYM(virt_to_phys(s5pv310_secondary_startup
)), S5P_VA_SYSRAM
);