arch/arm/mach-sa1100/irq.c

   1 /*
   2  * linux/arch/arm/mach-sa1100/irq.c
   3  *
   4  * Copyright (C) 1999-2001 Nicolas Pitre
   5  *
   6  * Generic IRQ handling for the SA11x0, GPIO 11-27 IRQ demultiplexing.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12 #include <linux/init.h>
  13 #include <linux/module.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/io.h>
  16 #include <linux/irq.h>
  17 #include <linux/irqdomain.h>
  18 #include <linux/ioport.h>
  19 #include <linux/syscore_ops.h>
  20
  21 #include <mach/hardware.h>
  22 #include <mach/irqs.h>
  23 #include <asm/mach/irq.h>
  24 #include <asm/exception.h>
  25
  26 #include "generic.h"
  27
  28
  29 /*
  30  * We don't need to ACK IRQs on the SA1100 unless they're GPIOs
  31  * this is for internal IRQs i.e. from IRQ LCD to RTCAlrm.
  32  */
  33 static void sa1100_mask_irq(struct irq_data *d)
  34 {
  35         ICMR &= ~BIT(d->hwirq);
  36 }
  37
  38 static void sa1100_unmask_irq(struct irq_data *d)
  39 {
  40         ICMR |= BIT(d->hwirq);
  41 }
  42
  43 /*
  44  * Apart form GPIOs, only the RTC alarm can be a wakeup event.
  45  */
  46 static int sa1100_set_wake(struct irq_data *d, unsigned int on)
  47 {
  48         if (BIT(d->hwirq) == IC_RTCAlrm) {
  49                 if (on)
  50                         PWER |= PWER_RTC;
  51                 else
  52                         PWER &= ~PWER_RTC;
  53                 return 0;
  54         }
  55         return -EINVAL;
  56 }
  57
  58 static struct irq_chip sa1100_normal_chip = {
  59         .name           = "SC",
  60         .irq_ack        = sa1100_mask_irq,
  61         .irq_mask       = sa1100_mask_irq,
  62         .irq_unmask     = sa1100_unmask_irq,
  63         .irq_set_wake   = sa1100_set_wake,
  64 };
  65
  66 static int sa1100_normal_irqdomain_map(struct irq_domain *d,
  67                 unsigned int irq, irq_hw_number_t hwirq)
  68 {
  69         irq_set_chip_and_handler(irq, &sa1100_normal_chip,
  70                                  handle_level_irq);
  71         set_irq_flags(irq, IRQF_VALID);
  72
  73         return 0;
  74 }
  75
  76 static struct irq_domain_ops sa1100_normal_irqdomain_ops = {
  77         .map = sa1100_normal_irqdomain_map,
  78         .xlate = irq_domain_xlate_onetwocell,
  79 };
  80
  81 static struct irq_domain *sa1100_normal_irqdomain;
  82
  83 /*
  84  * SA1100 GPIO edge detection for IRQs:
  85  * IRQs are generated on Falling-Edge, Rising-Edge, or both.
  86  * Use this instead of directly setting GRER/GFER.
  87  */
  88 static int GPIO_IRQ_rising_edge;
  89 static int GPIO_IRQ_falling_edge;
  90 static int GPIO_IRQ_mask;
  91
  92 static int sa1100_gpio_type(struct irq_data *d, unsigned int type)
  93 {
  94         unsigned int mask;
  95
  96         mask = BIT(d->hwirq);
  97
  98         if (type == IRQ_TYPE_PROBE) {
  99                 if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
 100                         return 0;
 101                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 102         }
 103
 104         if (type & IRQ_TYPE_EDGE_RISING) {
 105                 GPIO_IRQ_rising_edge |= mask;
 106         } else
 107                 GPIO_IRQ_rising_edge &= ~mask;
 108         if (type & IRQ_TYPE_EDGE_FALLING) {
 109                 GPIO_IRQ_falling_edge |= mask;
 110         } else
 111                 GPIO_IRQ_falling_edge &= ~mask;
 112
 113         GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
 114         GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
 115
 116         return 0;
 117 }
 118
 119 /*
 120  * GPIO IRQs must be acknowledged.
 121  */
 122 static void sa1100_gpio_ack(struct irq_data *d)
 123 {
 124         GEDR = BIT(d->hwirq);
 125 }
 126
 127 static void sa1100_gpio_mask(struct irq_data *d)
 128 {
 129         unsigned int mask = BIT(d->hwirq);
 130
 131         GPIO_IRQ_mask &= ~mask;
 132
 133         GRER &= ~mask;
 134         GFER &= ~mask;
 135 }
 136
 137 static void sa1100_gpio_unmask(struct irq_data *d)
 138 {
 139         unsigned int mask = BIT(d->hwirq);
 140
 141         GPIO_IRQ_mask |= mask;
 142
 143         GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
 144         GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
 145 }
 146
 147 static int sa1100_gpio_wake(struct irq_data *d, unsigned int on)
 148 {
 149         if (on)
 150                 PWER |= BIT(d->hwirq);
 151         else
 152                 PWER &= ~BIT(d->hwirq);
 153         return 0;
 154 }
 155
 156 /*
 157  * This is for IRQs from 0 to 10.
 158  */
 159 static struct irq_chip sa1100_low_gpio_chip = {
 160         .name           = "GPIO-l",
 161         .irq_ack        = sa1100_gpio_ack,
 162         .irq_mask       = sa1100_gpio_mask,
 163         .irq_unmask     = sa1100_gpio_unmask,
 164         .irq_set_type   = sa1100_gpio_type,
 165         .irq_set_wake   = sa1100_gpio_wake,
 166 };
 167
 168 static int sa1100_low_gpio_irqdomain_map(struct irq_domain *d,
 169                 unsigned int irq, irq_hw_number_t hwirq)
 170 {
 171         irq_set_chip_and_handler(irq, &sa1100_low_gpio_chip,
 172                                  handle_edge_irq);
 173         set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 174
 175         return 0;
 176 }
 177
 178 static struct irq_domain_ops sa1100_low_gpio_irqdomain_ops = {
 179         .map = sa1100_low_gpio_irqdomain_map,
 180         .xlate = irq_domain_xlate_onetwocell,
 181 };
 182
 183 static struct irq_domain *sa1100_low_gpio_irqdomain;
 184
 185 /*
 186  * IRQ 0-11 (GPIO) handler.  We enter here with the
 187  * irq_controller_lock held, and IRQs disabled.  Decode the IRQ
 188  * and call the handler.
 189  */
 190 static void
 191 sa1100_gpio_handler(unsigned int irq, struct irq_desc *desc)
 192 {
 193         unsigned int mask;
 194
 195         mask = GEDR;
 196         do {
 197                 /*
 198                  * clear down all currently active IRQ sources.
 199                  * We will be processing them all.
 200                  */
 201                 GEDR = mask;
 202
 203                 irq = IRQ_GPIO0;
 204                 do {
 205                         if (mask & 1)
 206                                 generic_handle_irq(irq);
 207                         mask >>= 1;
 208                         irq++;
 209                 } while (mask);
 210
 211                 mask = GEDR;
 212         } while (mask);
 213 }
 214
 215 /*
 216  * Like GPIO0 to 10, GPIO11-27 IRQs need to be handled specially.
 217  * In addition, the IRQs are all collected up into one bit in the
 218  * interrupt controller registers.
 219  */
 220 static struct irq_chip sa1100_high_gpio_chip = {
 221         .name           = "GPIO-h",
 222         .irq_ack        = sa1100_gpio_ack,
 223         .irq_mask       = sa1100_gpio_mask,
 224         .irq_unmask     = sa1100_gpio_unmask,
 225         .irq_set_type   = sa1100_gpio_type,
 226         .irq_set_wake   = sa1100_gpio_wake,
 227 };
 228
 229 static int sa1100_high_gpio_irqdomain_map(struct irq_domain *d,
 230                 unsigned int irq, irq_hw_number_t hwirq)
 231 {
 232         irq_set_chip_and_handler(irq, &sa1100_high_gpio_chip,
 233                                  handle_edge_irq);
 234         set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 235
 236         return 0;
 237 }
 238
 239 static struct irq_domain_ops sa1100_high_gpio_irqdomain_ops = {
 240         .map = sa1100_high_gpio_irqdomain_map,
 241         .xlate = irq_domain_xlate_onetwocell,
 242 };
 243
 244 static struct irq_domain *sa1100_high_gpio_irqdomain;
 245
 246 static struct resource irq_resource =
 247         DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs");
 248
 249 static struct sa1100irq_state {
 250         unsigned int    saved;
 251         unsigned int    icmr;
 252         unsigned int    iclr;
 253         unsigned int    iccr;
 254 } sa1100irq_state;
 255
 256 static int sa1100irq_suspend(void)
 257 {
 258         struct sa1100irq_state *st = &sa1100irq_state;
 259
 260         st->saved = 1;
 261         st->icmr = ICMR;
 262         st->iclr = ICLR;
 263         st->iccr = ICCR;
 264
 265         /*
 266          * Disable all GPIO-based interrupts.
 267          */
 268         ICMR &= ~(IC_GPIO11_27|IC_GPIO10|IC_GPIO9|IC_GPIO8|IC_GPIO7|
 269                   IC_GPIO6|IC_GPIO5|IC_GPIO4|IC_GPIO3|IC_GPIO2|
 270                   IC_GPIO1|IC_GPIO0);
 271
 272         /*
 273          * Set the appropriate edges for wakeup.
 274          */
 275         GRER = PWER & GPIO_IRQ_rising_edge;
 276         GFER = PWER & GPIO_IRQ_falling_edge;
 277
 278         /*
 279          * Clear any pending GPIO interrupts.
 280          */
 281         GEDR = GEDR;
 282
 283         return 0;
 284 }
 285
 286 static void sa1100irq_resume(void)
 287 {
 288         struct sa1100irq_state *st = &sa1100irq_state;
 289
 290         if (st->saved) {
 291                 ICCR = st->iccr;
 292                 ICLR = st->iclr;
 293
 294                 GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
 295                 GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
 296
 297                 ICMR = st->icmr;
 298         }
 299 }
 300
 301 static struct syscore_ops sa1100irq_syscore_ops = {
 302         .suspend        = sa1100irq_suspend,
 303         .resume         = sa1100irq_resume,
 304 };
 305
 306 static int __init sa1100irq_init_devicefs(void)
 307 {
 308         register_syscore_ops(&sa1100irq_syscore_ops);
 309         return 0;
 310 }
 311
 312 device_initcall(sa1100irq_init_devicefs);
 313
 314 static asmlinkage void __exception_irq_entry
 315 sa1100_handle_irq(struct pt_regs *regs)
 316 {
 317         uint32_t icip, icmr, mask;
 318
 319         do {
 320                 icip = (ICIP);
 321                 icmr = (ICMR);
 322                 mask = icip & icmr;
 323
 324                 if (mask == 0)
 325                         break;
 326
 327                 handle_IRQ(ffs(mask) - 1 + IRQ_GPIO0_SC, regs);
 328         } while (1);
 329 }
 330
 331 void __init sa1100_init_irq(void)
 332 {
 333         request_resource(&iomem_resource, &irq_resource);
 334
 335         /* disable all IRQs */
 336         ICMR = 0;
 337
 338         /* all IRQs are IRQ, not FIQ */
 339         ICLR = 0;
 340
 341         /* clear all GPIO edge detects */
 342         GFER = 0;
 343         GRER = 0;
 344         GEDR = -1;
 345
 346         /*
 347          * Whatever the doc says, this has to be set for the wait-on-irq
 348          * instruction to work... on a SA1100 rev 9 at least.
 349          */
 350         ICCR = 1;
 351
 352         sa1100_normal_irqdomain = irq_domain_add_legacy(NULL,
 353                         32, IRQ_GPIO0_SC, 0,
 354                         &sa1100_normal_irqdomain_ops, NULL);
 355
 356         sa1100_low_gpio_irqdomain = irq_domain_add_legacy(NULL,
 357                         11, IRQ_GPIO0, 0,
 358                         &sa1100_low_gpio_irqdomain_ops, NULL);
 359
 360         sa1100_high_gpio_irqdomain = irq_domain_add_legacy(NULL,
 361                         17, IRQ_GPIO11, 11,
 362                         &sa1100_high_gpio_irqdomain_ops, NULL);
 363
 364         /*
 365          * Install handlers for GPIO 0-10 edge detect interrupts
 366          */
 367         irq_set_chained_handler(IRQ_GPIO0_SC, sa1100_gpio_handler);
 368         irq_set_chained_handler(IRQ_GPIO1_SC, sa1100_gpio_handler);
 369         irq_set_chained_handler(IRQ_GPIO2_SC, sa1100_gpio_handler);
 370         irq_set_chained_handler(IRQ_GPIO3_SC, sa1100_gpio_handler);
 371         irq_set_chained_handler(IRQ_GPIO4_SC, sa1100_gpio_handler);
 372         irq_set_chained_handler(IRQ_GPIO5_SC, sa1100_gpio_handler);
 373         irq_set_chained_handler(IRQ_GPIO6_SC, sa1100_gpio_handler);
 374         irq_set_chained_handler(IRQ_GPIO7_SC, sa1100_gpio_handler);
 375         irq_set_chained_handler(IRQ_GPIO8_SC, sa1100_gpio_handler);
 376         irq_set_chained_handler(IRQ_GPIO9_SC, sa1100_gpio_handler);
 377         irq_set_chained_handler(IRQ_GPIO10_SC, sa1100_gpio_handler);
 378         /*
 379          * Install handler for GPIO 11-27 edge detect interrupts
 380          */
 381         irq_set_chained_handler(IRQ_GPIO11_27, sa1100_gpio_handler);
 382
 383         set_handle_irq(sa1100_handle_irq);
 384
 385         sa1100_init_gpio();
 386 }