arch/arm/mach-sa1100/irq.c

   1 /*
   2  * linux/arch/arm/mach-sa1100/irq.c
   3  *
   4  * Copyright (C) 1999-2001 Nicolas Pitre
   5  *
   6  * Generic IRQ handling for the SA11x0, GPIO 11-27 IRQ demultiplexing.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12 #include <linux/init.h>
  13 #include <linux/module.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/io.h>
  16 #include <linux/irq.h>
  17 #include <linux/ioport.h>
  18 #include <linux/syscore_ops.h>
  19
  20 #include <mach/hardware.h>
  21 #include <mach/irqs.h>
  22 #include <asm/mach/irq.h>
  23 #include <asm/exception.h>
  24
  25 #include "generic.h"
  26
  27
  28 /*
  29  * SA1100 GPIO edge detection for IRQs:
  30  * IRQs are generated on Falling-Edge, Rising-Edge, or both.
  31  * Use this instead of directly setting GRER/GFER.
  32  */
  33 static int GPIO_IRQ_rising_edge;
  34 static int GPIO_IRQ_falling_edge;
  35 static int GPIO_IRQ_mask = (1 << 11) - 1;
  36
  37 /*
  38  * To get the GPIO number from an IRQ number
  39  */
  40 #define GPIO_11_27_IRQ(i)       ((i) + 11 - IRQ_GPIO11)
  41 #define GPIO11_27_MASK(irq)     (1 << GPIO_11_27_IRQ(irq))
  42
  43 static int sa1100_gpio_type(struct irq_data *d, unsigned int type)
  44 {
  45         unsigned int mask;
  46
  47         if (d->irq <= IRQ_GPIO10)
  48                 mask = 1 << d->irq;
  49         else
  50                 mask = GPIO11_27_MASK(d->irq);
  51
  52         if (type == IRQ_TYPE_PROBE) {
  53                 if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
  54                         return 0;
  55                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
  56         }
  57
  58         if (type & IRQ_TYPE_EDGE_RISING) {
  59                 GPIO_IRQ_rising_edge |= mask;
  60         } else
  61                 GPIO_IRQ_rising_edge &= ~mask;
  62         if (type & IRQ_TYPE_EDGE_FALLING) {
  63                 GPIO_IRQ_falling_edge |= mask;
  64         } else
  65                 GPIO_IRQ_falling_edge &= ~mask;
  66
  67         GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
  68         GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
  69
  70         return 0;
  71 }
  72
  73 /*
  74  * GPIO IRQs must be acknowledged.  This is for IRQs from GPIO0 to 10.
  75  */
  76 static void sa1100_low_gpio_ack(struct irq_data *d)
  77 {
  78         GEDR = (1 << d->irq);
  79 }
  80
  81 static void sa1100_low_gpio_mask(struct irq_data *d)
  82 {
  83         ICMR &= ~(1 << d->irq);
  84 }
  85
  86 static void sa1100_low_gpio_unmask(struct irq_data *d)
  87 {
  88         ICMR |= 1 << d->irq;
  89 }
  90
  91 static int sa1100_low_gpio_wake(struct irq_data *d, unsigned int on)
  92 {
  93         if (on)
  94                 PWER |= 1 << d->irq;
  95         else
  96                 PWER &= ~(1 << d->irq);
  97         return 0;
  98 }
  99
 100 static struct irq_chip sa1100_low_gpio_chip = {
 101         .name           = "GPIO-l",
 102         .irq_ack        = sa1100_low_gpio_ack,
 103         .irq_mask       = sa1100_low_gpio_mask,
 104         .irq_unmask     = sa1100_low_gpio_unmask,
 105         .irq_set_type   = sa1100_gpio_type,
 106         .irq_set_wake   = sa1100_low_gpio_wake,
 107 };
 108
 109 /*
 110  * IRQ11 (GPIO11 through 27) handler.  We enter here with the
 111  * irq_controller_lock held, and IRQs disabled.  Decode the IRQ
 112  * and call the handler.
 113  */
 114 static void
 115 sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc)
 116 {
 117         unsigned int mask;
 118
 119         mask = GEDR & 0xfffff800;
 120         do {
 121                 /*
 122                  * clear down all currently active IRQ sources.
 123                  * We will be processing them all.
 124                  */
 125                 GEDR = mask;
 126
 127                 irq = IRQ_GPIO11;
 128                 mask >>= 11;
 129                 do {
 130                         if (mask & 1)
 131                                 generic_handle_irq(irq);
 132                         mask >>= 1;
 133                         irq++;
 134                 } while (mask);
 135
 136                 mask = GEDR & 0xfffff800;
 137         } while (mask);
 138 }
 139
 140 /*
 141  * Like GPIO0 to 10, GPIO11-27 IRQs need to be handled specially.
 142  * In addition, the IRQs are all collected up into one bit in the
 143  * interrupt controller registers.
 144  */
 145 static void sa1100_high_gpio_ack(struct irq_data *d)
 146 {
 147         unsigned int mask = GPIO11_27_MASK(d->irq);
 148
 149         GEDR = mask;
 150 }
 151
 152 static void sa1100_high_gpio_mask(struct irq_data *d)
 153 {
 154         unsigned int mask = GPIO11_27_MASK(d->irq);
 155
 156         GPIO_IRQ_mask &= ~mask;
 157
 158         GRER &= ~mask;
 159         GFER &= ~mask;
 160 }
 161
 162 static void sa1100_high_gpio_unmask(struct irq_data *d)
 163 {
 164         unsigned int mask = GPIO11_27_MASK(d->irq);
 165
 166         GPIO_IRQ_mask |= mask;
 167
 168         GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
 169         GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
 170 }
 171
 172 static int sa1100_high_gpio_wake(struct irq_data *d, unsigned int on)
 173 {
 174         if (on)
 175                 PWER |= GPIO11_27_MASK(d->irq);
 176         else
 177                 PWER &= ~GPIO11_27_MASK(d->irq);
 178         return 0;
 179 }
 180
 181 static struct irq_chip sa1100_high_gpio_chip = {
 182         .name           = "GPIO-h",
 183         .irq_ack        = sa1100_high_gpio_ack,
 184         .irq_mask       = sa1100_high_gpio_mask,
 185         .irq_unmask     = sa1100_high_gpio_unmask,
 186         .irq_set_type   = sa1100_gpio_type,
 187         .irq_set_wake   = sa1100_high_gpio_wake,
 188 };
 189
 190 /*
 191  * We don't need to ACK IRQs on the SA1100 unless they're GPIOs
 192  * this is for internal IRQs i.e. from IRQ LCD to RTCAlrm.
 193  */
 194 static void sa1100_mask_irq(struct irq_data *d)
 195 {
 196         ICMR &= ~(1 << d->irq);
 197 }
 198
 199 static void sa1100_unmask_irq(struct irq_data *d)
 200 {
 201         ICMR |= (1 << d->irq);
 202 }
 203
 204 /*
 205  * Apart form GPIOs, only the RTC alarm can be a wakeup event.
 206  */
 207 static int sa1100_set_wake(struct irq_data *d, unsigned int on)
 208 {
 209         if (d->irq == IRQ_RTCAlrm) {
 210                 if (on)
 211                         PWER |= PWER_RTC;
 212                 else
 213                         PWER &= ~PWER_RTC;
 214                 return 0;
 215         }
 216         return -EINVAL;
 217 }
 218
 219 static struct irq_chip sa1100_normal_chip = {
 220         .name           = "SC",
 221         .irq_ack        = sa1100_mask_irq,
 222         .irq_mask       = sa1100_mask_irq,
 223         .irq_unmask     = sa1100_unmask_irq,
 224         .irq_set_wake   = sa1100_set_wake,
 225 };
 226
 227 static struct resource irq_resource =
 228         DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs");
 229
 230 static struct sa1100irq_state {
 231         unsigned int    saved;
 232         unsigned int    icmr;
 233         unsigned int    iclr;
 234         unsigned int    iccr;
 235 } sa1100irq_state;
 236
 237 static int sa1100irq_suspend(void)
 238 {
 239         struct sa1100irq_state *st = &sa1100irq_state;
 240
 241         st->saved = 1;
 242         st->icmr = ICMR;
 243         st->iclr = ICLR;
 244         st->iccr = ICCR;
 245
 246         /*
 247          * Disable all GPIO-based interrupts.
 248          */
 249         ICMR &= ~(IC_GPIO11_27|IC_GPIO10|IC_GPIO9|IC_GPIO8|IC_GPIO7|
 250                   IC_GPIO6|IC_GPIO5|IC_GPIO4|IC_GPIO3|IC_GPIO2|
 251                   IC_GPIO1|IC_GPIO0);
 252
 253         /*
 254          * Set the appropriate edges for wakeup.
 255          */
 256         GRER = PWER & GPIO_IRQ_rising_edge;
 257         GFER = PWER & GPIO_IRQ_falling_edge;
 258
 259         /*
 260          * Clear any pending GPIO interrupts.
 261          */
 262         GEDR = GEDR;
 263
 264         return 0;
 265 }
 266
 267 static void sa1100irq_resume(void)
 268 {
 269         struct sa1100irq_state *st = &sa1100irq_state;
 270
 271         if (st->saved) {
 272                 ICCR = st->iccr;
 273                 ICLR = st->iclr;
 274
 275                 GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
 276                 GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
 277
 278                 ICMR = st->icmr;
 279         }
 280 }
 281
 282 static struct syscore_ops sa1100irq_syscore_ops = {
 283         .suspend        = sa1100irq_suspend,
 284         .resume         = sa1100irq_resume,
 285 };
 286
 287 static int __init sa1100irq_init_devicefs(void)
 288 {
 289         register_syscore_ops(&sa1100irq_syscore_ops);
 290         return 0;
 291 }
 292
 293 device_initcall(sa1100irq_init_devicefs);
 294
 295 static asmlinkage void __exception_irq_entry
 296 sa1100_handle_irq(struct pt_regs *regs)
 297 {
 298         uint32_t icip, icmr, mask;
 299
 300         do {
 301                 icip = (ICIP);
 302                 icmr = (ICMR);
 303                 mask = icip & icmr;
 304
 305                 if (mask == 0)
 306                         break;
 307
 308                 handle_IRQ(ffs(mask) - 1 + IRQ_GPIO0, regs);
 309         } while (1);
 310 }
 311
 312 void __init sa1100_init_irq(void)
 313 {
 314         unsigned int irq;
 315
 316         request_resource(&iomem_resource, &irq_resource);
 317
 318         /* disable all IRQs */
 319         ICMR = 0;
 320
 321         /* all IRQs are IRQ, not FIQ */
 322         ICLR = 0;
 323
 324         /* clear all GPIO edge detects */
 325         GFER = 0;
 326         GRER = 0;
 327         GEDR = -1;
 328
 329         /*
 330          * Whatever the doc says, this has to be set for the wait-on-irq
 331          * instruction to work... on a SA1100 rev 9 at least.
 332          */
 333         ICCR = 1;
 334
 335         for (irq = IRQ_GPIO0; irq <= IRQ_GPIO10; irq++) {
 336                 irq_set_chip_and_handler(irq, &sa1100_low_gpio_chip,
 337                                          handle_edge_irq);
 338                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 339         }
 340
 341         for (irq = IRQ_LCD; irq <= IRQ_RTCAlrm; irq++) {
 342                 irq_set_chip_and_handler(irq, &sa1100_normal_chip,
 343                                          handle_level_irq);
 344                 set_irq_flags(irq, IRQF_VALID);
 345         }
 346
 347         for (irq = IRQ_GPIO11; irq <= IRQ_GPIO27; irq++) {
 348                 irq_set_chip_and_handler(irq, &sa1100_high_gpio_chip,
 349                                          handle_edge_irq);
 350                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 351         }
 352
 353         /*
 354          * Install handler for GPIO 11-27 edge detect interrupts
 355          */
 356         irq_set_chip(IRQ_GPIO11_27, &sa1100_normal_chip);
 357         irq_set_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler);
 358
 359         set_handle_irq(sa1100_handle_irq);
 360
 361         sa1100_init_gpio();
 362 }