arch/arm/mach-shmobile/clock-r8a7740.c

   1 /*
   2  * R8A7740 processor support
   3  *
   4  * Copyright (C) 2011  Renesas Solutions Corp.
   5  * Copyright (C) 2011  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include <linux/init.h>
  21 #include <linux/kernel.h>
  22 #include <linux/io.h>
  23 #include <linux/sh_clk.h>
  24 #include <linux/clkdev.h>
  25 #include <mach/common.h>
  26 #include <mach/r8a7740.h>
  27
  28 /*
  29  *        |  MDx  |  XTAL1/EXTAL1   |  System   | EXTALR |
  30  *  Clock |-------+-----------------+  clock    | 32.768 |   RCLK
  31  *  Mode  | 2/1/0 | src         MHz |  source   |  KHz   |  source
  32  * -------+-------+-----------------+-----------+--------+----------
  33  *    0   | 0 0 0 | External  20~50 | XTAL1     |    O   |  EXTALR
  34  *    1   | 0 0 1 | Crystal   20~30 | XTAL1     |    O   |  EXTALR
  35  *    2   | 0 1 0 | External  40~50 | XTAL1 / 2 |    O   |  EXTALR
  36  *    3   | 0 1 1 | Crystal   40~50 | XTAL1 / 2 |    O   |  EXTALR
  37  *    4   | 1 0 0 | External  20~50 | XTAL1     |    x   |  XTAL1 / 1024
  38  *    5   | 1 0 1 | Crystal   20~30 | XTAL1     |    x   |  XTAL1 / 1024
  39  *    6   | 1 1 0 | External  40~50 | XTAL1 / 2 |    x   |  XTAL1 / 2048
  40  *    7   | 1 1 1 | Crystal   40~50 | XTAL1 / 2 |    x   |  XTAL1 / 2048
  41  */
  42
  43 /* CPG registers */
  44 #define FRQCRA          0xe6150000
  45 #define FRQCRB          0xe6150004
  46 #define VCLKCR1         0xE6150008
  47 #define VCLKCR2         0xE615000c
  48 #define FRQCRC          0xe61500e0
  49 #define PLLC01CR        0xe6150028
  50
  51 #define SUBCKCR         0xe6150080
  52 #define USBCKCR         0xe615008c
  53
  54 #define MSTPSR0         0xe6150030
  55 #define MSTPSR1         0xe6150038
  56 #define MSTPSR2         0xe6150040
  57 #define MSTPSR3         0xe6150048
  58 #define MSTPSR4         0xe615004c
  59 #define HDMICKCR        0xe6150094
  60 #define SMSTPCR0        0xe6150130
  61 #define SMSTPCR1        0xe6150134
  62 #define SMSTPCR2        0xe6150138
  63 #define SMSTPCR3        0xe615013c
  64 #define SMSTPCR4        0xe6150140
  65
  66 /* Fixed 32 KHz root clock from EXTALR pin */
  67 static struct clk extalr_clk = {
  68         .rate   = 32768,
  69 };
  70
  71 /*
  72  * 25MHz default rate for the EXTAL1 root input clock.
  73  * If needed, reset this with clk_set_rate() from the platform code.
  74  */
  75 static struct clk extal1_clk = {
  76         .rate   = 25000000,
  77 };
  78
  79 /*
  80  * 48MHz default rate for the EXTAL2 root input clock.
  81  * If needed, reset this with clk_set_rate() from the platform code.
  82  */
  83 static struct clk extal2_clk = {
  84         .rate   = 48000000,
  85 };
  86
  87 /*
  88  * 27MHz default rate for the DV_CLKI root input clock.
  89  * If needed, reset this with clk_set_rate() from the platform code.
  90  */
  91 static struct clk dv_clk = {
  92         .rate   = 27000000,
  93 };
  94
  95 static unsigned long div_recalc(struct clk *clk)
  96 {
  97         return clk->parent->rate / (int)(clk->priv);
  98 }
  99
 100 static struct sh_clk_ops div_clk_ops = {
 101         .recalc = div_recalc,
 102 };
 103
 104 /* extal1 / 2 */
 105 static struct clk extal1_div2_clk = {
 106         .ops    = &div_clk_ops,
 107         .priv   = (void *)2,
 108         .parent = &extal1_clk,
 109 };
 110
 111 /* extal1 / 1024 */
 112 static struct clk extal1_div1024_clk = {
 113         .ops    = &div_clk_ops,
 114         .priv   = (void *)1024,
 115         .parent = &extal1_clk,
 116 };
 117
 118 /* extal1 / 2 / 1024 */
 119 static struct clk extal1_div2048_clk = {
 120         .ops    = &div_clk_ops,
 121         .priv   = (void *)1024,
 122         .parent = &extal1_div2_clk,
 123 };
 124
 125 /* extal2 / 2 */
 126 static struct clk extal2_div2_clk = {
 127         .ops    = &div_clk_ops,
 128         .priv   = (void *)2,
 129         .parent = &extal2_clk,
 130 };
 131
 132 static struct sh_clk_ops followparent_clk_ops = {
 133         .recalc = followparent_recalc,
 134 };
 135
 136 /* Main clock */
 137 static struct clk system_clk = {
 138         .ops    = &followparent_clk_ops,
 139 };
 140
 141 static struct clk system_div2_clk = {
 142         .ops    = &div_clk_ops,
 143         .priv   = (void *)2,
 144         .parent = &system_clk,
 145 };
 146
 147 /* r_clk */
 148 static struct clk r_clk = {
 149         .ops    = &followparent_clk_ops,
 150 };
 151
 152 /* PLLC0/PLLC1 */
 153 static unsigned long pllc01_recalc(struct clk *clk)
 154 {
 155         unsigned long mult = 1;
 156
 157         if (__raw_readl(PLLC01CR) & (1 << 14))
 158                 mult = ((__raw_readl(clk->enable_reg) >> 24) & 0x7f) + 1;
 159
 160         return clk->parent->rate * mult;
 161 }
 162
 163 static struct sh_clk_ops pllc01_clk_ops = {
 164         .recalc         = pllc01_recalc,
 165 };
 166
 167 static struct clk pllc0_clk = {
 168         .ops            = &pllc01_clk_ops,
 169         .flags          = CLK_ENABLE_ON_INIT,
 170         .parent         = &system_clk,
 171         .enable_reg     = (void __iomem *)FRQCRC,
 172 };
 173
 174 static struct clk pllc1_clk = {
 175         .ops            = &pllc01_clk_ops,
 176         .flags          = CLK_ENABLE_ON_INIT,
 177         .parent         = &system_div2_clk,
 178         .enable_reg     = (void __iomem *)FRQCRA,
 179 };
 180
 181 /* PLLC1 / 2 */
 182 static struct clk pllc1_div2_clk = {
 183         .ops            = &div_clk_ops,
 184         .priv           = (void *)2,
 185         .parent         = &pllc1_clk,
 186 };
 187
 188 /* USB clock */
 189 static struct clk *usb24s_parents[] = {
 190         [0] = &system_clk,
 191         [1] = &extal2_clk
 192 };
 193
 194 static int usb24s_enable(struct clk *clk)
 195 {
 196         __raw_writel(__raw_readl(USBCKCR) & ~(1 << 8), USBCKCR);
 197
 198         return 0;
 199 }
 200
 201 static void usb24s_disable(struct clk *clk)
 202 {
 203         __raw_writel(__raw_readl(USBCKCR) | (1 << 8), USBCKCR);
 204 }
 205
 206 static int usb24s_set_parent(struct clk *clk, struct clk *parent)
 207 {
 208         int i, ret;
 209         u32 val;
 210
 211         if (!clk->parent_table || !clk->parent_num)
 212                 return -EINVAL;
 213
 214         /* Search the parent */
 215         for (i = 0; i < clk->parent_num; i++)
 216                 if (clk->parent_table[i] == parent)
 217                         break;
 218
 219         if (i == clk->parent_num)
 220                 return -ENODEV;
 221
 222         ret = clk_reparent(clk, parent);
 223         if (ret < 0)
 224                 return ret;
 225
 226         val = __raw_readl(USBCKCR);
 227         val &= ~(1 << 7);
 228         val |= i << 7;
 229         __raw_writel(val, USBCKCR);
 230
 231         return 0;
 232 }
 233
 234 static struct sh_clk_ops usb24s_clk_ops = {
 235         .recalc         = followparent_recalc,
 236         .enable         = usb24s_enable,
 237         .disable        = usb24s_disable,
 238         .set_parent     = usb24s_set_parent,
 239 };
 240
 241 static struct clk usb24s_clk = {
 242         .ops            = &usb24s_clk_ops,
 243         .parent_table   = usb24s_parents,
 244         .parent_num     = ARRAY_SIZE(usb24s_parents),
 245         .parent         = &system_clk,
 246 };
 247
 248 static unsigned long usb24_recalc(struct clk *clk)
 249 {
 250         return clk->parent->rate /
 251                 ((__raw_readl(USBCKCR) & (1 << 6)) ? 1 : 2);
 252 };
 253
 254 static int usb24_set_rate(struct clk *clk, unsigned long rate)
 255 {
 256         u32 val;
 257
 258         /* closer to which ? parent->rate or parent->rate/2 */
 259         val = __raw_readl(USBCKCR);
 260         val &= ~(1 << 6);
 261         val |= (rate > (clk->parent->rate / 4) * 3) << 6;
 262         __raw_writel(val, USBCKCR);
 263
 264         return 0;
 265 }
 266
 267 static struct sh_clk_ops usb24_clk_ops = {
 268         .recalc         = usb24_recalc,
 269         .set_rate       = usb24_set_rate,
 270 };
 271
 272 static struct clk usb24_clk = {
 273         .ops            = &usb24_clk_ops,
 274         .parent         = &usb24s_clk,
 275 };
 276
 277 struct clk *main_clks[] = {
 278         &extalr_clk,
 279         &extal1_clk,
 280         &extal2_clk,
 281         &extal1_div2_clk,
 282         &extal1_div1024_clk,
 283         &extal1_div2048_clk,
 284         &extal2_div2_clk,
 285         &dv_clk,
 286         &system_clk,
 287         &system_div2_clk,
 288         &r_clk,
 289         &pllc0_clk,
 290         &pllc1_clk,
 291         &pllc1_div2_clk,
 292         &usb24s_clk,
 293         &usb24_clk,
 294 };
 295
 296 static void div4_kick(struct clk *clk)
 297 {
 298         unsigned long value;
 299
 300         /* set KICK bit in FRQCRB to update hardware setting */
 301         value = __raw_readl(FRQCRB);
 302         value |= (1 << 31);
 303         __raw_writel(value, FRQCRB);
 304 }
 305
 306 static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
 307                           24, 32, 36, 48, 0, 72, 96, 0 };
 308
 309 static struct clk_div_mult_table div4_div_mult_table = {
 310         .divisors = divisors,
 311         .nr_divisors = ARRAY_SIZE(divisors),
 312 };
 313
 314 static struct clk_div4_table div4_table = {
 315         .div_mult_table = &div4_div_mult_table,
 316         .kick = div4_kick,
 317 };
 318
 319 /* DIV6 reparent */
 320 enum {
 321         DIV6_HDMI,
 322         DIV6_VCLK1, DIV6_VCLK2,
 323         DIV6_REPARENT_NR,
 324 };
 325
 326 static struct clk *hdmi_parent[] = {
 327         [0] = &pllc1_div2_clk,
 328         [1] = &system_clk,
 329         [2] = &dv_clk
 330 };
 331
 332 static struct clk *vclk_parents[8] = {
 333         [0] = &pllc1_div2_clk,
 334         [2] = &dv_clk,
 335         [3] = &usb24s_clk,
 336         [4] = &extal1_div2_clk,
 337         [5] = &extalr_clk,
 338 };
 339
 340 static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
 341         [DIV6_HDMI] = SH_CLK_DIV6_EXT(HDMICKCR, 0,
 342                                       hdmi_parent, ARRAY_SIZE(hdmi_parent), 6, 2),
 343         [DIV6_VCLK1] = SH_CLK_DIV6_EXT(VCLKCR1, 0,
 344                                        vclk_parents, ARRAY_SIZE(vclk_parents), 12, 3),
 345         [DIV6_VCLK2] = SH_CLK_DIV6_EXT(VCLKCR2, 0,
 346                                        vclk_parents, ARRAY_SIZE(vclk_parents), 12, 3),
 347 };
 348
 349 /* HDMI1/2 clock */
 350 static unsigned long hdmi12_recalc(struct clk *clk)
 351 {
 352         u32 val = __raw_readl(HDMICKCR);
 353         int shift = (int)clk->priv;
 354
 355         val >>= shift;
 356         val &= 0x3;
 357
 358         return clk->parent->rate / (1 << val);
 359 };
 360
 361 static int hdmi12_set_rate(struct clk *clk, unsigned long rate)
 362 {
 363         u32 val, mask;
 364         int i, shift;
 365
 366         for (i = 0; i < 3; i++)
 367                 if (rate == clk->parent->rate / (1 << i))
 368                         goto find;
 369         return -ENODEV;
 370
 371 find:
 372         shift = (int)clk->priv;
 373
 374         val = __raw_readl(HDMICKCR);
 375         mask = ~(0x3 << shift);
 376         val = (val & mask) | i << shift;
 377         __raw_writel(val, HDMICKCR);
 378
 379         return 0;
 380 };
 381
 382 static struct sh_clk_ops hdmi12_clk_ops = {
 383         .recalc         = hdmi12_recalc,
 384         .set_rate       = hdmi12_set_rate,
 385 };
 386
 387 static struct clk hdmi1_clk = {
 388         .ops            = &hdmi12_clk_ops,
 389         .priv           = (void *)9,
 390         .parent         = &div6_reparent_clks[DIV6_HDMI],  /* late install */
 391 };
 392
 393 static struct clk hdmi2_clk = {
 394         .ops            = &hdmi12_clk_ops,
 395         .priv           = (void *)11,
 396         .parent         = &div6_reparent_clks[DIV6_HDMI], /* late install */
 397 };
 398
 399 static struct clk *late_main_clks[] = {
 400         &hdmi1_clk,
 401         &hdmi2_clk,
 402 };
 403
 404 /* MSTP */
 405 enum {
 406         DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP,
 407         DIV4_HPP, DIV4_USBP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP,
 408         DIV4_NR
 409 };
 410
 411 struct clk div4_clks[DIV4_NR] = {
 412         [DIV4_I]        = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
 413         [DIV4_ZG]       = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
 414         [DIV4_B]        = SH_CLK_DIV4(&pllc1_clk, FRQCRA,  8, 0x6fff, CLK_ENABLE_ON_INIT),
 415         [DIV4_M1]       = SH_CLK_DIV4(&pllc1_clk, FRQCRA,  4, 0x6fff, CLK_ENABLE_ON_INIT),
 416         [DIV4_HP]       = SH_CLK_DIV4(&pllc1_clk, FRQCRB,  4, 0x6fff, 0),
 417         [DIV4_HPP]      = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 20, 0x6fff, 0),
 418         [DIV4_USBP]     = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 16, 0x6fff, 0),
 419         [DIV4_S]        = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 12, 0x6fff, 0),
 420         [DIV4_ZB]       = SH_CLK_DIV4(&pllc1_clk, FRQCRC,  8, 0x6fff, 0),
 421         [DIV4_M3]       = SH_CLK_DIV4(&pllc1_clk, FRQCRC,  4, 0x6fff, 0),
 422         [DIV4_CP]       = SH_CLK_DIV4(&pllc1_clk, FRQCRC,  0, 0x6fff, 0),
 423 };
 424
 425 enum {
 426         DIV6_SUB,
 427         DIV6_NR
 428 };
 429
 430 static struct clk div6_clks[DIV6_NR] = {
 431         [DIV6_SUB]      = SH_CLK_DIV6(&pllc1_div2_clk, SUBCKCR, 0),
 432 };
 433
 434 enum {
 435         MSTP128, MSTP127, MSTP125,
 436         MSTP116, MSTP111, MSTP100, MSTP117,
 437
 438         MSTP230,
 439         MSTP222,
 440         MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
 441
 442         MSTP329, MSTP328, MSTP323, MSTP320,
 443         MSTP314, MSTP313, MSTP312,
 444         MSTP309,
 445
 446         MSTP416, MSTP415, MSTP407, MSTP406,
 447
 448         MSTP_NR
 449 };
 450
 451 static struct clk mstp_clks[MSTP_NR] = {
 452         [MSTP128] = SH_CLK_MSTP32(&div4_clks[DIV4_S],   SMSTPCR1, 28, 0), /* CEU21 */
 453         [MSTP127] = SH_CLK_MSTP32(&div4_clks[DIV4_S],   SMSTPCR1, 27, 0), /* CEU20 */
 454         [MSTP125] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
 455         [MSTP117] = SH_CLK_MSTP32(&div4_clks[DIV4_B],   SMSTPCR1, 17, 0), /* LCDC1 */
 456         [MSTP116] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
 457         [MSTP111] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 11, 0), /* TMU1 */
 458         [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_B],   SMSTPCR1,  0, 0), /* LCDC0 */
 459
 460         [MSTP230] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 30, 0), /* SCIFA6 */
 461         [MSTP222] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 22, 0), /* SCIFA7 */
 462         [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2,  7, 0), /* SCIFA5 */
 463         [MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2,  6, 0), /* SCIFB */
 464         [MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2,  4, 0), /* SCIFA0 */
 465         [MSTP203] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2,  3, 0), /* SCIFA1 */
 466         [MSTP202] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2,  2, 0), /* SCIFA2 */
 467         [MSTP201] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2,  1, 0), /* SCIFA3 */
 468         [MSTP200] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2,  0, 0), /* SCIFA4 */
 469
 470         [MSTP329] = SH_CLK_MSTP32(&r_clk,               SMSTPCR3, 29, 0), /* CMT10 */
 471         [MSTP328] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 28, 0), /* FSI */
 472         [MSTP323] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
 473         [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 20, 0), /* USBF */
 474         [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 14, 0), /* SDHI0 */
 475         [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 13, 0), /* SDHI1 */
 476         [MSTP312] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 12, 0), /* MMC */
 477         [MSTP309] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3,  9, 0), /* GEther */
 478
 479         [MSTP416] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR4, 16, 0), /* USBHOST */
 480         [MSTP415] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR4, 15, 0), /* SDHI2 */
 481         [MSTP407] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR4,  7, 0), /* USB-Func */
 482         [MSTP406] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR4,  6, 0), /* USB Phy */
 483 };
 484
 485 static struct clk_lookup lookups[] = {
 486         /* main clocks */
 487         CLKDEV_CON_ID("extalr",                 &extalr_clk),
 488         CLKDEV_CON_ID("extal1",                 &extal1_clk),
 489         CLKDEV_CON_ID("extal2",                 &extal2_clk),
 490         CLKDEV_CON_ID("extal1_div2",            &extal1_div2_clk),
 491         CLKDEV_CON_ID("extal1_div1024",         &extal1_div1024_clk),
 492         CLKDEV_CON_ID("extal1_div2048",         &extal1_div2048_clk),
 493         CLKDEV_CON_ID("extal2_div2",            &extal2_div2_clk),
 494         CLKDEV_CON_ID("dv_clk",                 &dv_clk),
 495         CLKDEV_CON_ID("system_clk",             &system_clk),
 496         CLKDEV_CON_ID("system_div2_clk",        &system_div2_clk),
 497         CLKDEV_CON_ID("r_clk",                  &r_clk),
 498         CLKDEV_CON_ID("pllc0_clk",              &pllc0_clk),
 499         CLKDEV_CON_ID("pllc1_clk",              &pllc1_clk),
 500         CLKDEV_CON_ID("pllc1_div2_clk",         &pllc1_div2_clk),
 501         CLKDEV_CON_ID("usb24s",                 &usb24s_clk),
 502         CLKDEV_CON_ID("hdmi1",                  &hdmi1_clk),
 503         CLKDEV_CON_ID("hdmi2",                  &hdmi2_clk),
 504         CLKDEV_CON_ID("video1",                 &div6_reparent_clks[DIV6_VCLK1]),
 505         CLKDEV_CON_ID("video2",                 &div6_reparent_clks[DIV6_VCLK2]),
 506
 507         /* DIV4 clocks */
 508         CLKDEV_CON_ID("i_clk",                  &div4_clks[DIV4_I]),
 509         CLKDEV_CON_ID("zg_clk",                 &div4_clks[DIV4_ZG]),
 510         CLKDEV_CON_ID("b_clk",                  &div4_clks[DIV4_B]),
 511         CLKDEV_CON_ID("m1_clk",                 &div4_clks[DIV4_M1]),
 512         CLKDEV_CON_ID("hp_clk",                 &div4_clks[DIV4_HP]),
 513         CLKDEV_CON_ID("hpp_clk",                &div4_clks[DIV4_HPP]),
 514         CLKDEV_CON_ID("s_clk",                  &div4_clks[DIV4_S]),
 515         CLKDEV_CON_ID("zb_clk",                 &div4_clks[DIV4_ZB]),
 516         CLKDEV_CON_ID("m3_clk",                 &div4_clks[DIV4_M3]),
 517         CLKDEV_CON_ID("cp_clk",                 &div4_clks[DIV4_CP]),
 518
 519         /* DIV6 clocks */
 520         CLKDEV_CON_ID("sub_clk",                &div6_clks[DIV6_SUB]),
 521
 522         /* MSTP32 clocks */
 523         CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0",    &mstp_clks[MSTP100]),
 524         CLKDEV_DEV_ID("sh_tmu.1",               &mstp_clks[MSTP111]),
 525         CLKDEV_DEV_ID("i2c-sh_mobile.0",        &mstp_clks[MSTP116]),
 526         CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1",    &mstp_clks[MSTP117]),
 527         CLKDEV_DEV_ID("sh_tmu.0",               &mstp_clks[MSTP125]),
 528         CLKDEV_DEV_ID("sh_mobile_ceu.0",        &mstp_clks[MSTP127]),
 529         CLKDEV_DEV_ID("sh_mobile_ceu.1",        &mstp_clks[MSTP128]),
 530
 531         CLKDEV_DEV_ID("sh-sci.4",               &mstp_clks[MSTP200]),
 532         CLKDEV_DEV_ID("sh-sci.3",               &mstp_clks[MSTP201]),
 533         CLKDEV_DEV_ID("sh-sci.2",               &mstp_clks[MSTP202]),
 534         CLKDEV_DEV_ID("sh-sci.1",               &mstp_clks[MSTP203]),
 535         CLKDEV_DEV_ID("sh-sci.0",               &mstp_clks[MSTP204]),
 536         CLKDEV_DEV_ID("sh-sci.8",               &mstp_clks[MSTP206]),
 537         CLKDEV_DEV_ID("sh-sci.5",               &mstp_clks[MSTP207]),
 538
 539         CLKDEV_DEV_ID("sh-sci.7",               &mstp_clks[MSTP222]),
 540         CLKDEV_DEV_ID("sh-sci.6",               &mstp_clks[MSTP230]),
 541
 542         CLKDEV_DEV_ID("sh_cmt.10",              &mstp_clks[MSTP329]),
 543         CLKDEV_DEV_ID("sh_fsi2",                &mstp_clks[MSTP328]),
 544         CLKDEV_DEV_ID("i2c-sh_mobile.1",        &mstp_clks[MSTP323]),
 545         CLKDEV_DEV_ID("renesas_usbhs",          &mstp_clks[MSTP320]),
 546         CLKDEV_DEV_ID("sh_mobile_sdhi.0",       &mstp_clks[MSTP314]),
 547         CLKDEV_DEV_ID("sh_mobile_sdhi.1",       &mstp_clks[MSTP313]),
 548         CLKDEV_DEV_ID("sh_mmcif",               &mstp_clks[MSTP312]),
 549         CLKDEV_DEV_ID("sh-eth",                 &mstp_clks[MSTP309]),
 550
 551         CLKDEV_DEV_ID("sh_mobile_sdhi.2",       &mstp_clks[MSTP415]),
 552
 553         /* ICK */
 554         CLKDEV_ICK_ID("host",   "renesas_usbhs",        &mstp_clks[MSTP416]),
 555         CLKDEV_ICK_ID("func",   "renesas_usbhs",        &mstp_clks[MSTP407]),
 556         CLKDEV_ICK_ID("phy",    "renesas_usbhs",        &mstp_clks[MSTP406]),
 557         CLKDEV_ICK_ID("pci",    "renesas_usbhs",        &div4_clks[DIV4_USBP]),
 558         CLKDEV_ICK_ID("usb24",  "renesas_usbhs",        &usb24_clk),
 559         CLKDEV_ICK_ID("ick",    "sh-mobile-hdmi",       &div6_reparent_clks[DIV6_HDMI]),
 560 };
 561
 562 void __init r8a7740_clock_init(u8 md_ck)
 563 {
 564         int k, ret = 0;
 565
 566         /* detect system clock parent */
 567         if (md_ck & MD_CK1)
 568                 system_clk.parent = &extal1_div2_clk;
 569         else
 570                 system_clk.parent = &extal1_clk;
 571
 572         /* detect RCLK parent */
 573         switch (md_ck & (MD_CK2 | MD_CK1)) {
 574         case MD_CK2 | MD_CK1:
 575                 r_clk.parent = &extal1_div2048_clk;
 576                 break;
 577         case MD_CK2:
 578                 r_clk.parent = &extal1_div1024_clk;
 579                 break;
 580         case MD_CK1:
 581         default:
 582                 r_clk.parent = &extalr_clk;
 583                 break;
 584         }
 585
 586         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
 587                 ret = clk_register(main_clks[k]);
 588
 589         if (!ret)
 590                 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
 591
 592         if (!ret)
 593                 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
 594
 595         if (!ret)
 596                 ret = sh_clk_div6_reparent_register(div6_reparent_clks,
 597                                                     DIV6_REPARENT_NR);
 598
 599         if (!ret)
 600                 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
 601
 602         for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
 603                 ret = clk_register(late_main_clks[k]);
 604
 605         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 606
 607         if (!ret)
 608                 shmobile_clk_init();
 609         else
 610                 panic("failed to setup r8a7740 clocks\n");
 611 }