cd6855290b1fe27f56ba44dfa11923903b7c17bb
[deliverable/linux.git] / arch / arm / mach-shmobile / clock-r8a7778.c
1 /*
2 * r8a7778 clock framework support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * based on r8a7779
8 *
9 * Copyright (C) 2011 Renesas Solutions Corp.
10 * Copyright (C) 2011 Magnus Damm
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25
26 #include <linux/io.h>
27 #include <linux/sh_clk.h>
28 #include <linux/clkdev.h>
29 #include <mach/common.h>
30
31 #define MSTPCR0 IOMEM(0xffc80030)
32 #define MSTPCR1 IOMEM(0xffc80034)
33 #define MSTPCR3 IOMEM(0xffc8003c)
34 #define MSTPSR1 IOMEM(0xffc80044)
35 #define MSTPSR4 IOMEM(0xffc80048)
36 #define MSTPSR6 IOMEM(0xffc8004c)
37 #define MSTPCR4 IOMEM(0xffc80050)
38 #define MSTPCR5 IOMEM(0xffc80054)
39 #define MSTPCR6 IOMEM(0xffc80058)
40
41 /* ioremap() through clock mapping mandatory to avoid
42 * collision with ARM coherent DMA virtual memory range.
43 */
44
45 static struct clk_mapping cpg_mapping = {
46 .phys = 0xffc80000,
47 .len = 0x80,
48 };
49
50 static struct clk clkp = {
51 .rate = 62500000, /* FIXME: shortcut */
52 .flags = CLK_ENABLE_ON_INIT,
53 .mapping = &cpg_mapping,
54 };
55
56 static struct clk *main_clks[] = {
57 &clkp,
58 };
59
60 enum {
61 MSTP114,
62 MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
63 MSTP016, MSTP015,
64 MSTP_NR };
65
66 static struct clk mstp_clks[MSTP_NR] = {
67 [MSTP114] = SH_CLK_MSTP32(&clkp, MSTPCR1, 14, 0), /* Ether */
68 [MSTP026] = SH_CLK_MSTP32(&clkp, MSTPCR0, 26, 0), /* SCIF0 */
69 [MSTP025] = SH_CLK_MSTP32(&clkp, MSTPCR0, 25, 0), /* SCIF1 */
70 [MSTP024] = SH_CLK_MSTP32(&clkp, MSTPCR0, 24, 0), /* SCIF2 */
71 [MSTP023] = SH_CLK_MSTP32(&clkp, MSTPCR0, 23, 0), /* SCIF3 */
72 [MSTP022] = SH_CLK_MSTP32(&clkp, MSTPCR0, 22, 0), /* SCIF4 */
73 [MSTP021] = SH_CLK_MSTP32(&clkp, MSTPCR0, 21, 0), /* SCIF5 */
74 [MSTP016] = SH_CLK_MSTP32(&clkp, MSTPCR0, 16, 0), /* TMU0 */
75 [MSTP015] = SH_CLK_MSTP32(&clkp, MSTPCR0, 15, 0), /* TMU1 */
76 };
77
78 static struct clk_lookup lookups[] = {
79 /* MSTP32 clocks */
80 CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */
81 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
82 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
83 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
84 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */
85 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
86 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
87 CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */
88 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP015]), /* TMU01 */
89 };
90
91 void __init r8a7778_clock_init(void)
92 {
93 int k, ret = 0;
94
95 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
96 ret = clk_register(main_clks[k]);
97
98 if (!ret)
99 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
100
101 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
102
103 if (!ret)
104 shmobile_clk_init();
105 else
106 panic("failed to setup r8a7778 clocks\n");
107 }
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