arch/arm/mach-shmobile/clock-r8a7790.c

   1 /*
   2  * r8a7790 clock framework support
   3  *
   4  * Copyright (C) 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2013  Magnus Damm
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #include <linux/init.h>
  21 #include <linux/io.h>
  22 #include <linux/kernel.h>
  23 #include <linux/sh_clk.h>
  24 #include <linux/clkdev.h>
  25 #include <mach/clock.h>
  26 #include <mach/common.h>
  27 #include <mach/r8a7790.h>
  28
  29 /*
  30  *   MD         EXTAL           PLL0    PLL1    PLL3
  31  * 14 13 19     (MHz)           *1      *1
  32  *---------------------------------------------------
  33  * 0  0  0      15 x 1          x172/2  x208/2  x106
  34  * 0  0  1      15 x 1          x172/2  x208/2  x88
  35  * 0  1  0      20 x 1          x130/2  x156/2  x80
  36  * 0  1  1      20 x 1          x130/2  x156/2  x66
  37  * 1  0  0      26 / 2          x200/2  x240/2  x122
  38  * 1  0  1      26 / 2          x200/2  x240/2  x102
  39  * 1  1  0      30 / 2          x172/2  x208/2  x106
  40  * 1  1  1      30 / 2          x172/2  x208/2  x88
  41  *
  42  * *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2)
  43  *      see "p1 / 2" on R8A7790_CLOCK_ROOT() below
  44  */
  45
  46 #define CPG_BASE        0xe6150000
  47 #define CPG_LEN         0x1000
  48
  49 #define SMSTPCR1        0xe6150134
  50 #define SMSTPCR2        0xe6150138
  51 #define SMSTPCR3        0xe615013c
  52 #define SMSTPCR5        0xe6150144
  53 #define SMSTPCR7        0xe615014c
  54 #define SMSTPCR8        0xe6150990
  55 #define SMSTPCR9        0xe6150994
  56 #define SMSTPCR10       0xe6150998
  57
  58 #define MSTPSR1         IOMEM(0xe6150038)
  59 #define MSTPSR2         IOMEM(0xe6150040)
  60 #define MSTPSR3         IOMEM(0xe6150048)
  61 #define MSTPSR5         IOMEM(0xe615003c)
  62 #define MSTPSR7         IOMEM(0xe61501c4)
  63 #define MSTPSR8         IOMEM(0xe61509a0)
  64 #define MSTPSR9         IOMEM(0xe61509a4)
  65 #define MSTPSR10        IOMEM(0xe61509a8)
  66
  67 #define SDCKCR          0xE6150074
  68 #define SD2CKCR         0xE6150078
  69 #define SD3CKCR         0xE615007C
  70 #define MMC0CKCR        0xE6150240
  71 #define MMC1CKCR        0xE6150244
  72 #define SSPCKCR         0xE6150248
  73 #define SSPRSCKCR       0xE615024C
  74
  75 static struct clk_mapping cpg_mapping = {
  76         .phys   = CPG_BASE,
  77         .len    = CPG_LEN,
  78 };
  79
  80 static struct clk extal_clk = {
  81         /* .rate will be updated on r8a7790_clock_init() */
  82         .mapping        = &cpg_mapping,
  83 };
  84
  85 static struct sh_clk_ops followparent_clk_ops = {
  86         .recalc = followparent_recalc,
  87 };
  88
  89 static struct clk main_clk = {
  90         /* .parent will be set r8a7790_clock_init */
  91         .ops    = &followparent_clk_ops,
  92 };
  93
  94 static struct clk audio_clk_a = {
  95 };
  96
  97 static struct clk audio_clk_b = {
  98 };
  99
 100 static struct clk audio_clk_c = {
 101 };
 102
 103 /*
 104  * clock ratio of these clock will be updated
 105  * on r8a7790_clock_init()
 106  */
 107 SH_FIXED_RATIO_CLK_SET(pll1_clk,                main_clk,       1, 1);
 108 SH_FIXED_RATIO_CLK_SET(pll3_clk,                main_clk,       1, 1);
 109 SH_FIXED_RATIO_CLK_SET(lb_clk,                  pll1_clk,       1, 1);
 110 SH_FIXED_RATIO_CLK_SET(qspi_clk,                pll1_clk,       1, 1);
 111
 112 /* fixed ratio clock */
 113 SH_FIXED_RATIO_CLK_SET(extal_div2_clk,          extal_clk,      1, 2);
 114 SH_FIXED_RATIO_CLK_SET(cp_clk,                  extal_clk,      1, 2);
 115
 116 SH_FIXED_RATIO_CLK_SET(pll1_div2_clk,           pll1_clk,       1, 2);
 117 SH_FIXED_RATIO_CLK_SET(zg_clk,                  pll1_clk,       1, 3);
 118 SH_FIXED_RATIO_CLK_SET(zx_clk,                  pll1_clk,       1, 3);
 119 SH_FIXED_RATIO_CLK_SET(zs_clk,                  pll1_clk,       1, 6);
 120 SH_FIXED_RATIO_CLK_SET(hp_clk,                  pll1_clk,       1, 12);
 121 SH_FIXED_RATIO_CLK_SET(i_clk,                   pll1_clk,       1, 2);
 122 SH_FIXED_RATIO_CLK_SET(b_clk,                   pll1_clk,       1, 12);
 123 SH_FIXED_RATIO_CLK_SET(p_clk,                   pll1_clk,       1, 24);
 124 SH_FIXED_RATIO_CLK_SET(cl_clk,                  pll1_clk,       1, 48);
 125 SH_FIXED_RATIO_CLK_SET(m2_clk,                  pll1_clk,       1, 8);
 126 SH_FIXED_RATIO_CLK_SET(imp_clk,                 pll1_clk,       1, 4);
 127 SH_FIXED_RATIO_CLK_SET(rclk_clk,                pll1_clk,       1, (48 * 1024));
 128 SH_FIXED_RATIO_CLK_SET(oscclk_clk,              pll1_clk,       1, (12 * 1024));
 129
 130 SH_FIXED_RATIO_CLK_SET(zb3_clk,                 pll3_clk,       1, 4);
 131 SH_FIXED_RATIO_CLK_SET(zb3d2_clk,               pll3_clk,       1, 8);
 132 SH_FIXED_RATIO_CLK_SET(ddr_clk,                 pll3_clk,       1, 8);
 133 SH_FIXED_RATIO_CLK_SET(mp_clk,                  pll1_div2_clk,  1, 15);
 134
 135 static struct clk *main_clks[] = {
 136         &audio_clk_a,
 137         &audio_clk_b,
 138         &audio_clk_c,
 139         &extal_clk,
 140         &extal_div2_clk,
 141         &main_clk,
 142         &pll1_clk,
 143         &pll1_div2_clk,
 144         &pll3_clk,
 145         &lb_clk,
 146         &qspi_clk,
 147         &zg_clk,
 148         &zx_clk,
 149         &zs_clk,
 150         &hp_clk,
 151         &i_clk,
 152         &b_clk,
 153         &p_clk,
 154         &cl_clk,
 155         &m2_clk,
 156         &imp_clk,
 157         &rclk_clk,
 158         &oscclk_clk,
 159         &zb3_clk,
 160         &zb3d2_clk,
 161         &ddr_clk,
 162         &mp_clk,
 163         &cp_clk,
 164 };
 165
 166 /* SDHI (DIV4) clock */
 167 static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10 };
 168
 169 static struct clk_div_mult_table div4_div_mult_table = {
 170         .divisors = divisors,
 171         .nr_divisors = ARRAY_SIZE(divisors),
 172 };
 173
 174 static struct clk_div4_table div4_table = {
 175         .div_mult_table = &div4_div_mult_table,
 176 };
 177
 178 enum {
 179         DIV4_SDH, DIV4_SD0, DIV4_SD1, DIV4_NR
 180 };
 181
 182 static struct clk div4_clks[DIV4_NR] = {
 183         [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
 184         [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT),
 185         [DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1de0, CLK_ENABLE_ON_INIT),
 186 };
 187
 188 /* DIV6 clocks */
 189 enum {
 190         DIV6_SD2, DIV6_SD3,
 191         DIV6_MMC0, DIV6_MMC1,
 192         DIV6_SSP, DIV6_SSPRS,
 193         DIV6_NR
 194 };
 195
 196 static struct clk div6_clks[DIV6_NR] = {
 197         [DIV6_SD2]      = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
 198         [DIV6_SD3]      = SH_CLK_DIV6(&pll1_div2_clk, SD3CKCR, 0),
 199         [DIV6_MMC0]     = SH_CLK_DIV6(&pll1_div2_clk, MMC0CKCR, 0),
 200         [DIV6_MMC1]     = SH_CLK_DIV6(&pll1_div2_clk, MMC1CKCR, 0),
 201         [DIV6_SSP]      = SH_CLK_DIV6(&pll1_div2_clk, SSPCKCR, 0),
 202         [DIV6_SSPRS]    = SH_CLK_DIV6(&pll1_div2_clk, SSPRSCKCR, 0),
 203 };
 204
 205 /* MSTP */
 206 enum {
 207         MSTP1017, /* parent of SCU */
 208
 209         MSTP1031, MSTP1030,
 210         MSTP1029, MSTP1028, MSTP1027, MSTP1026, MSTP1025, MSTP1024, MSTP1023, MSTP1022,
 211         MSTP1015, MSTP1014, MSTP1013, MSTP1012, MSTP1011, MSTP1010,
 212         MSTP1009, MSTP1008, MSTP1007, MSTP1006, MSTP1005,
 213         MSTP931, MSTP930, MSTP929, MSTP928,
 214         MSTP917,
 215         MSTP815, MSTP814,
 216         MSTP813,
 217         MSTP811, MSTP810, MSTP809, MSTP808,
 218         MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720,
 219         MSTP717, MSTP716,
 220         MSTP704, MSTP703,
 221         MSTP522,
 222         MSTP502, MSTP501,
 223         MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304,
 224         MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
 225         MSTP124,
 226         MSTP_NR
 227 };
 228
 229 static struct clk mstp_clks[MSTP_NR] = {
 230         [MSTP1031] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 31, MSTPSR10, 0), /* SCU0 */
 231         [MSTP1030] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 30, MSTPSR10, 0), /* SCU1 */
 232         [MSTP1029] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 29, MSTPSR10, 0), /* SCU2 */
 233         [MSTP1028] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 28, MSTPSR10, 0), /* SCU3 */
 234         [MSTP1027] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 27, MSTPSR10, 0), /* SCU4 */
 235         [MSTP1026] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 26, MSTPSR10, 0), /* SCU5 */
 236         [MSTP1025] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 25, MSTPSR10, 0), /* SCU6 */
 237         [MSTP1024] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 24, MSTPSR10, 0), /* SCU7 */
 238         [MSTP1023] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 23, MSTPSR10, 0), /* SCU8 */
 239         [MSTP1022] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 22, MSTPSR10, 0), /* SCU9 */
 240         [MSTP1017] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 17, MSTPSR10, 0), /* SCU */
 241         [MSTP1015] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 15, MSTPSR10, 0), /* SSI0 */
 242         [MSTP1014] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 14, MSTPSR10, 0), /* SSI1 */
 243         [MSTP1013] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 13, MSTPSR10, 0), /* SSI2 */
 244         [MSTP1012] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 12, MSTPSR10, 0), /* SSI3 */
 245         [MSTP1011] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 11, MSTPSR10, 0), /* SSI4 */
 246         [MSTP1010] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 10, MSTPSR10, 0), /* SSI5 */
 247         [MSTP1009] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 9, MSTPSR10, 0), /* SSI6 */
 248         [MSTP1008] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 8, MSTPSR10, 0), /* SSI7 */
 249         [MSTP1007] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 7, MSTPSR10, 0), /* SSI8 */
 250         [MSTP1006] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 6, MSTPSR10, 0), /* SSI9 */
 251         [MSTP1005] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 5, MSTPSR10, 0), /* SSI ALL */
 252         [MSTP931] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */
 253         [MSTP930] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */
 254         [MSTP929] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */
 255         [MSTP928] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
 256         [MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */
 257         [MSTP815] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 15, MSTPSR8, 0), /* SATA0 */
 258         [MSTP814] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 14, MSTPSR8, 0), /* SATA1 */
 259         [MSTP813] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR8, 13, MSTPSR8, 0), /* Ether */
 260         [MSTP811] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 11, MSTPSR8, 0), /* VIN0 */
 261         [MSTP810] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 10, MSTPSR8, 0), /* VIN1 */
 262         [MSTP809] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8,  9, MSTPSR8, 0), /* VIN2 */
 263         [MSTP808] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8,  8, MSTPSR8, 0), /* VIN3 */
 264         [MSTP726] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 26, MSTPSR7, 0), /* LVDS0 */
 265         [MSTP725] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 25, MSTPSR7, 0), /* LVDS1 */
 266         [MSTP724] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 24, MSTPSR7, 0), /* DU0 */
 267         [MSTP723] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 23, MSTPSR7, 0), /* DU1 */
 268         [MSTP722] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 22, MSTPSR7, 0), /* DU2 */
 269         [MSTP721] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 21, MSTPSR7, 0), /* SCIF0 */
 270         [MSTP720] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 20, MSTPSR7, 0), /* SCIF1 */
 271         [MSTP717] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR7, 17, MSTPSR7, 0), /* HSCIF0 */
 272         [MSTP716] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR7, 16, MSTPSR7, 0), /* HSCIF1 */
 273         [MSTP704] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR7, 4, MSTPSR7, 0), /* HSUSB */
 274         [MSTP703] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR7, 3, MSTPSR7, 0), /* EHCI */
 275         [MSTP522] = SH_CLK_MSTP32_STS(&extal_clk, SMSTPCR5, 22, MSTPSR5, 0), /* Thermal */
 276         [MSTP502] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR5, 2, MSTPSR5, 0), /* Audio-DMAC low */
 277         [MSTP501] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR5, 1, MSTPSR5, 0), /* Audio-DMAC hi */
 278         [MSTP315] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, MSTPSR3, 0), /* MMC0 */
 279         [MSTP314] = SH_CLK_MSTP32_STS(&div4_clks[DIV4_SD0], SMSTPCR3, 14, MSTPSR3, 0), /* SDHI0 */
 280         [MSTP313] = SH_CLK_MSTP32_STS(&div4_clks[DIV4_SD1], SMSTPCR3, 13, MSTPSR3, 0), /* SDHI1 */
 281         [MSTP312] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD2], SMSTPCR3, 12, MSTPSR3, 0), /* SDHI2 */
 282         [MSTP311] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD3], SMSTPCR3, 11, MSTPSR3, 0), /* SDHI3 */
 283         [MSTP305] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_MMC1], SMSTPCR3, 5, MSTPSR3, 0), /* MMC1 */
 284         [MSTP304] = SH_CLK_MSTP32_STS(&cp_clk, SMSTPCR3, 4, MSTPSR3, 0), /* TPU0 */
 285         [MSTP216] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 16, MSTPSR2, 0), /* SCIFB2 */
 286         [MSTP207] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 7, MSTPSR2, 0), /* SCIFB1 */
 287         [MSTP206] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 6, MSTPSR2, 0), /* SCIFB0 */
 288         [MSTP204] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 4, MSTPSR2, 0), /* SCIFA0 */
 289         [MSTP203] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 3, MSTPSR2, 0), /* SCIFA1 */
 290         [MSTP202] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 2, MSTPSR2, 0), /* SCIFA2 */
 291         [MSTP124] = SH_CLK_MSTP32_STS(&rclk_clk, SMSTPCR1, 24, MSTPSR1, 0), /* CMT0 */
 292 };
 293
 294 static struct clk_lookup lookups[] = {
 295
 296         /* main clocks */
 297         CLKDEV_CON_ID("audio_clk_a",    &audio_clk_a),
 298         CLKDEV_CON_ID("audio_clk_b",    &audio_clk_b),
 299         CLKDEV_CON_ID("audio_clk_c",    &audio_clk_c),
 300         CLKDEV_CON_ID("audio_clk_internal",     &m2_clk),
 301         CLKDEV_CON_ID("extal",          &extal_clk),
 302         CLKDEV_CON_ID("extal_div2",     &extal_div2_clk),
 303         CLKDEV_CON_ID("main",           &main_clk),
 304         CLKDEV_CON_ID("pll1",           &pll1_clk),
 305         CLKDEV_CON_ID("pll1_div2",      &pll1_div2_clk),
 306         CLKDEV_CON_ID("pll3",           &pll3_clk),
 307         CLKDEV_CON_ID("zg",             &zg_clk),
 308         CLKDEV_CON_ID("zx",             &zx_clk),
 309         CLKDEV_CON_ID("zs",             &zs_clk),
 310         CLKDEV_CON_ID("hp",             &hp_clk),
 311         CLKDEV_CON_ID("i",              &i_clk),
 312         CLKDEV_CON_ID("b",              &b_clk),
 313         CLKDEV_CON_ID("lb",             &lb_clk),
 314         CLKDEV_CON_ID("p",              &p_clk),
 315         CLKDEV_CON_ID("cl",             &cl_clk),
 316         CLKDEV_CON_ID("m2",             &m2_clk),
 317         CLKDEV_CON_ID("imp",            &imp_clk),
 318         CLKDEV_CON_ID("rclk",           &rclk_clk),
 319         CLKDEV_CON_ID("oscclk",         &oscclk_clk),
 320         CLKDEV_CON_ID("zb3",            &zb3_clk),
 321         CLKDEV_CON_ID("zb3d2",          &zb3d2_clk),
 322         CLKDEV_CON_ID("ddr",            &ddr_clk),
 323         CLKDEV_CON_ID("mp",             &mp_clk),
 324         CLKDEV_CON_ID("qspi",           &qspi_clk),
 325         CLKDEV_CON_ID("cp",             &cp_clk),
 326
 327         /* DIV4 */
 328         CLKDEV_CON_ID("sdh",            &div4_clks[DIV4_SDH]),
 329
 330         /* DIV6 */
 331         CLKDEV_CON_ID("ssp",            &div6_clks[DIV6_SSP]),
 332         CLKDEV_CON_ID("ssprs",          &div6_clks[DIV6_SSPRS]),
 333
 334         /* MSTP */
 335         CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP1005]),
 336         CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
 337         CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
 338         CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
 339         CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
 340         CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
 341         CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]),
 342         CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]),
 343         CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
 344         CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]),
 345         CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]),
 346         CLKDEV_DEV_ID("i2c-rcar_gen2.0", &mstp_clks[MSTP931]),
 347         CLKDEV_DEV_ID("i2c-rcar_gen2.1", &mstp_clks[MSTP930]),
 348         CLKDEV_DEV_ID("i2c-rcar_gen2.2", &mstp_clks[MSTP929]),
 349         CLKDEV_DEV_ID("i2c-rcar_gen2.3", &mstp_clks[MSTP928]),
 350         CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
 351         CLKDEV_DEV_ID("r8a7790-vin.0", &mstp_clks[MSTP811]),
 352         CLKDEV_DEV_ID("r8a7790-vin.1", &mstp_clks[MSTP810]),
 353         CLKDEV_DEV_ID("r8a7790-vin.2", &mstp_clks[MSTP809]),
 354         CLKDEV_DEV_ID("r8a7790-vin.3", &mstp_clks[MSTP808]),
 355         CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
 356         CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP502]),
 357         CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP501]),
 358         CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
 359         CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
 360         CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
 361         CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
 362         CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]),
 363         CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
 364         CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
 365         CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
 366         CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP704]),
 367         CLKDEV_DEV_ID("pci-rcar-gen2.0", &mstp_clks[MSTP703]),
 368         CLKDEV_DEV_ID("pci-rcar-gen2.1", &mstp_clks[MSTP703]),
 369         CLKDEV_DEV_ID("pci-rcar-gen2.2", &mstp_clks[MSTP703]),
 370         CLKDEV_DEV_ID("sata-r8a7790.0", &mstp_clks[MSTP815]),
 371         CLKDEV_DEV_ID("sata-r8a7790.1", &mstp_clks[MSTP814]),
 372
 373         /* ICK */
 374         CLKDEV_ICK_ID("usbhs", "usb_phy_rcar_gen2", &mstp_clks[MSTP704]),
 375         CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7790", &mstp_clks[MSTP726]),
 376         CLKDEV_ICK_ID("lvds.1", "rcar-du-r8a7790", &mstp_clks[MSTP725]),
 377         CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]),
 378         CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]),
 379         CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]),
 380         CLKDEV_ICK_ID("clk_a", "rcar_sound", &audio_clk_a),
 381         CLKDEV_ICK_ID("clk_b", "rcar_sound", &audio_clk_b),
 382         CLKDEV_ICK_ID("clk_c", "rcar_sound", &audio_clk_c),
 383         CLKDEV_ICK_ID("clk_i", "rcar_sound", &m2_clk),
 384         CLKDEV_ICK_ID("scu.0", "rcar_sound", &mstp_clks[MSTP1031]),
 385         CLKDEV_ICK_ID("scu.1", "rcar_sound", &mstp_clks[MSTP1030]),
 386         CLKDEV_ICK_ID("scu.2", "rcar_sound", &mstp_clks[MSTP1029]),
 387         CLKDEV_ICK_ID("scu.3", "rcar_sound", &mstp_clks[MSTP1028]),
 388         CLKDEV_ICK_ID("scu.4", "rcar_sound", &mstp_clks[MSTP1027]),
 389         CLKDEV_ICK_ID("scu.5", "rcar_sound", &mstp_clks[MSTP1026]),
 390         CLKDEV_ICK_ID("scu.6", "rcar_sound", &mstp_clks[MSTP1025]),
 391         CLKDEV_ICK_ID("scu.7", "rcar_sound", &mstp_clks[MSTP1024]),
 392         CLKDEV_ICK_ID("scu.8", "rcar_sound", &mstp_clks[MSTP1023]),
 393         CLKDEV_ICK_ID("scu.9", "rcar_sound", &mstp_clks[MSTP1022]),
 394         CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP1015]),
 395         CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP1014]),
 396         CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP1013]),
 397         CLKDEV_ICK_ID("ssi.3", "rcar_sound", &mstp_clks[MSTP1012]),
 398         CLKDEV_ICK_ID("ssi.4", "rcar_sound", &mstp_clks[MSTP1011]),
 399         CLKDEV_ICK_ID("ssi.5", "rcar_sound", &mstp_clks[MSTP1010]),
 400         CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP1009]),
 401         CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP1008]),
 402         CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP1007]),
 403         CLKDEV_ICK_ID("ssi.9", "rcar_sound", &mstp_clks[MSTP1006]),
 404
 405 };
 406
 407 #define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31)              \
 408         extal_clk.rate  = e * 1000 * 1000;                      \
 409         main_clk.parent = m;                                    \
 410         SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1);           \
 411         if (mode & MD(19))                                      \
 412                 SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1);      \
 413         else                                                    \
 414                 SH_CLK_SET_RATIO(&pll3_clk_ratio, p30, 1)
 415
 416
 417 void __init r8a7790_clock_init(void)
 418 {
 419         u32 mode = rcar_gen2_read_mode_pins();
 420         int k, ret = 0;
 421
 422         switch (mode & (MD(14) | MD(13))) {
 423         case 0:
 424                 R8A7790_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
 425                 break;
 426         case MD(13):
 427                 R8A7790_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66);
 428                 break;
 429         case MD(14):
 430                 R8A7790_CLOCK_ROOT(26 / 2, &extal_div2_clk, 200, 240, 122, 102);
 431                 break;
 432         case MD(13) | MD(14):
 433                 R8A7790_CLOCK_ROOT(30 / 2, &extal_div2_clk, 172, 208, 106, 88);
 434                 break;
 435         }
 436
 437         if (mode & (MD(18)))
 438                 SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 36);
 439         else
 440                 SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 24);
 441
 442         if ((mode & (MD(3) | MD(2) | MD(1))) == MD(2))
 443                 SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16);
 444         else
 445                 SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20);
 446
 447         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
 448                 ret = clk_register(main_clks[k]);
 449
 450         if (!ret)
 451                 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
 452
 453         if (!ret)
 454                 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
 455
 456         if (!ret)
 457                 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
 458
 459         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 460
 461         if (!ret)
 462                 shmobile_clk_init();
 463         else
 464                 panic("failed to setup r8a7790 clocks\n");
 465 }