arch/arm/mach-shmobile/intc-r8a7779.c

   1 /*
   2  * r8a7779 processor support - INTC hardware block
   3  *
   4  * Copyright (C) 2011  Renesas Solutions Corp.
   5  * Copyright (C) 2011  Magnus Damm
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/irq.h>
  24 #include <linux/io.h>
  25 #include <mach/common.h>
  26 #include <mach/intc.h>
  27 #include <mach/r8a7779.h>
  28 #include <asm/hardware/gic.h>
  29 #include <asm/mach-types.h>
  30 #include <asm/mach/arch.h>
  31
  32 #define INT2SMSKCR0 0xfe7822a0
  33 #define INT2SMSKCR1 0xfe7822a4
  34 #define INT2SMSKCR2 0xfe7822a8
  35 #define INT2SMSKCR3 0xfe7822ac
  36 #define INT2SMSKCR4 0xfe7822b0
  37
  38 #define INT2NTSR0 0xfe700060
  39 #define INT2NTSR1 0xfe700064
  40
  41 static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
  42 {
  43         return 0; /* always allow wakeup */
  44 }
  45
  46 void __init r8a7779_init_irq(void)
  47 {
  48         void __iomem *gic_dist_base = IOMEM(0xf0001000);
  49         void __iomem *gic_cpu_base = IOMEM(0xf0000100);
  50
  51         /* use GIC to handle interrupts */
  52         gic_init(0, 29, gic_dist_base, gic_cpu_base);
  53         gic_arch_extn.irq_set_wake = r8a7779_set_wake;
  54
  55         /* route all interrupts to ARM */
  56         __raw_writel(0xffffffff, INT2NTSR0);
  57         __raw_writel(0x3fffffff, INT2NTSR1);
  58
  59         /* unmask all known interrupts in INTCS2 */
  60         __raw_writel(0xfffffff0, INT2SMSKCR0);
  61         __raw_writel(0xfff7ffff, INT2SMSKCR1);
  62         __raw_writel(0xfffbffdf, INT2SMSKCR2);
  63         __raw_writel(0xbffffffc, INT2SMSKCR3);
  64         __raw_writel(0x003fee3f, INT2SMSKCR4);
  65 }