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ARM: shmobile: r8a7778: add SSIx DMAEngine support
[deliverable/linux.git] / arch / arm / mach-shmobile / setup-r8a7778.c
1 /*
2 * r8a7778 processor support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 * Copyright (C) 2013 Cogent Embedded, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22 #include <linux/kernel.h>
23 #include <linux/io.h>
24 #include <linux/irqchip/arm-gic.h>
25 #include <linux/of.h>
26 #include <linux/of_platform.h>
27 #include <linux/platform_data/dma-rcar-hpbdma.h>
28 #include <linux/platform_data/gpio-rcar.h>
29 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
30 #include <linux/platform_device.h>
31 #include <linux/irqchip.h>
32 #include <linux/serial_sci.h>
33 #include <linux/sh_timer.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/usb/phy.h>
36 #include <linux/usb/hcd.h>
37 #include <linux/usb/ehci_pdriver.h>
38 #include <linux/usb/ohci_pdriver.h>
39 #include <linux/dma-mapping.h>
40 #include <mach/irqs.h>
41 #include <mach/r8a7778.h>
42 #include <mach/common.h>
43 #include <asm/mach/arch.h>
44 #include <asm/hardware/cache-l2x0.h>
45
46 /* SCIF */
47 #define SCIF_INFO(baseaddr, irq) \
48 { \
49 .mapbase = baseaddr, \
50 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
51 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \
52 .scbrr_algo_id = SCBRR_ALGO_2, \
53 .type = PORT_SCIF, \
54 .irqs = SCIx_IRQ_MUXED(irq), \
55 }
56
57 static struct plat_sci_port scif_platform_data[] __initdata = {
58 SCIF_INFO(0xffe40000, gic_iid(0x66)),
59 SCIF_INFO(0xffe41000, gic_iid(0x67)),
60 SCIF_INFO(0xffe42000, gic_iid(0x68)),
61 SCIF_INFO(0xffe43000, gic_iid(0x69)),
62 SCIF_INFO(0xffe44000, gic_iid(0x6a)),
63 SCIF_INFO(0xffe45000, gic_iid(0x6b)),
64 };
65
66 /* TMU */
67 static struct resource sh_tmu0_resources[] __initdata = {
68 DEFINE_RES_MEM(0xffd80008, 12),
69 DEFINE_RES_IRQ(gic_iid(0x40)),
70 };
71
72 static struct sh_timer_config sh_tmu0_platform_data __initdata = {
73 .name = "TMU00",
74 .channel_offset = 0x4,
75 .timer_bit = 0,
76 .clockevent_rating = 200,
77 };
78
79 static struct resource sh_tmu1_resources[] __initdata = {
80 DEFINE_RES_MEM(0xffd80014, 12),
81 DEFINE_RES_IRQ(gic_iid(0x41)),
82 };
83
84 static struct sh_timer_config sh_tmu1_platform_data __initdata = {
85 .name = "TMU01",
86 .channel_offset = 0x10,
87 .timer_bit = 1,
88 .clocksource_rating = 200,
89 };
90
91 #define r8a7778_register_tmu(idx) \
92 platform_device_register_resndata( \
93 &platform_bus, "sh_tmu", idx, \
94 sh_tmu##idx##_resources, \
95 ARRAY_SIZE(sh_tmu##idx##_resources), \
96 &sh_tmu##idx##_platform_data, \
97 sizeof(sh_tmu##idx##_platform_data))
98
99 int r8a7778_usb_phy_power(bool enable)
100 {
101 static struct usb_phy *phy = NULL;
102 int ret = 0;
103
104 if (!phy)
105 phy = usb_get_phy(USB_PHY_TYPE_USB2);
106
107 if (IS_ERR(phy)) {
108 pr_err("kernel doesn't have usb phy driver\n");
109 return PTR_ERR(phy);
110 }
111
112 if (enable)
113 ret = usb_phy_init(phy);
114 else
115 usb_phy_shutdown(phy);
116
117 return ret;
118 }
119
120 /* USB */
121 static int usb_power_on(struct platform_device *pdev)
122 {
123 int ret = r8a7778_usb_phy_power(true);
124
125 if (ret)
126 return ret;
127
128 pm_runtime_enable(&pdev->dev);
129 pm_runtime_get_sync(&pdev->dev);
130
131 return 0;
132 }
133
134 static void usb_power_off(struct platform_device *pdev)
135 {
136 if (r8a7778_usb_phy_power(false))
137 return;
138
139 pm_runtime_put_sync(&pdev->dev);
140 pm_runtime_disable(&pdev->dev);
141 }
142
143 static int ehci_init_internal_buffer(struct usb_hcd *hcd)
144 {
145 /*
146 * Below are recommended values from the datasheet;
147 * see [USB :: Setting of EHCI Internal Buffer].
148 */
149 /* EHCI IP internal buffer setting */
150 iowrite32(0x00ff0040, hcd->regs + 0x0094);
151 /* EHCI IP internal buffer enable */
152 iowrite32(0x00000001, hcd->regs + 0x009C);
153
154 return 0;
155 }
156
157 static struct usb_ehci_pdata ehci_pdata __initdata = {
158 .power_on = usb_power_on,
159 .power_off = usb_power_off,
160 .power_suspend = usb_power_off,
161 .pre_setup = ehci_init_internal_buffer,
162 };
163
164 static struct resource ehci_resources[] __initdata = {
165 DEFINE_RES_MEM(0xffe70000, 0x400),
166 DEFINE_RES_IRQ(gic_iid(0x4c)),
167 };
168
169 static struct usb_ohci_pdata ohci_pdata __initdata = {
170 .power_on = usb_power_on,
171 .power_off = usb_power_off,
172 .power_suspend = usb_power_off,
173 };
174
175 static struct resource ohci_resources[] __initdata = {
176 DEFINE_RES_MEM(0xffe70400, 0x400),
177 DEFINE_RES_IRQ(gic_iid(0x4c)),
178 };
179
180 #define USB_PLATFORM_INFO(hci) \
181 static struct platform_device_info hci##_info __initdata = { \
182 .parent = &platform_bus, \
183 .name = #hci "-platform", \
184 .id = -1, \
185 .res = hci##_resources, \
186 .num_res = ARRAY_SIZE(hci##_resources), \
187 .data = &hci##_pdata, \
188 .size_data = sizeof(hci##_pdata), \
189 .dma_mask = DMA_BIT_MASK(32), \
190 }
191
192 USB_PLATFORM_INFO(ehci);
193 USB_PLATFORM_INFO(ohci);
194
195 /* PFC/GPIO */
196 static struct resource pfc_resources[] __initdata = {
197 DEFINE_RES_MEM(0xfffc0000, 0x118),
198 };
199
200 #define R8A7778_GPIO(idx) \
201 static struct resource r8a7778_gpio##idx##_resources[] __initdata = { \
202 DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30), \
203 DEFINE_RES_IRQ(gic_iid(0x87)), \
204 }; \
205 \
206 static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data __initdata = { \
207 .gpio_base = 32 * (idx), \
208 .irq_base = GPIO_IRQ_BASE(idx), \
209 .number_of_pins = 32, \
210 .pctl_name = "pfc-r8a7778", \
211 }
212
213 R8A7778_GPIO(0);
214 R8A7778_GPIO(1);
215 R8A7778_GPIO(2);
216 R8A7778_GPIO(3);
217 R8A7778_GPIO(4);
218
219 #define r8a7778_register_gpio(idx) \
220 platform_device_register_resndata( \
221 &platform_bus, "gpio_rcar", idx, \
222 r8a7778_gpio##idx##_resources, \
223 ARRAY_SIZE(r8a7778_gpio##idx##_resources), \
224 &r8a7778_gpio##idx##_platform_data, \
225 sizeof(r8a7778_gpio##idx##_platform_data))
226
227 void __init r8a7778_pinmux_init(void)
228 {
229 platform_device_register_simple(
230 "pfc-r8a7778", -1,
231 pfc_resources,
232 ARRAY_SIZE(pfc_resources));
233
234 r8a7778_register_gpio(0);
235 r8a7778_register_gpio(1);
236 r8a7778_register_gpio(2);
237 r8a7778_register_gpio(3);
238 r8a7778_register_gpio(4);
239 };
240
241 /* I2C */
242 static struct resource i2c_resources[] __initdata = {
243 /* I2C0 */
244 DEFINE_RES_MEM(0xffc70000, 0x1000),
245 DEFINE_RES_IRQ(gic_iid(0x63)),
246 /* I2C1 */
247 DEFINE_RES_MEM(0xffc71000, 0x1000),
248 DEFINE_RES_IRQ(gic_iid(0x6e)),
249 /* I2C2 */
250 DEFINE_RES_MEM(0xffc72000, 0x1000),
251 DEFINE_RES_IRQ(gic_iid(0x6c)),
252 /* I2C3 */
253 DEFINE_RES_MEM(0xffc73000, 0x1000),
254 DEFINE_RES_IRQ(gic_iid(0x6d)),
255 };
256
257 static void __init r8a7778_register_i2c(int id)
258 {
259 BUG_ON(id < 0 || id > 3);
260
261 platform_device_register_simple(
262 "i2c-rcar", id,
263 i2c_resources + (2 * id), 2);
264 }
265
266 /* HSPI */
267 static struct resource hspi_resources[] __initdata = {
268 /* HSPI0 */
269 DEFINE_RES_MEM(0xfffc7000, 0x18),
270 DEFINE_RES_IRQ(gic_iid(0x5f)),
271 /* HSPI1 */
272 DEFINE_RES_MEM(0xfffc8000, 0x18),
273 DEFINE_RES_IRQ(gic_iid(0x74)),
274 /* HSPI2 */
275 DEFINE_RES_MEM(0xfffc6000, 0x18),
276 DEFINE_RES_IRQ(gic_iid(0x75)),
277 };
278
279 static void __init r8a7778_register_hspi(int id)
280 {
281 BUG_ON(id < 0 || id > 2);
282
283 platform_device_register_simple(
284 "sh-hspi", id,
285 hspi_resources + (2 * id), 2);
286 }
287
288 void __init r8a7778_add_dt_devices(void)
289 {
290 int i;
291
292 #ifdef CONFIG_CACHE_L2X0
293 void __iomem *base = ioremap_nocache(0xf0100000, 0x1000);
294 if (base) {
295 /*
296 * Early BRESP enable, Shared attribute override enable, 64K*16way
297 * don't call iounmap(base)
298 */
299 l2x0_init(base, 0x40470000, 0x82000fff);
300 }
301 #endif
302
303 for (i = 0; i < ARRAY_SIZE(scif_platform_data); i++)
304 platform_device_register_data(&platform_bus, "sh-sci", i,
305 &scif_platform_data[i],
306 sizeof(struct plat_sci_port));
307
308 r8a7778_register_tmu(0);
309 r8a7778_register_tmu(1);
310 }
311
312 /* HPB-DMA */
313
314 /* Asynchronous mode register (ASYNCMDR) bits */
315 #define HPB_DMAE_ASYNCMDR_ASMD22_MASK BIT(2) /* SDHI0 */
316 #define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE BIT(2) /* SDHI0 */
317 #define HPB_DMAE_ASYNCMDR_ASMD22_MULTI 0 /* SDHI0 */
318 #define HPB_DMAE_ASYNCMDR_ASMD21_MASK BIT(1) /* SDHI0 */
319 #define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(1) /* SDHI0 */
320 #define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */
321
322 #define HPBDMA_SSI(_id) \
323 { \
324 .id = HPBDMA_SLAVE_SSI## _id ##_TX, \
325 .addr = 0xffd91008 + (_id * 0x40), \
326 .dcr = HPB_DMAE_DCR_CT | \
327 HPB_DMAE_DCR_DIP | \
328 HPB_DMAE_DCR_SPDS_32BIT | \
329 HPB_DMAE_DCR_DMDL | \
330 HPB_DMAE_DCR_DPDS_32BIT, \
331 .port = _id + (_id << 8), \
332 .dma_ch = (28 + _id), \
333 }, { \
334 .id = HPBDMA_SLAVE_SSI## _id ##_RX, \
335 .addr = 0xffd9100c + (_id * 0x40), \
336 .dcr = HPB_DMAE_DCR_CT | \
337 HPB_DMAE_DCR_DIP | \
338 HPB_DMAE_DCR_SMDL | \
339 HPB_DMAE_DCR_SPDS_32BIT | \
340 HPB_DMAE_DCR_DPDS_32BIT, \
341 .port = _id + (_id << 8), \
342 .dma_ch = (28 + _id), \
343 }
344
345 #define HPBDMA_HPBIF(_id) \
346 { \
347 .id = HPBDMA_SLAVE_HPBIF## _id ##_TX, \
348 .addr = 0xffda0000 + (_id * 0x1000), \
349 .dcr = HPB_DMAE_DCR_CT | \
350 HPB_DMAE_DCR_DIP | \
351 HPB_DMAE_DCR_SPDS_32BIT | \
352 HPB_DMAE_DCR_DMDL | \
353 HPB_DMAE_DCR_DPDS_32BIT, \
354 .port = 0x1111, \
355 .dma_ch = (28 + _id), \
356 }, { \
357 .id = HPBDMA_SLAVE_HPBIF## _id ##_RX, \
358 .addr = 0xffda0000 + (_id * 0x1000), \
359 .dcr = HPB_DMAE_DCR_CT | \
360 HPB_DMAE_DCR_DIP | \
361 HPB_DMAE_DCR_SMDL | \
362 HPB_DMAE_DCR_SPDS_32BIT | \
363 HPB_DMAE_DCR_DPDS_32BIT, \
364 .port = 0x1111, \
365 .dma_ch = (28 + _id), \
366 }
367
368 static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
369 {
370 .id = HPBDMA_SLAVE_SDHI0_TX,
371 .addr = 0xffe4c000 + 0x30,
372 .dcr = HPB_DMAE_DCR_SPDS_16BIT |
373 HPB_DMAE_DCR_DMDL |
374 HPB_DMAE_DCR_DPDS_16BIT,
375 .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 |
376 HPB_DMAE_ASYNCRSTR_ASRST22 |
377 HPB_DMAE_ASYNCRSTR_ASRST23,
378 .mdr = HPB_DMAE_ASYNCMDR_ASMD21_MULTI,
379 .mdm = HPB_DMAE_ASYNCMDR_ASMD21_MASK,
380 .port = 0x0D0C,
381 .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
382 .dma_ch = 21,
383 }, {
384 .id = HPBDMA_SLAVE_SDHI0_RX,
385 .addr = 0xffe4c000 + 0x30,
386 .dcr = HPB_DMAE_DCR_SMDL |
387 HPB_DMAE_DCR_SPDS_16BIT |
388 HPB_DMAE_DCR_DPDS_16BIT,
389 .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 |
390 HPB_DMAE_ASYNCRSTR_ASRST22 |
391 HPB_DMAE_ASYNCRSTR_ASRST23,
392 .mdr = HPB_DMAE_ASYNCMDR_ASMD22_MULTI,
393 .mdm = HPB_DMAE_ASYNCMDR_ASMD22_MASK,
394 .port = 0x0D0C,
395 .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
396 .dma_ch = 22,
397 },
398
399 HPBDMA_SSI(0),
400 HPBDMA_SSI(1),
401 HPBDMA_SSI(2),
402 HPBDMA_SSI(3),
403 HPBDMA_SSI(4),
404 HPBDMA_SSI(5),
405 HPBDMA_SSI(6),
406 HPBDMA_SSI(7),
407 HPBDMA_SSI(8),
408
409 HPBDMA_HPBIF(0),
410 HPBDMA_HPBIF(1),
411 HPBDMA_HPBIF(2),
412 HPBDMA_HPBIF(3),
413 HPBDMA_HPBIF(4),
414 HPBDMA_HPBIF(5),
415 HPBDMA_HPBIF(6),
416 HPBDMA_HPBIF(7),
417 HPBDMA_HPBIF(8),
418 };
419
420 static const struct hpb_dmae_channel hpb_dmae_channels[] = {
421 HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */
422 HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */
423 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_TX), /* ch. 28 */
424 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_RX), /* ch. 28 */
425 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_TX), /* ch. 28 */
426 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_RX), /* ch. 28 */
427 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_TX), /* ch. 29 */
428 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_RX), /* ch. 29 */
429 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_TX), /* ch. 29 */
430 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_RX), /* ch. 29 */
431 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_TX), /* ch. 30 */
432 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_RX), /* ch. 30 */
433 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_TX), /* ch. 30 */
434 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_RX), /* ch. 30 */
435 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_TX), /* ch. 31 */
436 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_RX), /* ch. 31 */
437 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_TX), /* ch. 31 */
438 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_RX), /* ch. 31 */
439 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_TX), /* ch. 32 */
440 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_RX), /* ch. 32 */
441 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_TX), /* ch. 32 */
442 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_RX), /* ch. 32 */
443 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_TX), /* ch. 33 */
444 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_RX), /* ch. 33 */
445 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_TX), /* ch. 33 */
446 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_RX), /* ch. 33 */
447 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_TX), /* ch. 34 */
448 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_RX), /* ch. 34 */
449 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_TX), /* ch. 34 */
450 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_RX), /* ch. 34 */
451 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_TX), /* ch. 35 */
452 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_RX), /* ch. 35 */
453 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_TX), /* ch. 35 */
454 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_RX), /* ch. 35 */
455 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_TX), /* ch. 36 */
456 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_RX), /* ch. 36 */
457 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_TX), /* ch. 36 */
458 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_RX), /* ch. 36 */
459 };
460
461 static struct hpb_dmae_pdata dma_platform_data __initdata = {
462 .slaves = hpb_dmae_slaves,
463 .num_slaves = ARRAY_SIZE(hpb_dmae_slaves),
464 .channels = hpb_dmae_channels,
465 .num_channels = ARRAY_SIZE(hpb_dmae_channels),
466 .ts_shift = {
467 [XMIT_SZ_8BIT] = 0,
468 [XMIT_SZ_16BIT] = 1,
469 [XMIT_SZ_32BIT] = 2,
470 },
471 .num_hw_channels = 39,
472 };
473
474 static struct resource hpb_dmae_resources[] __initdata = {
475 /* Channel registers */
476 DEFINE_RES_MEM(0xffc08000, 0x1000),
477 /* Common registers */
478 DEFINE_RES_MEM(0xffc09000, 0x170),
479 /* Asynchronous reset registers */
480 DEFINE_RES_MEM(0xffc00300, 4),
481 /* Asynchronous mode registers */
482 DEFINE_RES_MEM(0xffc00400, 4),
483 /* IRQ for DMA channels */
484 DEFINE_RES_NAMED(gic_iid(0x7b), 5, NULL, IORESOURCE_IRQ),
485 };
486
487 static void __init r8a7778_register_hpb_dmae(void)
488 {
489 platform_device_register_resndata(&platform_bus, "hpb-dma-engine", -1,
490 hpb_dmae_resources,
491 ARRAY_SIZE(hpb_dmae_resources),
492 &dma_platform_data,
493 sizeof(dma_platform_data));
494 }
495
496 void __init r8a7778_add_standard_devices(void)
497 {
498 r8a7778_add_dt_devices();
499 r8a7778_register_i2c(0);
500 r8a7778_register_i2c(1);
501 r8a7778_register_i2c(2);
502 r8a7778_register_i2c(3);
503 r8a7778_register_hspi(0);
504 r8a7778_register_hspi(1);
505 r8a7778_register_hspi(2);
506
507 r8a7778_register_hpb_dmae();
508 }
509
510 void __init r8a7778_init_late(void)
511 {
512 platform_device_register_full(&ehci_info);
513 platform_device_register_full(&ohci_info);
514 }
515
516 static struct renesas_intc_irqpin_config irqpin_platform_data __initdata = {
517 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
518 .sense_bitfield_width = 2,
519 };
520
521 static struct resource irqpin_resources[] __initdata = {
522 DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
523 DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
524 DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
525 DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
526 DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
527 DEFINE_RES_IRQ(gic_iid(0x3b)), /* IRQ0 */
528 DEFINE_RES_IRQ(gic_iid(0x3c)), /* IRQ1 */
529 DEFINE_RES_IRQ(gic_iid(0x3d)), /* IRQ2 */
530 DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */
531 };
532
533 void __init r8a7778_init_irq_extpin_dt(int irlm)
534 {
535 void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
536 unsigned long tmp;
537
538 if (!icr0) {
539 pr_warn("r8a7778: unable to setup external irq pin mode\n");
540 return;
541 }
542
543 tmp = ioread32(icr0);
544 if (irlm)
545 tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
546 else
547 tmp &= ~(1 << 23); /* IRL mode - not supported */
548 tmp |= (1 << 21); /* LVLMODE = 1 */
549 iowrite32(tmp, icr0);
550 iounmap(icr0);
551 }
552
553 void __init r8a7778_init_irq_extpin(int irlm)
554 {
555 r8a7778_init_irq_extpin_dt(irlm);
556 if (irlm)
557 platform_device_register_resndata(
558 &platform_bus, "renesas_intc_irqpin", -1,
559 irqpin_resources, ARRAY_SIZE(irqpin_resources),
560 &irqpin_platform_data, sizeof(irqpin_platform_data));
561 }
562
563 void __init r8a7778_init_delay(void)
564 {
565 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
566 }
567
568 #ifdef CONFIG_USE_OF
569 #define INT2SMSKCR0 0x82288 /* 0xfe782288 */
570 #define INT2SMSKCR1 0x8228c /* 0xfe78228c */
571
572 #define INT2NTSR0 0x00018 /* 0xfe700018 */
573 #define INT2NTSR1 0x0002c /* 0xfe70002c */
574 void __init r8a7778_init_irq_dt(void)
575 {
576 void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000);
577
578 BUG_ON(!base);
579
580 irqchip_init();
581
582 /* route all interrupts to ARM */
583 __raw_writel(0x73ffffff, base + INT2NTSR0);
584 __raw_writel(0xffffffff, base + INT2NTSR1);
585
586 /* unmask all known interrupts in INTCS2 */
587 __raw_writel(0x08330773, base + INT2SMSKCR0);
588 __raw_writel(0x00311110, base + INT2SMSKCR1);
589
590 iounmap(base);
591 }
592
593 static const char *r8a7778_compat_dt[] __initdata = {
594 "renesas,r8a7778",
595 NULL,
596 };
597
598 DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
599 .init_early = r8a7778_init_delay,
600 .init_irq = r8a7778_init_irq_dt,
601 .dt_compat = r8a7778_compat_dt,
602 .init_late = r8a7778_init_late,
603 MACHINE_END
604
605 #endif /* CONFIG_USE_OF */
Linux kernel - Deliverables
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