arch/arm/mach-shmobile/setup-r8a7779.c

   1 /*
   2  * r8a7779 processor support
   3  *
   4  * Copyright (C) 2011, 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2011  Magnus Damm
   6  * Copyright (C) 2013  Cogent Embedded, Inc.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  20  */
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/irq.h>
  25 #include <linux/irqchip.h>
  26 #include <linux/irqchip/arm-gic.h>
  27 #include <linux/of_platform.h>
  28 #include <linux/platform_data/dma-rcar-hpbdma.h>
  29 #include <linux/platform_data/gpio-rcar.h>
  30 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/delay.h>
  33 #include <linux/input.h>
  34 #include <linux/io.h>
  35 #include <linux/serial_sci.h>
  36 #include <linux/sh_timer.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/usb/otg.h>
  39 #include <linux/usb/hcd.h>
  40 #include <linux/usb/ehci_pdriver.h>
  41 #include <linux/usb/ohci_pdriver.h>
  42 #include <linux/pm_runtime.h>
  43
  44 #include <asm/mach-types.h>
  45 #include <asm/mach/arch.h>
  46 #include <asm/mach/time.h>
  47 #include <asm/mach/map.h>
  48 #include <asm/hardware/cache-l2x0.h>
  49
  50 #include "common.h"
  51 #include "irqs.h"
  52 #include "r8a7779.h"
  53
  54 static struct map_desc r8a7779_io_desc[] __initdata = {
  55         /* 2M entity map for 0xf0000000 (MPCORE) */
  56         {
  57                 .virtual        = 0xf0000000,
  58                 .pfn            = __phys_to_pfn(0xf0000000),
  59                 .length         = SZ_2M,
  60                 .type           = MT_DEVICE_NONSHARED
  61         },
  62         /* 16M entity map for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
  63         {
  64                 .virtual        = 0xfe000000,
  65                 .pfn            = __phys_to_pfn(0xfe000000),
  66                 .length         = SZ_16M,
  67                 .type           = MT_DEVICE_NONSHARED
  68         },
  69 };
  70
  71 void __init r8a7779_map_io(void)
  72 {
  73         iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc));
  74 }
  75
  76 /* IRQ */
  77 #define INT2SMSKCR0 IOMEM(0xfe7822a0)
  78 #define INT2SMSKCR1 IOMEM(0xfe7822a4)
  79 #define INT2SMSKCR2 IOMEM(0xfe7822a8)
  80 #define INT2SMSKCR3 IOMEM(0xfe7822ac)
  81 #define INT2SMSKCR4 IOMEM(0xfe7822b0)
  82
  83 #define INT2NTSR0 IOMEM(0xfe700060)
  84 #define INT2NTSR1 IOMEM(0xfe700064)
  85
  86 static struct renesas_intc_irqpin_config irqpin0_platform_data __initdata = {
  87         .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
  88         .sense_bitfield_width = 2,
  89 };
  90
  91 static struct resource irqpin0_resources[] __initdata = {
  92         DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
  93         DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
  94         DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
  95         DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
  96         DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
  97         DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */
  98         DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */
  99         DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */
 100         DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */
 101 };
 102
 103 void __init r8a7779_init_irq_extpin_dt(int irlm)
 104 {
 105         void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
 106         u32 tmp;
 107
 108         if (!icr0) {
 109                 pr_warn("r8a7779: unable to setup external irq pin mode\n");
 110                 return;
 111         }
 112
 113         tmp = ioread32(icr0);
 114         if (irlm)
 115                 tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
 116         else
 117                 tmp &= ~(1 << 23); /* IRL mode - not supported */
 118         tmp |= (1 << 21); /* LVLMODE = 1 */
 119         iowrite32(tmp, icr0);
 120         iounmap(icr0);
 121 }
 122
 123 void __init r8a7779_init_irq_extpin(int irlm)
 124 {
 125         r8a7779_init_irq_extpin_dt(irlm);
 126         if (irlm)
 127                 platform_device_register_resndata(
 128                         &platform_bus, "renesas_intc_irqpin", -1,
 129                         irqpin0_resources, ARRAY_SIZE(irqpin0_resources),
 130                         &irqpin0_platform_data, sizeof(irqpin0_platform_data));
 131 }
 132
 133 /* PFC/GPIO */
 134 static struct resource r8a7779_pfc_resources[] = {
 135         DEFINE_RES_MEM(0xfffc0000, 0x023c),
 136 };
 137
 138 static struct platform_device r8a7779_pfc_device = {
 139         .name           = "pfc-r8a7779",
 140         .id             = -1,
 141         .resource       = r8a7779_pfc_resources,
 142         .num_resources  = ARRAY_SIZE(r8a7779_pfc_resources),
 143 };
 144
 145 #define R8A7779_GPIO(idx, npins) \
 146 static struct resource r8a7779_gpio##idx##_resources[] = {              \
 147         DEFINE_RES_MEM(0xffc40000 + (0x1000 * (idx)), 0x002c),          \
 148         DEFINE_RES_IRQ(gic_iid(0xad + (idx))),                          \
 149 };                                                                      \
 150                                                                         \
 151 static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = {    \
 152         .gpio_base      = 32 * (idx),                                   \
 153         .irq_base       = 0,                                            \
 154         .number_of_pins = npins,                                        \
 155         .pctl_name      = "pfc-r8a7779",                                \
 156 };                                                                      \
 157                                                                         \
 158 static struct platform_device r8a7779_gpio##idx##_device = {            \
 159         .name           = "gpio_rcar",                                  \
 160         .id             = idx,                                          \
 161         .resource       = r8a7779_gpio##idx##_resources,                \
 162         .num_resources  = ARRAY_SIZE(r8a7779_gpio##idx##_resources),    \
 163         .dev            = {                                             \
 164                 .platform_data  = &r8a7779_gpio##idx##_platform_data,   \
 165         },                                                              \
 166 }
 167
 168 R8A7779_GPIO(0, 32);
 169 R8A7779_GPIO(1, 32);
 170 R8A7779_GPIO(2, 32);
 171 R8A7779_GPIO(3, 32);
 172 R8A7779_GPIO(4, 32);
 173 R8A7779_GPIO(5, 32);
 174 R8A7779_GPIO(6, 9);
 175
 176 static struct platform_device *r8a7779_pinctrl_devices[] __initdata = {
 177         &r8a7779_pfc_device,
 178         &r8a7779_gpio0_device,
 179         &r8a7779_gpio1_device,
 180         &r8a7779_gpio2_device,
 181         &r8a7779_gpio3_device,
 182         &r8a7779_gpio4_device,
 183         &r8a7779_gpio5_device,
 184         &r8a7779_gpio6_device,
 185 };
 186
 187 void __init r8a7779_pinmux_init(void)
 188 {
 189         platform_add_devices(r8a7779_pinctrl_devices,
 190                             ARRAY_SIZE(r8a7779_pinctrl_devices));
 191 }
 192
 193 /* SCIF */
 194 #define R8A7779_SCIF(index, baseaddr, irq)                      \
 195 static struct plat_sci_port scif##index##_platform_data = {     \
 196         .type           = PORT_SCIF,                            \
 197         .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,      \
 198         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,     \
 199 };                                                              \
 200                                                                 \
 201 static struct resource scif##index##_resources[] = {            \
 202         DEFINE_RES_MEM(baseaddr, 0x100),                        \
 203         DEFINE_RES_IRQ(irq),                                    \
 204 };                                                              \
 205                                                                 \
 206 static struct platform_device scif##index##_device = {          \
 207         .name           = "sh-sci",                             \
 208         .id             = index,                                \
 209         .resource       = scif##index##_resources,              \
 210         .num_resources  = ARRAY_SIZE(scif##index##_resources),  \
 211         .dev            = {                                     \
 212                 .platform_data  = &scif##index##_platform_data, \
 213         },                                                      \
 214 }
 215
 216 R8A7779_SCIF(0, 0xffe40000, gic_iid(0x78));
 217 R8A7779_SCIF(1, 0xffe41000, gic_iid(0x79));
 218 R8A7779_SCIF(2, 0xffe42000, gic_iid(0x7a));
 219 R8A7779_SCIF(3, 0xffe43000, gic_iid(0x7b));
 220 R8A7779_SCIF(4, 0xffe44000, gic_iid(0x7c));
 221 R8A7779_SCIF(5, 0xffe45000, gic_iid(0x7d));
 222
 223 /* TMU */
 224 static struct sh_timer_config tmu0_platform_data = {
 225         .channels_mask = 7,
 226 };
 227
 228 static struct resource tmu0_resources[] = {
 229         DEFINE_RES_MEM(0xffd80000, 0x30),
 230         DEFINE_RES_IRQ(gic_iid(0x40)),
 231         DEFINE_RES_IRQ(gic_iid(0x41)),
 232         DEFINE_RES_IRQ(gic_iid(0x42)),
 233 };
 234
 235 static struct platform_device tmu0_device = {
 236         .name           = "sh-tmu",
 237         .id             = 0,
 238         .dev = {
 239                 .platform_data  = &tmu0_platform_data,
 240         },
 241         .resource       = tmu0_resources,
 242         .num_resources  = ARRAY_SIZE(tmu0_resources),
 243 };
 244
 245 /* I2C */
 246 static struct resource rcar_i2c0_res[] = {
 247         {
 248                 .start  = 0xffc70000,
 249                 .end    = 0xffc70fff,
 250                 .flags  = IORESOURCE_MEM,
 251         }, {
 252                 .start  = gic_iid(0x6f),
 253                 .flags  = IORESOURCE_IRQ,
 254         },
 255 };
 256
 257 static struct platform_device i2c0_device = {
 258         .name           = "i2c-rcar",
 259         .id             = 0,
 260         .resource       = rcar_i2c0_res,
 261         .num_resources  = ARRAY_SIZE(rcar_i2c0_res),
 262 };
 263
 264 static struct resource rcar_i2c1_res[] = {
 265         {
 266                 .start  = 0xffc71000,
 267                 .end    = 0xffc71fff,
 268                 .flags  = IORESOURCE_MEM,
 269         }, {
 270                 .start  = gic_iid(0x72),
 271                 .flags  = IORESOURCE_IRQ,
 272         },
 273 };
 274
 275 static struct platform_device i2c1_device = {
 276         .name           = "i2c-rcar",
 277         .id             = 1,
 278         .resource       = rcar_i2c1_res,
 279         .num_resources  = ARRAY_SIZE(rcar_i2c1_res),
 280 };
 281
 282 static struct resource rcar_i2c2_res[] = {
 283         {
 284                 .start  = 0xffc72000,
 285                 .end    = 0xffc72fff,
 286                 .flags  = IORESOURCE_MEM,
 287         }, {
 288                 .start  = gic_iid(0x70),
 289                 .flags  = IORESOURCE_IRQ,
 290         },
 291 };
 292
 293 static struct platform_device i2c2_device = {
 294         .name           = "i2c-rcar",
 295         .id             = 2,
 296         .resource       = rcar_i2c2_res,
 297         .num_resources  = ARRAY_SIZE(rcar_i2c2_res),
 298 };
 299
 300 static struct resource rcar_i2c3_res[] = {
 301         {
 302                 .start  = 0xffc73000,
 303                 .end    = 0xffc73fff,
 304                 .flags  = IORESOURCE_MEM,
 305         }, {
 306                 .start  = gic_iid(0x71),
 307                 .flags  = IORESOURCE_IRQ,
 308         },
 309 };
 310
 311 static struct platform_device i2c3_device = {
 312         .name           = "i2c-rcar",
 313         .id             = 3,
 314         .resource       = rcar_i2c3_res,
 315         .num_resources  = ARRAY_SIZE(rcar_i2c3_res),
 316 };
 317
 318 static struct resource sata_resources[] = {
 319         [0] = {
 320                 .name   = "rcar-sata",
 321                 .start  = 0xfc600000,
 322                 .end    = 0xfc601fff,
 323                 .flags  = IORESOURCE_MEM,
 324         },
 325         [1] = {
 326                 .start  = gic_iid(0x84),
 327                 .flags  = IORESOURCE_IRQ,
 328         },
 329 };
 330
 331 static struct platform_device sata_device = {
 332         .name           = "sata_rcar",
 333         .id             = -1,
 334         .resource       = sata_resources,
 335         .num_resources  = ARRAY_SIZE(sata_resources),
 336         .dev            = {
 337                 .dma_mask               = &sata_device.dev.coherent_dma_mask,
 338                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 339         },
 340 };
 341
 342 /* USB */
 343 static struct usb_phy *phy;
 344
 345 static int usb_power_on(struct platform_device *pdev)
 346 {
 347         if (IS_ERR(phy))
 348                 return PTR_ERR(phy);
 349
 350         pm_runtime_enable(&pdev->dev);
 351         pm_runtime_get_sync(&pdev->dev);
 352
 353         usb_phy_init(phy);
 354
 355         return 0;
 356 }
 357
 358 static void usb_power_off(struct platform_device *pdev)
 359 {
 360         if (IS_ERR(phy))
 361                 return;
 362
 363         usb_phy_shutdown(phy);
 364
 365         pm_runtime_put_sync(&pdev->dev);
 366         pm_runtime_disable(&pdev->dev);
 367 }
 368
 369 static int ehci_init_internal_buffer(struct usb_hcd *hcd)
 370 {
 371         /*
 372          * Below are recommended values from the datasheet;
 373          * see [USB :: Setting of EHCI Internal Buffer].
 374          */
 375         /* EHCI IP internal buffer setting */
 376         iowrite32(0x00ff0040, hcd->regs + 0x0094);
 377         /* EHCI IP internal buffer enable */
 378         iowrite32(0x00000001, hcd->regs + 0x009C);
 379
 380         return 0;
 381 }
 382
 383 static struct usb_ehci_pdata ehcix_pdata = {
 384         .power_on       = usb_power_on,
 385         .power_off      = usb_power_off,
 386         .power_suspend  = usb_power_off,
 387         .pre_setup      = ehci_init_internal_buffer,
 388 };
 389
 390 static struct resource ehci0_resources[] = {
 391         [0] = {
 392                 .start  = 0xffe70000,
 393                 .end    = 0xffe70400 - 1,
 394                 .flags  = IORESOURCE_MEM,
 395         },
 396         [1] = {
 397                 .start  = gic_iid(0x4c),
 398                 .flags  = IORESOURCE_IRQ,
 399         },
 400 };
 401
 402 static struct platform_device ehci0_device = {
 403         .name   = "ehci-platform",
 404         .id     = 0,
 405         .dev    = {
 406                 .dma_mask               = &ehci0_device.dev.coherent_dma_mask,
 407                 .coherent_dma_mask      = 0xffffffff,
 408                 .platform_data          = &ehcix_pdata,
 409         },
 410         .num_resources  = ARRAY_SIZE(ehci0_resources),
 411         .resource       = ehci0_resources,
 412 };
 413
 414 static struct resource ehci1_resources[] = {
 415         [0] = {
 416                 .start  = 0xfff70000,
 417                 .end    = 0xfff70400 - 1,
 418                 .flags  = IORESOURCE_MEM,
 419         },
 420         [1] = {
 421                 .start  = gic_iid(0x4d),
 422                 .flags  = IORESOURCE_IRQ,
 423         },
 424 };
 425
 426 static struct platform_device ehci1_device = {
 427         .name   = "ehci-platform",
 428         .id     = 1,
 429         .dev    = {
 430                 .dma_mask               = &ehci1_device.dev.coherent_dma_mask,
 431                 .coherent_dma_mask      = 0xffffffff,
 432                 .platform_data          = &ehcix_pdata,
 433         },
 434         .num_resources  = ARRAY_SIZE(ehci1_resources),
 435         .resource       = ehci1_resources,
 436 };
 437
 438 static struct usb_ohci_pdata ohcix_pdata = {
 439         .power_on       = usb_power_on,
 440         .power_off      = usb_power_off,
 441         .power_suspend  = usb_power_off,
 442 };
 443
 444 static struct resource ohci0_resources[] = {
 445         [0] = {
 446                 .start  = 0xffe70400,
 447                 .end    = 0xffe70800 - 1,
 448                 .flags  = IORESOURCE_MEM,
 449         },
 450         [1] = {
 451                 .start  = gic_iid(0x4c),
 452                 .flags  = IORESOURCE_IRQ,
 453         },
 454 };
 455
 456 static struct platform_device ohci0_device = {
 457         .name   = "ohci-platform",
 458         .id     = 0,
 459         .dev    = {
 460                 .dma_mask               = &ohci0_device.dev.coherent_dma_mask,
 461                 .coherent_dma_mask      = 0xffffffff,
 462                 .platform_data          = &ohcix_pdata,
 463         },
 464         .num_resources  = ARRAY_SIZE(ohci0_resources),
 465         .resource       = ohci0_resources,
 466 };
 467
 468 static struct resource ohci1_resources[] = {
 469         [0] = {
 470                 .start  = 0xfff70400,
 471                 .end    = 0xfff70800 - 1,
 472                 .flags  = IORESOURCE_MEM,
 473         },
 474         [1] = {
 475                 .start  = gic_iid(0x4d),
 476                 .flags  = IORESOURCE_IRQ,
 477         },
 478 };
 479
 480 static struct platform_device ohci1_device = {
 481         .name   = "ohci-platform",
 482         .id     = 1,
 483         .dev    = {
 484                 .dma_mask               = &ohci1_device.dev.coherent_dma_mask,
 485                 .coherent_dma_mask      = 0xffffffff,
 486                 .platform_data          = &ohcix_pdata,
 487         },
 488         .num_resources  = ARRAY_SIZE(ohci1_resources),
 489         .resource       = ohci1_resources,
 490 };
 491
 492 /* HPB-DMA */
 493
 494 /* Asynchronous mode register bits */
 495 #define HPB_DMAE_ASYNCMDR_ASMD43_MASK           BIT(23) /* MMC1 */
 496 #define HPB_DMAE_ASYNCMDR_ASMD43_SINGLE         BIT(23) /* MMC1 */
 497 #define HPB_DMAE_ASYNCMDR_ASMD43_MULTI          0       /* MMC1 */
 498 #define HPB_DMAE_ASYNCMDR_ASBTMD43_MASK         BIT(22) /* MMC1 */
 499 #define HPB_DMAE_ASYNCMDR_ASBTMD43_BURST        BIT(22) /* MMC1 */
 500 #define HPB_DMAE_ASYNCMDR_ASBTMD43_NBURST       0       /* MMC1 */
 501 #define HPB_DMAE_ASYNCMDR_ASMD24_MASK           BIT(21) /* MMC0 */
 502 #define HPB_DMAE_ASYNCMDR_ASMD24_SINGLE         BIT(21) /* MMC0 */
 503 #define HPB_DMAE_ASYNCMDR_ASMD24_MULTI          0       /* MMC0 */
 504 #define HPB_DMAE_ASYNCMDR_ASBTMD24_MASK         BIT(20) /* MMC0 */
 505 #define HPB_DMAE_ASYNCMDR_ASBTMD24_BURST        BIT(20) /* MMC0 */
 506 #define HPB_DMAE_ASYNCMDR_ASBTMD24_NBURST       0       /* MMC0 */
 507 #define HPB_DMAE_ASYNCMDR_ASMD41_MASK           BIT(19) /* SDHI3 */
 508 #define HPB_DMAE_ASYNCMDR_ASMD41_SINGLE         BIT(19) /* SDHI3 */
 509 #define HPB_DMAE_ASYNCMDR_ASMD41_MULTI          0       /* SDHI3 */
 510 #define HPB_DMAE_ASYNCMDR_ASBTMD41_MASK         BIT(18) /* SDHI3 */
 511 #define HPB_DMAE_ASYNCMDR_ASBTMD41_BURST        BIT(18) /* SDHI3 */
 512 #define HPB_DMAE_ASYNCMDR_ASBTMD41_NBURST       0       /* SDHI3 */
 513 #define HPB_DMAE_ASYNCMDR_ASMD40_MASK           BIT(17) /* SDHI3 */
 514 #define HPB_DMAE_ASYNCMDR_ASMD40_SINGLE         BIT(17) /* SDHI3 */
 515 #define HPB_DMAE_ASYNCMDR_ASMD40_MULTI          0       /* SDHI3 */
 516 #define HPB_DMAE_ASYNCMDR_ASBTMD40_MASK         BIT(16) /* SDHI3 */
 517 #define HPB_DMAE_ASYNCMDR_ASBTMD40_BURST        BIT(16) /* SDHI3 */
 518 #define HPB_DMAE_ASYNCMDR_ASBTMD40_NBURST       0       /* SDHI3 */
 519 #define HPB_DMAE_ASYNCMDR_ASMD39_MASK           BIT(15) /* SDHI3 */
 520 #define HPB_DMAE_ASYNCMDR_ASMD39_SINGLE         BIT(15) /* SDHI3 */
 521 #define HPB_DMAE_ASYNCMDR_ASMD39_MULTI          0       /* SDHI3 */
 522 #define HPB_DMAE_ASYNCMDR_ASBTMD39_MASK         BIT(14) /* SDHI3 */
 523 #define HPB_DMAE_ASYNCMDR_ASBTMD39_BURST        BIT(14) /* SDHI3 */
 524 #define HPB_DMAE_ASYNCMDR_ASBTMD39_NBURST       0       /* SDHI3 */
 525 #define HPB_DMAE_ASYNCMDR_ASMD27_MASK           BIT(13) /* SDHI2 */
 526 #define HPB_DMAE_ASYNCMDR_ASMD27_SINGLE         BIT(13) /* SDHI2 */
 527 #define HPB_DMAE_ASYNCMDR_ASMD27_MULTI          0       /* SDHI2 */
 528 #define HPB_DMAE_ASYNCMDR_ASBTMD27_MASK         BIT(12) /* SDHI2 */
 529 #define HPB_DMAE_ASYNCMDR_ASBTMD27_BURST        BIT(12) /* SDHI2 */
 530 #define HPB_DMAE_ASYNCMDR_ASBTMD27_NBURST       0       /* SDHI2 */
 531 #define HPB_DMAE_ASYNCMDR_ASMD26_MASK           BIT(11) /* SDHI2 */
 532 #define HPB_DMAE_ASYNCMDR_ASMD26_SINGLE         BIT(11) /* SDHI2 */
 533 #define HPB_DMAE_ASYNCMDR_ASMD26_MULTI          0       /* SDHI2 */
 534 #define HPB_DMAE_ASYNCMDR_ASBTMD26_MASK         BIT(10) /* SDHI2 */
 535 #define HPB_DMAE_ASYNCMDR_ASBTMD26_BURST        BIT(10) /* SDHI2 */
 536 #define HPB_DMAE_ASYNCMDR_ASBTMD26_NBURST       0       /* SDHI2 */
 537 #define HPB_DMAE_ASYNCMDR_ASMD25_MASK           BIT(9)  /* SDHI2 */
 538 #define HPB_DMAE_ASYNCMDR_ASMD25_SINGLE         BIT(9)  /* SDHI2 */
 539 #define HPB_DMAE_ASYNCMDR_ASMD25_MULTI          0       /* SDHI2 */
 540 #define HPB_DMAE_ASYNCMDR_ASBTMD25_MASK         BIT(8)  /* SDHI2 */
 541 #define HPB_DMAE_ASYNCMDR_ASBTMD25_BURST        BIT(8)  /* SDHI2 */
 542 #define HPB_DMAE_ASYNCMDR_ASBTMD25_NBURST       0       /* SDHI2 */
 543 #define HPB_DMAE_ASYNCMDR_ASMD23_MASK           BIT(7)  /* SDHI0 */
 544 #define HPB_DMAE_ASYNCMDR_ASMD23_SINGLE         BIT(7)  /* SDHI0 */
 545 #define HPB_DMAE_ASYNCMDR_ASMD23_MULTI          0       /* SDHI0 */
 546 #define HPB_DMAE_ASYNCMDR_ASBTMD23_MASK         BIT(6)  /* SDHI0 */
 547 #define HPB_DMAE_ASYNCMDR_ASBTMD23_BURST        BIT(6)  /* SDHI0 */
 548 #define HPB_DMAE_ASYNCMDR_ASBTMD23_NBURST       0       /* SDHI0 */
 549 #define HPB_DMAE_ASYNCMDR_ASMD22_MASK           BIT(5)  /* SDHI0 */
 550 #define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE         BIT(5)  /* SDHI0 */
 551 #define HPB_DMAE_ASYNCMDR_ASMD22_MULTI          0       /* SDHI0 */
 552 #define HPB_DMAE_ASYNCMDR_ASBTMD22_MASK         BIT(4)  /* SDHI0 */
 553 #define HPB_DMAE_ASYNCMDR_ASBTMD22_BURST        BIT(4)  /* SDHI0 */
 554 #define HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST       0       /* SDHI0 */
 555 #define HPB_DMAE_ASYNCMDR_ASMD21_MASK           BIT(3)  /* SDHI0 */
 556 #define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE         BIT(3)  /* SDHI0 */
 557 #define HPB_DMAE_ASYNCMDR_ASMD21_MULTI          0       /* SDHI0 */
 558 #define HPB_DMAE_ASYNCMDR_ASBTMD21_MASK         BIT(2)  /* SDHI0 */
 559 #define HPB_DMAE_ASYNCMDR_ASBTMD21_BURST        BIT(2)  /* SDHI0 */
 560 #define HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST       0       /* SDHI0 */
 561 #define HPB_DMAE_ASYNCMDR_ASMD20_MASK           BIT(1)  /* SDHI1 */
 562 #define HPB_DMAE_ASYNCMDR_ASMD20_SINGLE         BIT(1)  /* SDHI1 */
 563 #define HPB_DMAE_ASYNCMDR_ASMD20_MULTI          0       /* SDHI1 */
 564 #define HPB_DMAE_ASYNCMDR_ASBTMD20_MASK         BIT(0)  /* SDHI1 */
 565 #define HPB_DMAE_ASYNCMDR_ASBTMD20_BURST        BIT(0)  /* SDHI1 */
 566 #define HPB_DMAE_ASYNCMDR_ASBTMD20_NBURST       0       /* SDHI1 */
 567
 568 static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
 569         {
 570                 .id     = HPBDMA_SLAVE_SDHI0_TX,
 571                 .addr   = 0xffe4c000 + 0x30,
 572                 .dcr    = HPB_DMAE_DCR_SPDS_16BIT |
 573                           HPB_DMAE_DCR_DMDL |
 574                           HPB_DMAE_DCR_DPDS_16BIT,
 575                 .rstr   = HPB_DMAE_ASYNCRSTR_ASRST21 |
 576                           HPB_DMAE_ASYNCRSTR_ASRST22 |
 577                           HPB_DMAE_ASYNCRSTR_ASRST23,
 578                 .mdr    = HPB_DMAE_ASYNCMDR_ASMD21_SINGLE |
 579                           HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST,
 580                 .mdm    = HPB_DMAE_ASYNCMDR_ASMD21_MASK |
 581                           HPB_DMAE_ASYNCMDR_ASBTMD21_MASK,
 582                 .port   = 0x0D0C,
 583                 .flags  = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
 584                 .dma_ch = 21,
 585         }, {
 586                 .id     = HPBDMA_SLAVE_SDHI0_RX,
 587                 .addr   = 0xffe4c000 + 0x30,
 588                 .dcr    = HPB_DMAE_DCR_SMDL |
 589                           HPB_DMAE_DCR_SPDS_16BIT |
 590                           HPB_DMAE_DCR_DPDS_16BIT,
 591                 .rstr   = HPB_DMAE_ASYNCRSTR_ASRST21 |
 592                           HPB_DMAE_ASYNCRSTR_ASRST22 |
 593                           HPB_DMAE_ASYNCRSTR_ASRST23,
 594                 .mdr    = HPB_DMAE_ASYNCMDR_ASMD22_SINGLE |
 595                           HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST,
 596                 .mdm    = HPB_DMAE_ASYNCMDR_ASMD22_MASK |
 597                           HPB_DMAE_ASYNCMDR_ASBTMD22_MASK,
 598                 .port   = 0x0D0C,
 599                 .flags  = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
 600                 .dma_ch = 22,
 601         },
 602 };
 603
 604 static const struct hpb_dmae_channel hpb_dmae_channels[] = {
 605         HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */
 606         HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */
 607 };
 608
 609 static struct hpb_dmae_pdata dma_platform_data __initdata = {
 610         .slaves                 = hpb_dmae_slaves,
 611         .num_slaves             = ARRAY_SIZE(hpb_dmae_slaves),
 612         .channels               = hpb_dmae_channels,
 613         .num_channels           = ARRAY_SIZE(hpb_dmae_channels),
 614         .ts_shift               = {
 615                 [XMIT_SZ_8BIT]  = 0,
 616                 [XMIT_SZ_16BIT] = 1,
 617                 [XMIT_SZ_32BIT] = 2,
 618         },
 619         .num_hw_channels        = 44,
 620 };
 621
 622 static struct resource hpb_dmae_resources[] __initdata = {
 623         /* Channel registers */
 624         DEFINE_RES_MEM(0xffc08000, 0x1000),
 625         /* Common registers */
 626         DEFINE_RES_MEM(0xffc09000, 0x170),
 627         /* Asynchronous reset registers */
 628         DEFINE_RES_MEM(0xffc00300, 4),
 629         /* Asynchronous mode registers */
 630         DEFINE_RES_MEM(0xffc00400, 4),
 631         /* IRQ for DMA channels */
 632         DEFINE_RES_NAMED(gic_iid(0x8e), 12, NULL, IORESOURCE_IRQ),
 633 };
 634
 635 static void __init r8a7779_register_hpb_dmae(void)
 636 {
 637         platform_device_register_resndata(&platform_bus, "hpb-dma-engine", -1,
 638                                           hpb_dmae_resources,
 639                                           ARRAY_SIZE(hpb_dmae_resources),
 640                                           &dma_platform_data,
 641                                           sizeof(dma_platform_data));
 642 }
 643
 644 static struct platform_device *r8a7779_devices_dt[] __initdata = {
 645         &tmu0_device,
 646 };
 647
 648 static struct platform_device *r8a7779_standard_devices[] __initdata = {
 649         &scif0_device,
 650         &scif1_device,
 651         &scif2_device,
 652         &scif3_device,
 653         &scif4_device,
 654         &scif5_device,
 655         &i2c0_device,
 656         &i2c1_device,
 657         &i2c2_device,
 658         &i2c3_device,
 659         &sata_device,
 660 };
 661
 662 void __init r8a7779_add_standard_devices(void)
 663 {
 664 #ifdef CONFIG_CACHE_L2X0
 665         /* Shared attribute override enable, 64K*16way */
 666         l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff);
 667 #endif
 668         r8a7779_pm_init();
 669
 670         r8a7779_init_pm_domains();
 671
 672         platform_add_devices(r8a7779_devices_dt,
 673                             ARRAY_SIZE(r8a7779_devices_dt));
 674         platform_add_devices(r8a7779_standard_devices,
 675                             ARRAY_SIZE(r8a7779_standard_devices));
 676         r8a7779_register_hpb_dmae();
 677 }
 678
 679 void __init r8a7779_add_early_devices(void)
 680 {
 681         early_platform_add_devices(r8a7779_devices_dt,
 682                                    ARRAY_SIZE(r8a7779_devices_dt));
 683
 684         /* Early serial console setup is not included here due to
 685          * memory map collisions. The SCIF serial ports in r8a7779
 686          * are difficult to entity map 1:1 due to collision with the
 687          * virtual memory range used by the coherent DMA code on ARM.
 688          *
 689          * Anyone wanting to debug early can remove UPF_IOREMAP from
 690          * the sh-sci serial console platform data, adjust mapbase
 691          * to a static M:N virt:phys mapping that needs to be added to
 692          * the mappings passed with iotable_init() above.
 693          *
 694          * Then add a call to shmobile_setup_console() from this function.
 695          *
 696          * As a final step pass earlyprint=sh-sci.2,115200 on the kernel
 697          * command line in case of the marzen board.
 698          */
 699 }
 700
 701 static struct platform_device *r8a7779_late_devices[] __initdata = {
 702         &ehci0_device,
 703         &ehci1_device,
 704         &ohci0_device,
 705         &ohci1_device,
 706 };
 707
 708 void __init r8a7779_init_late(void)
 709 {
 710         /* get USB PHY */
 711         phy = usb_get_phy(USB_PHY_TYPE_USB2);
 712
 713         shmobile_init_late();
 714         platform_add_devices(r8a7779_late_devices,
 715                              ARRAY_SIZE(r8a7779_late_devices));
 716 }
 717
 718 #ifdef CONFIG_USE_OF
 719 static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
 720 {
 721         return 0; /* always allow wakeup */
 722 }
 723
 724 void __init r8a7779_init_irq_dt(void)
 725 {
 726         gic_arch_extn.irq_set_wake = r8a7779_set_wake;
 727
 728         irqchip_init();
 729
 730         /* route all interrupts to ARM */
 731         __raw_writel(0xffffffff, INT2NTSR0);
 732         __raw_writel(0x3fffffff, INT2NTSR1);
 733
 734         /* unmask all known interrupts in INTCS2 */
 735         __raw_writel(0xfffffff0, INT2SMSKCR0);
 736         __raw_writel(0xfff7ffff, INT2SMSKCR1);
 737         __raw_writel(0xfffbffdf, INT2SMSKCR2);
 738         __raw_writel(0xbffffffc, INT2SMSKCR3);
 739         __raw_writel(0x003fee3f, INT2SMSKCR4);
 740 }
 741
 742 void __init r8a7779_add_standard_devices_dt(void)
 743 {
 744         platform_add_devices(r8a7779_devices_dt,
 745                              ARRAY_SIZE(r8a7779_devices_dt));
 746 }
 747
 748 #define MODEMR          0xffcc0020
 749
 750 u32 __init r8a7779_read_mode_pins(void)
 751 {
 752         static u32 mode;
 753         static bool mode_valid;
 754
 755         if (!mode_valid) {
 756                 void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
 757                 BUG_ON(!modemr);
 758                 mode = ioread32(modemr);
 759                 iounmap(modemr);
 760                 mode_valid = true;
 761         }
 762
 763         return mode;
 764 }
 765
 766 static const char *r8a7779_compat_dt[] __initdata = {
 767         "renesas,r8a7779",
 768         NULL,
 769 };
 770
 771 DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
 772         .map_io         = r8a7779_map_io,
 773         .init_early     = shmobile_init_delay,
 774         .nr_irqs        = NR_IRQS_LEGACY,
 775         .init_irq       = r8a7779_init_irq_dt,
 776         .init_machine   = r8a7779_add_standard_devices_dt,
 777         .init_late      = r8a7779_init_late,
 778         .dt_compat      = r8a7779_compat_dt,
 779 MACHINE_END
 780 #endif /* CONFIG_USE_OF */