arch/arm/mach-shmobile/setup-r8a7779.c

   1 /*
   2  * r8a7779 processor support
   3  *
   4  * Copyright (C) 2011, 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2011  Magnus Damm
   6  * Copyright (C) 2013  Cogent Embedded, Inc.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17 #include <linux/clk/shmobile.h>
  18 #include <linux/clocksource.h>
  19 #include <linux/kernel.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/irq.h>
  23 #include <linux/irqchip.h>
  24 #include <linux/irqchip/arm-gic.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/platform_data/dma-rcar-hpbdma.h>
  27 #include <linux/platform_data/gpio-rcar.h>
  28 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/delay.h>
  31 #include <linux/input.h>
  32 #include <linux/io.h>
  33 #include <linux/serial_sci.h>
  34 #include <linux/sh_timer.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/usb/otg.h>
  37 #include <linux/usb/hcd.h>
  38 #include <linux/usb/ehci_pdriver.h>
  39 #include <linux/usb/ohci_pdriver.h>
  40 #include <linux/pm_runtime.h>
  41
  42 #include <asm/mach-types.h>
  43 #include <asm/mach/arch.h>
  44 #include <asm/mach/time.h>
  45 #include <asm/mach/map.h>
  46 #include <asm/hardware/cache-l2x0.h>
  47
  48 #include "common.h"
  49 #include "irqs.h"
  50 #include "r8a7779.h"
  51
  52 static struct map_desc r8a7779_io_desc[] __initdata = {
  53         /* 2M identity mapping for 0xf0000000 (MPCORE) */
  54         {
  55                 .virtual        = 0xf0000000,
  56                 .pfn            = __phys_to_pfn(0xf0000000),
  57                 .length         = SZ_2M,
  58                 .type           = MT_DEVICE_NONSHARED
  59         },
  60         /* 16M identity mapping for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
  61         {
  62                 .virtual        = 0xfe000000,
  63                 .pfn            = __phys_to_pfn(0xfe000000),
  64                 .length         = SZ_16M,
  65                 .type           = MT_DEVICE_NONSHARED
  66         },
  67 };
  68
  69 void __init r8a7779_map_io(void)
  70 {
  71         debug_ll_io_init();
  72         iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc));
  73 }
  74
  75 /* IRQ */
  76 #define INT2SMSKCR0 IOMEM(0xfe7822a0)
  77 #define INT2SMSKCR1 IOMEM(0xfe7822a4)
  78 #define INT2SMSKCR2 IOMEM(0xfe7822a8)
  79 #define INT2SMSKCR3 IOMEM(0xfe7822ac)
  80 #define INT2SMSKCR4 IOMEM(0xfe7822b0)
  81
  82 #define INT2NTSR0 IOMEM(0xfe700060)
  83 #define INT2NTSR1 IOMEM(0xfe700064)
  84
  85 static struct renesas_intc_irqpin_config irqpin0_platform_data __initdata = {
  86         .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
  87         .sense_bitfield_width = 2,
  88 };
  89
  90 static struct resource irqpin0_resources[] __initdata = {
  91         DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
  92         DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
  93         DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
  94         DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
  95         DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
  96         DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */
  97         DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */
  98         DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */
  99         DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */
 100 };
 101
 102 static void __init r8a7779_init_irq_extpin_dt(int irlm)
 103 {
 104         void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
 105         u32 tmp;
 106
 107         if (!icr0) {
 108                 pr_warn("r8a7779: unable to setup external irq pin mode\n");
 109                 return;
 110         }
 111
 112         tmp = ioread32(icr0);
 113         if (irlm)
 114                 tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
 115         else
 116                 tmp &= ~(1 << 23); /* IRL mode - not supported */
 117         tmp |= (1 << 21); /* LVLMODE = 1 */
 118         iowrite32(tmp, icr0);
 119         iounmap(icr0);
 120 }
 121
 122 void __init r8a7779_init_irq_extpin(int irlm)
 123 {
 124         r8a7779_init_irq_extpin_dt(irlm);
 125         if (irlm)
 126                 platform_device_register_resndata(
 127                         NULL, "renesas_intc_irqpin", -1,
 128                         irqpin0_resources, ARRAY_SIZE(irqpin0_resources),
 129                         &irqpin0_platform_data, sizeof(irqpin0_platform_data));
 130 }
 131
 132 /* PFC/GPIO */
 133 static struct resource r8a7779_pfc_resources[] = {
 134         DEFINE_RES_MEM(0xfffc0000, 0x023c),
 135 };
 136
 137 static struct platform_device r8a7779_pfc_device = {
 138         .name           = "pfc-r8a7779",
 139         .id             = -1,
 140         .resource       = r8a7779_pfc_resources,
 141         .num_resources  = ARRAY_SIZE(r8a7779_pfc_resources),
 142 };
 143
 144 #define R8A7779_GPIO(idx, npins) \
 145 static struct resource r8a7779_gpio##idx##_resources[] = {              \
 146         DEFINE_RES_MEM(0xffc40000 + (0x1000 * (idx)), 0x002c),          \
 147         DEFINE_RES_IRQ(gic_iid(0xad + (idx))),                          \
 148 };                                                                      \
 149                                                                         \
 150 static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = {    \
 151         .gpio_base      = 32 * (idx),                                   \
 152         .irq_base       = 0,                                            \
 153         .number_of_pins = npins,                                        \
 154         .pctl_name      = "pfc-r8a7779",                                \
 155 };                                                                      \
 156                                                                         \
 157 static struct platform_device r8a7779_gpio##idx##_device = {            \
 158         .name           = "gpio_rcar",                                  \
 159         .id             = idx,                                          \
 160         .resource       = r8a7779_gpio##idx##_resources,                \
 161         .num_resources  = ARRAY_SIZE(r8a7779_gpio##idx##_resources),    \
 162         .dev            = {                                             \
 163                 .platform_data  = &r8a7779_gpio##idx##_platform_data,   \
 164         },                                                              \
 165 }
 166
 167 R8A7779_GPIO(0, 32);
 168 R8A7779_GPIO(1, 32);
 169 R8A7779_GPIO(2, 32);
 170 R8A7779_GPIO(3, 32);
 171 R8A7779_GPIO(4, 32);
 172 R8A7779_GPIO(5, 32);
 173 R8A7779_GPIO(6, 9);
 174
 175 static struct platform_device *r8a7779_pinctrl_devices[] __initdata = {
 176         &r8a7779_pfc_device,
 177         &r8a7779_gpio0_device,
 178         &r8a7779_gpio1_device,
 179         &r8a7779_gpio2_device,
 180         &r8a7779_gpio3_device,
 181         &r8a7779_gpio4_device,
 182         &r8a7779_gpio5_device,
 183         &r8a7779_gpio6_device,
 184 };
 185
 186 void __init r8a7779_pinmux_init(void)
 187 {
 188         platform_add_devices(r8a7779_pinctrl_devices,
 189                             ARRAY_SIZE(r8a7779_pinctrl_devices));
 190 }
 191
 192 /* SCIF */
 193 #define R8A7779_SCIF(index, baseaddr, irq)                      \
 194 static struct plat_sci_port scif##index##_platform_data = {     \
 195         .type           = PORT_SCIF,                            \
 196         .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,      \
 197         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,     \
 198 };                                                              \
 199                                                                 \
 200 static struct resource scif##index##_resources[] = {            \
 201         DEFINE_RES_MEM(baseaddr, 0x100),                        \
 202         DEFINE_RES_IRQ(irq),                                    \
 203 };                                                              \
 204                                                                 \
 205 static struct platform_device scif##index##_device = {          \
 206         .name           = "sh-sci",                             \
 207         .id             = index,                                \
 208         .resource       = scif##index##_resources,              \
 209         .num_resources  = ARRAY_SIZE(scif##index##_resources),  \
 210         .dev            = {                                     \
 211                 .platform_data  = &scif##index##_platform_data, \
 212         },                                                      \
 213 }
 214
 215 R8A7779_SCIF(0, 0xffe40000, gic_iid(0x78));
 216 R8A7779_SCIF(1, 0xffe41000, gic_iid(0x79));
 217 R8A7779_SCIF(2, 0xffe42000, gic_iid(0x7a));
 218 R8A7779_SCIF(3, 0xffe43000, gic_iid(0x7b));
 219 R8A7779_SCIF(4, 0xffe44000, gic_iid(0x7c));
 220 R8A7779_SCIF(5, 0xffe45000, gic_iid(0x7d));
 221
 222 /* TMU */
 223 static struct sh_timer_config tmu0_platform_data = {
 224         .channels_mask = 7,
 225 };
 226
 227 static struct resource tmu0_resources[] = {
 228         DEFINE_RES_MEM(0xffd80000, 0x30),
 229         DEFINE_RES_IRQ(gic_iid(0x40)),
 230         DEFINE_RES_IRQ(gic_iid(0x41)),
 231         DEFINE_RES_IRQ(gic_iid(0x42)),
 232 };
 233
 234 static struct platform_device tmu0_device = {
 235         .name           = "sh-tmu",
 236         .id             = 0,
 237         .dev = {
 238                 .platform_data  = &tmu0_platform_data,
 239         },
 240         .resource       = tmu0_resources,
 241         .num_resources  = ARRAY_SIZE(tmu0_resources),
 242 };
 243
 244 /* I2C */
 245 static struct resource rcar_i2c0_res[] = {
 246         {
 247                 .start  = 0xffc70000,
 248                 .end    = 0xffc70fff,
 249                 .flags  = IORESOURCE_MEM,
 250         }, {
 251                 .start  = gic_iid(0x6f),
 252                 .flags  = IORESOURCE_IRQ,
 253         },
 254 };
 255
 256 static struct platform_device i2c0_device = {
 257         .name           = "i2c-rcar",
 258         .id             = 0,
 259         .resource       = rcar_i2c0_res,
 260         .num_resources  = ARRAY_SIZE(rcar_i2c0_res),
 261 };
 262
 263 static struct resource rcar_i2c1_res[] = {
 264         {
 265                 .start  = 0xffc71000,
 266                 .end    = 0xffc71fff,
 267                 .flags  = IORESOURCE_MEM,
 268         }, {
 269                 .start  = gic_iid(0x72),
 270                 .flags  = IORESOURCE_IRQ,
 271         },
 272 };
 273
 274 static struct platform_device i2c1_device = {
 275         .name           = "i2c-rcar",
 276         .id             = 1,
 277         .resource       = rcar_i2c1_res,
 278         .num_resources  = ARRAY_SIZE(rcar_i2c1_res),
 279 };
 280
 281 static struct resource rcar_i2c2_res[] = {
 282         {
 283                 .start  = 0xffc72000,
 284                 .end    = 0xffc72fff,
 285                 .flags  = IORESOURCE_MEM,
 286         }, {
 287                 .start  = gic_iid(0x70),
 288                 .flags  = IORESOURCE_IRQ,
 289         },
 290 };
 291
 292 static struct platform_device i2c2_device = {
 293         .name           = "i2c-rcar",
 294         .id             = 2,
 295         .resource       = rcar_i2c2_res,
 296         .num_resources  = ARRAY_SIZE(rcar_i2c2_res),
 297 };
 298
 299 static struct resource rcar_i2c3_res[] = {
 300         {
 301                 .start  = 0xffc73000,
 302                 .end    = 0xffc73fff,
 303                 .flags  = IORESOURCE_MEM,
 304         }, {
 305                 .start  = gic_iid(0x71),
 306                 .flags  = IORESOURCE_IRQ,
 307         },
 308 };
 309
 310 static struct platform_device i2c3_device = {
 311         .name           = "i2c-rcar",
 312         .id             = 3,
 313         .resource       = rcar_i2c3_res,
 314         .num_resources  = ARRAY_SIZE(rcar_i2c3_res),
 315 };
 316
 317 static struct resource sata_resources[] = {
 318         [0] = {
 319                 .name   = "rcar-sata",
 320                 .start  = 0xfc600000,
 321                 .end    = 0xfc601fff,
 322                 .flags  = IORESOURCE_MEM,
 323         },
 324         [1] = {
 325                 .start  = gic_iid(0x84),
 326                 .flags  = IORESOURCE_IRQ,
 327         },
 328 };
 329
 330 static struct platform_device sata_device = {
 331         .name           = "sata_rcar",
 332         .id             = -1,
 333         .resource       = sata_resources,
 334         .num_resources  = ARRAY_SIZE(sata_resources),
 335         .dev            = {
 336                 .dma_mask               = &sata_device.dev.coherent_dma_mask,
 337                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 338         },
 339 };
 340
 341 /* USB */
 342 static struct usb_phy *phy;
 343
 344 static int usb_power_on(struct platform_device *pdev)
 345 {
 346         if (IS_ERR(phy))
 347                 return PTR_ERR(phy);
 348
 349         pm_runtime_enable(&pdev->dev);
 350         pm_runtime_get_sync(&pdev->dev);
 351
 352         usb_phy_init(phy);
 353
 354         return 0;
 355 }
 356
 357 static void usb_power_off(struct platform_device *pdev)
 358 {
 359         if (IS_ERR(phy))
 360                 return;
 361
 362         usb_phy_shutdown(phy);
 363
 364         pm_runtime_put_sync(&pdev->dev);
 365         pm_runtime_disable(&pdev->dev);
 366 }
 367
 368 static int ehci_init_internal_buffer(struct usb_hcd *hcd)
 369 {
 370         /*
 371          * Below are recommended values from the datasheet;
 372          * see [USB :: Setting of EHCI Internal Buffer].
 373          */
 374         /* EHCI IP internal buffer setting */
 375         iowrite32(0x00ff0040, hcd->regs + 0x0094);
 376         /* EHCI IP internal buffer enable */
 377         iowrite32(0x00000001, hcd->regs + 0x009C);
 378
 379         return 0;
 380 }
 381
 382 static struct usb_ehci_pdata ehcix_pdata = {
 383         .power_on       = usb_power_on,
 384         .power_off      = usb_power_off,
 385         .power_suspend  = usb_power_off,
 386         .pre_setup      = ehci_init_internal_buffer,
 387 };
 388
 389 static struct resource ehci0_resources[] = {
 390         [0] = {
 391                 .start  = 0xffe70000,
 392                 .end    = 0xffe70400 - 1,
 393                 .flags  = IORESOURCE_MEM,
 394         },
 395         [1] = {
 396                 .start  = gic_iid(0x4c),
 397                 .flags  = IORESOURCE_IRQ,
 398         },
 399 };
 400
 401 static struct platform_device ehci0_device = {
 402         .name   = "ehci-platform",
 403         .id     = 0,
 404         .dev    = {
 405                 .dma_mask               = &ehci0_device.dev.coherent_dma_mask,
 406                 .coherent_dma_mask      = 0xffffffff,
 407                 .platform_data          = &ehcix_pdata,
 408         },
 409         .num_resources  = ARRAY_SIZE(ehci0_resources),
 410         .resource       = ehci0_resources,
 411 };
 412
 413 static struct resource ehci1_resources[] = {
 414         [0] = {
 415                 .start  = 0xfff70000,
 416                 .end    = 0xfff70400 - 1,
 417                 .flags  = IORESOURCE_MEM,
 418         },
 419         [1] = {
 420                 .start  = gic_iid(0x4d),
 421                 .flags  = IORESOURCE_IRQ,
 422         },
 423 };
 424
 425 static struct platform_device ehci1_device = {
 426         .name   = "ehci-platform",
 427         .id     = 1,
 428         .dev    = {
 429                 .dma_mask               = &ehci1_device.dev.coherent_dma_mask,
 430                 .coherent_dma_mask      = 0xffffffff,
 431                 .platform_data          = &ehcix_pdata,
 432         },
 433         .num_resources  = ARRAY_SIZE(ehci1_resources),
 434         .resource       = ehci1_resources,
 435 };
 436
 437 static struct usb_ohci_pdata ohcix_pdata = {
 438         .power_on       = usb_power_on,
 439         .power_off      = usb_power_off,
 440         .power_suspend  = usb_power_off,
 441 };
 442
 443 static struct resource ohci0_resources[] = {
 444         [0] = {
 445                 .start  = 0xffe70400,
 446                 .end    = 0xffe70800 - 1,
 447                 .flags  = IORESOURCE_MEM,
 448         },
 449         [1] = {
 450                 .start  = gic_iid(0x4c),
 451                 .flags  = IORESOURCE_IRQ,
 452         },
 453 };
 454
 455 static struct platform_device ohci0_device = {
 456         .name   = "ohci-platform",
 457         .id     = 0,
 458         .dev    = {
 459                 .dma_mask               = &ohci0_device.dev.coherent_dma_mask,
 460                 .coherent_dma_mask      = 0xffffffff,
 461                 .platform_data          = &ohcix_pdata,
 462         },
 463         .num_resources  = ARRAY_SIZE(ohci0_resources),
 464         .resource       = ohci0_resources,
 465 };
 466
 467 static struct resource ohci1_resources[] = {
 468         [0] = {
 469                 .start  = 0xfff70400,
 470                 .end    = 0xfff70800 - 1,
 471                 .flags  = IORESOURCE_MEM,
 472         },
 473         [1] = {
 474                 .start  = gic_iid(0x4d),
 475                 .flags  = IORESOURCE_IRQ,
 476         },
 477 };
 478
 479 static struct platform_device ohci1_device = {
 480         .name   = "ohci-platform",
 481         .id     = 1,
 482         .dev    = {
 483                 .dma_mask               = &ohci1_device.dev.coherent_dma_mask,
 484                 .coherent_dma_mask      = 0xffffffff,
 485                 .platform_data          = &ohcix_pdata,
 486         },
 487         .num_resources  = ARRAY_SIZE(ohci1_resources),
 488         .resource       = ohci1_resources,
 489 };
 490
 491 /* HPB-DMA */
 492
 493 /* Asynchronous mode register bits */
 494 #define HPB_DMAE_ASYNCMDR_ASMD43_MASK           BIT(23) /* MMC1 */
 495 #define HPB_DMAE_ASYNCMDR_ASMD43_SINGLE         BIT(23) /* MMC1 */
 496 #define HPB_DMAE_ASYNCMDR_ASMD43_MULTI          0       /* MMC1 */
 497 #define HPB_DMAE_ASYNCMDR_ASBTMD43_MASK         BIT(22) /* MMC1 */
 498 #define HPB_DMAE_ASYNCMDR_ASBTMD43_BURST        BIT(22) /* MMC1 */
 499 #define HPB_DMAE_ASYNCMDR_ASBTMD43_NBURST       0       /* MMC1 */
 500 #define HPB_DMAE_ASYNCMDR_ASMD24_MASK           BIT(21) /* MMC0 */
 501 #define HPB_DMAE_ASYNCMDR_ASMD24_SINGLE         BIT(21) /* MMC0 */
 502 #define HPB_DMAE_ASYNCMDR_ASMD24_MULTI          0       /* MMC0 */
 503 #define HPB_DMAE_ASYNCMDR_ASBTMD24_MASK         BIT(20) /* MMC0 */
 504 #define HPB_DMAE_ASYNCMDR_ASBTMD24_BURST        BIT(20) /* MMC0 */
 505 #define HPB_DMAE_ASYNCMDR_ASBTMD24_NBURST       0       /* MMC0 */
 506 #define HPB_DMAE_ASYNCMDR_ASMD41_MASK           BIT(19) /* SDHI3 */
 507 #define HPB_DMAE_ASYNCMDR_ASMD41_SINGLE         BIT(19) /* SDHI3 */
 508 #define HPB_DMAE_ASYNCMDR_ASMD41_MULTI          0       /* SDHI3 */
 509 #define HPB_DMAE_ASYNCMDR_ASBTMD41_MASK         BIT(18) /* SDHI3 */
 510 #define HPB_DMAE_ASYNCMDR_ASBTMD41_BURST        BIT(18) /* SDHI3 */
 511 #define HPB_DMAE_ASYNCMDR_ASBTMD41_NBURST       0       /* SDHI3 */
 512 #define HPB_DMAE_ASYNCMDR_ASMD40_MASK           BIT(17) /* SDHI3 */
 513 #define HPB_DMAE_ASYNCMDR_ASMD40_SINGLE         BIT(17) /* SDHI3 */
 514 #define HPB_DMAE_ASYNCMDR_ASMD40_MULTI          0       /* SDHI3 */
 515 #define HPB_DMAE_ASYNCMDR_ASBTMD40_MASK         BIT(16) /* SDHI3 */
 516 #define HPB_DMAE_ASYNCMDR_ASBTMD40_BURST        BIT(16) /* SDHI3 */
 517 #define HPB_DMAE_ASYNCMDR_ASBTMD40_NBURST       0       /* SDHI3 */
 518 #define HPB_DMAE_ASYNCMDR_ASMD39_MASK           BIT(15) /* SDHI3 */
 519 #define HPB_DMAE_ASYNCMDR_ASMD39_SINGLE         BIT(15) /* SDHI3 */
 520 #define HPB_DMAE_ASYNCMDR_ASMD39_MULTI          0       /* SDHI3 */
 521 #define HPB_DMAE_ASYNCMDR_ASBTMD39_MASK         BIT(14) /* SDHI3 */
 522 #define HPB_DMAE_ASYNCMDR_ASBTMD39_BURST        BIT(14) /* SDHI3 */
 523 #define HPB_DMAE_ASYNCMDR_ASBTMD39_NBURST       0       /* SDHI3 */
 524 #define HPB_DMAE_ASYNCMDR_ASMD27_MASK           BIT(13) /* SDHI2 */
 525 #define HPB_DMAE_ASYNCMDR_ASMD27_SINGLE         BIT(13) /* SDHI2 */
 526 #define HPB_DMAE_ASYNCMDR_ASMD27_MULTI          0       /* SDHI2 */
 527 #define HPB_DMAE_ASYNCMDR_ASBTMD27_MASK         BIT(12) /* SDHI2 */
 528 #define HPB_DMAE_ASYNCMDR_ASBTMD27_BURST        BIT(12) /* SDHI2 */
 529 #define HPB_DMAE_ASYNCMDR_ASBTMD27_NBURST       0       /* SDHI2 */
 530 #define HPB_DMAE_ASYNCMDR_ASMD26_MASK           BIT(11) /* SDHI2 */
 531 #define HPB_DMAE_ASYNCMDR_ASMD26_SINGLE         BIT(11) /* SDHI2 */
 532 #define HPB_DMAE_ASYNCMDR_ASMD26_MULTI          0       /* SDHI2 */
 533 #define HPB_DMAE_ASYNCMDR_ASBTMD26_MASK         BIT(10) /* SDHI2 */
 534 #define HPB_DMAE_ASYNCMDR_ASBTMD26_BURST        BIT(10) /* SDHI2 */
 535 #define HPB_DMAE_ASYNCMDR_ASBTMD26_NBURST       0       /* SDHI2 */
 536 #define HPB_DMAE_ASYNCMDR_ASMD25_MASK           BIT(9)  /* SDHI2 */
 537 #define HPB_DMAE_ASYNCMDR_ASMD25_SINGLE         BIT(9)  /* SDHI2 */
 538 #define HPB_DMAE_ASYNCMDR_ASMD25_MULTI          0       /* SDHI2 */
 539 #define HPB_DMAE_ASYNCMDR_ASBTMD25_MASK         BIT(8)  /* SDHI2 */
 540 #define HPB_DMAE_ASYNCMDR_ASBTMD25_BURST        BIT(8)  /* SDHI2 */
 541 #define HPB_DMAE_ASYNCMDR_ASBTMD25_NBURST       0       /* SDHI2 */
 542 #define HPB_DMAE_ASYNCMDR_ASMD23_MASK           BIT(7)  /* SDHI0 */
 543 #define HPB_DMAE_ASYNCMDR_ASMD23_SINGLE         BIT(7)  /* SDHI0 */
 544 #define HPB_DMAE_ASYNCMDR_ASMD23_MULTI          0       /* SDHI0 */
 545 #define HPB_DMAE_ASYNCMDR_ASBTMD23_MASK         BIT(6)  /* SDHI0 */
 546 #define HPB_DMAE_ASYNCMDR_ASBTMD23_BURST        BIT(6)  /* SDHI0 */
 547 #define HPB_DMAE_ASYNCMDR_ASBTMD23_NBURST       0       /* SDHI0 */
 548 #define HPB_DMAE_ASYNCMDR_ASMD22_MASK           BIT(5)  /* SDHI0 */
 549 #define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE         BIT(5)  /* SDHI0 */
 550 #define HPB_DMAE_ASYNCMDR_ASMD22_MULTI          0       /* SDHI0 */
 551 #define HPB_DMAE_ASYNCMDR_ASBTMD22_MASK         BIT(4)  /* SDHI0 */
 552 #define HPB_DMAE_ASYNCMDR_ASBTMD22_BURST        BIT(4)  /* SDHI0 */
 553 #define HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST       0       /* SDHI0 */
 554 #define HPB_DMAE_ASYNCMDR_ASMD21_MASK           BIT(3)  /* SDHI0 */
 555 #define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE         BIT(3)  /* SDHI0 */
 556 #define HPB_DMAE_ASYNCMDR_ASMD21_MULTI          0       /* SDHI0 */
 557 #define HPB_DMAE_ASYNCMDR_ASBTMD21_MASK         BIT(2)  /* SDHI0 */
 558 #define HPB_DMAE_ASYNCMDR_ASBTMD21_BURST        BIT(2)  /* SDHI0 */
 559 #define HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST       0       /* SDHI0 */
 560 #define HPB_DMAE_ASYNCMDR_ASMD20_MASK           BIT(1)  /* SDHI1 */
 561 #define HPB_DMAE_ASYNCMDR_ASMD20_SINGLE         BIT(1)  /* SDHI1 */
 562 #define HPB_DMAE_ASYNCMDR_ASMD20_MULTI          0       /* SDHI1 */
 563 #define HPB_DMAE_ASYNCMDR_ASBTMD20_MASK         BIT(0)  /* SDHI1 */
 564 #define HPB_DMAE_ASYNCMDR_ASBTMD20_BURST        BIT(0)  /* SDHI1 */
 565 #define HPB_DMAE_ASYNCMDR_ASBTMD20_NBURST       0       /* SDHI1 */
 566
 567 static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
 568         {
 569                 .id     = HPBDMA_SLAVE_SDHI0_TX,
 570                 .addr   = 0xffe4c000 + 0x30,
 571                 .dcr    = HPB_DMAE_DCR_SPDS_16BIT |
 572                           HPB_DMAE_DCR_DMDL |
 573                           HPB_DMAE_DCR_DPDS_16BIT,
 574                 .rstr   = HPB_DMAE_ASYNCRSTR_ASRST21 |
 575                           HPB_DMAE_ASYNCRSTR_ASRST22 |
 576                           HPB_DMAE_ASYNCRSTR_ASRST23,
 577                 .mdr    = HPB_DMAE_ASYNCMDR_ASMD21_SINGLE |
 578                           HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST,
 579                 .mdm    = HPB_DMAE_ASYNCMDR_ASMD21_MASK |
 580                           HPB_DMAE_ASYNCMDR_ASBTMD21_MASK,
 581                 .port   = 0x0D0C,
 582                 .flags  = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
 583                 .dma_ch = 21,
 584         }, {
 585                 .id     = HPBDMA_SLAVE_SDHI0_RX,
 586                 .addr   = 0xffe4c000 + 0x30,
 587                 .dcr    = HPB_DMAE_DCR_SMDL |
 588                           HPB_DMAE_DCR_SPDS_16BIT |
 589                           HPB_DMAE_DCR_DPDS_16BIT,
 590                 .rstr   = HPB_DMAE_ASYNCRSTR_ASRST21 |
 591                           HPB_DMAE_ASYNCRSTR_ASRST22 |
 592                           HPB_DMAE_ASYNCRSTR_ASRST23,
 593                 .mdr    = HPB_DMAE_ASYNCMDR_ASMD22_SINGLE |
 594                           HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST,
 595                 .mdm    = HPB_DMAE_ASYNCMDR_ASMD22_MASK |
 596                           HPB_DMAE_ASYNCMDR_ASBTMD22_MASK,
 597                 .port   = 0x0D0C,
 598                 .flags  = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
 599                 .dma_ch = 22,
 600         },
 601 };
 602
 603 static const struct hpb_dmae_channel hpb_dmae_channels[] = {
 604         HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */
 605         HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */
 606 };
 607
 608 static struct hpb_dmae_pdata dma_platform_data __initdata = {
 609         .slaves                 = hpb_dmae_slaves,
 610         .num_slaves             = ARRAY_SIZE(hpb_dmae_slaves),
 611         .channels               = hpb_dmae_channels,
 612         .num_channels           = ARRAY_SIZE(hpb_dmae_channels),
 613         .ts_shift               = {
 614                 [XMIT_SZ_8BIT]  = 0,
 615                 [XMIT_SZ_16BIT] = 1,
 616                 [XMIT_SZ_32BIT] = 2,
 617         },
 618         .num_hw_channels        = 44,
 619 };
 620
 621 static struct resource hpb_dmae_resources[] __initdata = {
 622         /* Channel registers */
 623         DEFINE_RES_MEM(0xffc08000, 0x1000),
 624         /* Common registers */
 625         DEFINE_RES_MEM(0xffc09000, 0x170),
 626         /* Asynchronous reset registers */
 627         DEFINE_RES_MEM(0xffc00300, 4),
 628         /* Asynchronous mode registers */
 629         DEFINE_RES_MEM(0xffc00400, 4),
 630         /* IRQ for DMA channels */
 631         DEFINE_RES_NAMED(gic_iid(0x8e), 12, NULL, IORESOURCE_IRQ),
 632 };
 633
 634 static void __init r8a7779_register_hpb_dmae(void)
 635 {
 636         platform_device_register_resndata(NULL, "hpb-dma-engine",
 637                                           -1, hpb_dmae_resources,
 638                                           ARRAY_SIZE(hpb_dmae_resources),
 639                                           &dma_platform_data,
 640                                           sizeof(dma_platform_data));
 641 }
 642
 643 static struct platform_device *r8a7779_early_devices[] __initdata = {
 644         &tmu0_device,
 645 };
 646
 647 static struct platform_device *r8a7779_standard_devices[] __initdata = {
 648         &scif0_device,
 649         &scif1_device,
 650         &scif2_device,
 651         &scif3_device,
 652         &scif4_device,
 653         &scif5_device,
 654         &i2c0_device,
 655         &i2c1_device,
 656         &i2c2_device,
 657         &i2c3_device,
 658         &sata_device,
 659 };
 660
 661 void __init r8a7779_add_standard_devices(void)
 662 {
 663 #ifdef CONFIG_CACHE_L2X0
 664         /* Shared attribute override enable, 64K*16way */
 665         l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff);
 666 #endif
 667         r8a7779_pm_init();
 668
 669         r8a7779_init_pm_domains();
 670
 671         platform_add_devices(r8a7779_early_devices,
 672                             ARRAY_SIZE(r8a7779_early_devices));
 673         platform_add_devices(r8a7779_standard_devices,
 674                             ARRAY_SIZE(r8a7779_standard_devices));
 675         r8a7779_register_hpb_dmae();
 676 }
 677
 678 void __init r8a7779_add_early_devices(void)
 679 {
 680         early_platform_add_devices(r8a7779_early_devices,
 681                                    ARRAY_SIZE(r8a7779_early_devices));
 682
 683         /* Early serial console setup is not included here due to
 684          * memory map collisions. The SCIF serial ports in r8a7779
 685          * are difficult to identity map 1:1 due to collision with the
 686          * virtual memory range used by the coherent DMA code on ARM.
 687          *
 688          * Anyone wanting to debug early can remove UPF_IOREMAP from
 689          * the sh-sci serial console platform data, adjust mapbase
 690          * to a static M:N virt:phys mapping that needs to be added to
 691          * the mappings passed with iotable_init() above.
 692          *
 693          * Then add a call to shmobile_setup_console() from this function.
 694          *
 695          * As a final step pass earlyprint=sh-sci.2,115200 on the kernel
 696          * command line in case of the marzen board.
 697          */
 698 }
 699
 700 static struct platform_device *r8a7779_late_devices[] __initdata = {
 701         &ehci0_device,
 702         &ehci1_device,
 703         &ohci0_device,
 704         &ohci1_device,
 705 };
 706
 707 void __init r8a7779_init_late(void)
 708 {
 709         /* get USB PHY */
 710         phy = usb_get_phy(USB_PHY_TYPE_USB2);
 711
 712         shmobile_init_late();
 713         platform_add_devices(r8a7779_late_devices,
 714                              ARRAY_SIZE(r8a7779_late_devices));
 715 }
 716
 717 #ifdef CONFIG_USE_OF
 718 void __init r8a7779_init_irq_dt(void)
 719 {
 720 #ifdef CONFIG_ARCH_SHMOBILE_LEGACY
 721         void __iomem *gic_dist_base = ioremap_nocache(0xf0001000, 0x1000);
 722         void __iomem *gic_cpu_base = ioremap_nocache(0xf0000100, 0x1000);
 723 #endif
 724         gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE);
 725
 726 #ifdef CONFIG_ARCH_SHMOBILE_LEGACY
 727         gic_init(0, 29, gic_dist_base, gic_cpu_base);
 728 #else
 729         irqchip_init();
 730 #endif
 731         /* route all interrupts to ARM */
 732         __raw_writel(0xffffffff, INT2NTSR0);
 733         __raw_writel(0x3fffffff, INT2NTSR1);
 734
 735         /* unmask all known interrupts in INTCS2 */
 736         __raw_writel(0xfffffff0, INT2SMSKCR0);
 737         __raw_writel(0xfff7ffff, INT2SMSKCR1);
 738         __raw_writel(0xfffbffdf, INT2SMSKCR2);
 739         __raw_writel(0xbffffffc, INT2SMSKCR3);
 740         __raw_writel(0x003fee3f, INT2SMSKCR4);
 741 }
 742
 743 #define MODEMR          0xffcc0020
 744
 745 u32 __init r8a7779_read_mode_pins(void)
 746 {
 747         static u32 mode;
 748         static bool mode_valid;
 749
 750         if (!mode_valid) {
 751                 void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
 752                 BUG_ON(!modemr);
 753                 mode = ioread32(modemr);
 754                 iounmap(modemr);
 755                 mode_valid = true;
 756         }
 757
 758         return mode;
 759 }
 760
 761 #ifdef CONFIG_ARCH_SHMOBILE_MULTI
 762
 763 static void __init r8a7779_init_time(void)
 764 {
 765         r8a7779_clocks_init(r8a7779_read_mode_pins());
 766         clocksource_of_init();
 767 }
 768
 769 static const char *r8a7779_compat_dt[] __initdata = {
 770         "renesas,r8a7779",
 771         NULL,
 772 };
 773
 774 DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
 775         .smp            = smp_ops(r8a7779_smp_ops),
 776         .map_io         = r8a7779_map_io,
 777         .init_early     = shmobile_init_delay,
 778         .init_time      = r8a7779_init_time,
 779         .init_irq       = r8a7779_init_irq_dt,
 780         .init_late      = shmobile_init_late,
 781         .dt_compat      = r8a7779_compat_dt,
 782 MACHINE_END
 783 #endif /* CONFIG_ARCH_SHMOBILE_MULTI */
 784 #endif /* CONFIG_USE_OF */