arch/arm/mach-shmobile/setup-rcar-gen2.c

   1 /*
   2  * R-Car Generation 2 support
   3  *
   4  * Copyright (C) 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2013  Magnus Damm
   6  * Copyright (C) 2014  Ulrich Hecht
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/clk/renesas.h>
  19 #include <linux/clocksource.h>
  20 #include <linux/device.h>
  21 #include <linux/dma-contiguous.h>
  22 #include <linux/io.h>
  23 #include <linux/kernel.h>
  24 #include <linux/memblock.h>
  25 #include <linux/of.h>
  26 #include <linux/of_fdt.h>
  27 #include <asm/mach/arch.h>
  28 #include "common.h"
  29 #include "rcar-gen2.h"
  30
  31 #define MODEMR 0xe6160060
  32
  33 u32 rcar_gen2_read_mode_pins(void)
  34 {
  35         static u32 mode;
  36         static bool mode_valid;
  37
  38         if (!mode_valid) {
  39                 void __iomem *modemr = ioremap_nocache(MODEMR, 4);
  40                 BUG_ON(!modemr);
  41                 mode = ioread32(modemr);
  42                 iounmap(modemr);
  43                 mode_valid = true;
  44         }
  45
  46         return mode;
  47 }
  48
  49 static unsigned int __init get_extal_freq(void)
  50 {
  51         struct device_node *cpg, *extal;
  52         u32 freq = 20000000;
  53
  54         cpg = of_find_compatible_node(NULL, NULL,
  55                                       "renesas,rcar-gen2-cpg-clocks");
  56         if (!cpg)
  57                 return freq;
  58
  59         extal = of_parse_phandle(cpg, "clocks", 0);
  60         of_node_put(cpg);
  61         if (!extal)
  62                 return freq;
  63
  64         of_property_read_u32(extal, "clock-frequency", &freq);
  65         of_node_put(extal);
  66         return freq;
  67 }
  68
  69 #define CNTCR 0
  70 #define CNTFID0 0x20
  71
  72 void __init rcar_gen2_timer_init(void)
  73 {
  74         u32 mode = rcar_gen2_read_mode_pins();
  75 #ifdef CONFIG_ARM_ARCH_TIMER
  76         void __iomem *base;
  77         u32 freq;
  78
  79         if (of_machine_is_compatible("renesas,r8a7792") ||
  80             of_machine_is_compatible("renesas,r8a7794")) {
  81                 freq = 260000000 / 8;   /* ZS / 8 */
  82                 /* CNTVOFF has to be initialized either from non-secure
  83                  * Hypervisor mode or secure Monitor mode with SCR.NS==1.
  84                  * If TrustZone is enabled then it should be handled by the
  85                  * secure code.
  86                  */
  87                 asm volatile(
  88                 "       cps     0x16\n"
  89                 "       mrc     p15, 0, r1, c1, c1, 0\n"
  90                 "       orr     r0, r1, #1\n"
  91                 "       mcr     p15, 0, r0, c1, c1, 0\n"
  92                 "       isb\n"
  93                 "       mov     r0, #0\n"
  94                 "       mcrr    p15, 4, r0, r0, c14\n"
  95                 "       isb\n"
  96                 "       mcr     p15, 0, r1, c1, c1, 0\n"
  97                 "       isb\n"
  98                 "       cps     0x13\n"
  99                         : : : "r0", "r1");
 100         } else {
 101                 /* At Linux boot time the r8a7790 arch timer comes up
 102                  * with the counter disabled. Moreover, it may also report
 103                  * a potentially incorrect fixed 13 MHz frequency. To be
 104                  * correct these registers need to be updated to use the
 105                  * frequency EXTAL / 2.
 106                  */
 107                 freq = get_extal_freq() / 2;
 108         }
 109
 110         /* Remap "armgcnt address map" space */
 111         base = ioremap(0xe6080000, PAGE_SIZE);
 112
 113         /*
 114          * Update the timer if it is either not running, or is not at the
 115          * right frequency. The timer is only configurable in secure mode
 116          * so this avoids an abort if the loader started the timer and
 117          * entered the kernel in non-secure mode.
 118          */
 119
 120         if ((ioread32(base + CNTCR) & 1) == 0 ||
 121             ioread32(base + CNTFID0) != freq) {
 122                 /* Update registers with correct frequency */
 123                 iowrite32(freq, base + CNTFID0);
 124                 asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
 125
 126                 /* make sure arch timer is started by setting bit 0 of CNTCR */
 127                 iowrite32(1, base + CNTCR);
 128         }
 129
 130         iounmap(base);
 131 #endif /* CONFIG_ARM_ARCH_TIMER */
 132
 133         rcar_gen2_clocks_init(mode);
 134         clocksource_probe();
 135 }
 136
 137 struct memory_reserve_config {
 138         u64 reserved;
 139         u64 base, size;
 140 };
 141
 142 static int __init rcar_gen2_scan_mem(unsigned long node, const char *uname,
 143                                      int depth, void *data)
 144 {
 145         const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
 146         const __be32 *reg, *endp;
 147         int l;
 148         struct memory_reserve_config *mrc = data;
 149         u64 lpae_start = 1ULL << 32;
 150
 151         /* We are scanning "memory" nodes only */
 152         if (type == NULL || strcmp(type, "memory"))
 153                 return 0;
 154
 155         reg = of_get_flat_dt_prop(node, "linux,usable-memory", &l);
 156         if (reg == NULL)
 157                 reg = of_get_flat_dt_prop(node, "reg", &l);
 158         if (reg == NULL)
 159                 return 0;
 160
 161         endp = reg + (l / sizeof(__be32));
 162         while ((endp - reg) >= (dt_root_addr_cells + dt_root_size_cells)) {
 163                 u64 base, size;
 164
 165                 base = dt_mem_next_cell(dt_root_addr_cells, &reg);
 166                 size = dt_mem_next_cell(dt_root_size_cells, &reg);
 167
 168                 if (base >= lpae_start)
 169                         continue;
 170
 171                 if ((base + size) >= lpae_start)
 172                         size = lpae_start - base;
 173
 174                 if (size < mrc->reserved)
 175                         continue;
 176
 177                 if (base < mrc->base)
 178                         continue;
 179
 180                 /* keep the area at top near the 32-bit legacy limit */
 181                 mrc->base = base + size - mrc->reserved;
 182                 mrc->size = mrc->reserved;
 183         }
 184
 185         return 0;
 186 }
 187
 188 void __init rcar_gen2_reserve(void)
 189 {
 190         struct memory_reserve_config mrc;
 191
 192         /* reserve 256 MiB at the top of the physical legacy 32-bit space */
 193         memset(&mrc, 0, sizeof(mrc));
 194         mrc.reserved = SZ_256M;
 195
 196         of_scan_flat_dt(rcar_gen2_scan_mem, &mrc);
 197 #ifdef CONFIG_DMA_CMA
 198         if (mrc.size && memblock_is_region_memory(mrc.base, mrc.size)) {
 199                 static struct cma *rcar_gen2_dma_contiguous;
 200
 201                 dma_contiguous_reserve_area(mrc.size, mrc.base, 0,
 202                                             &rcar_gen2_dma_contiguous, true);
 203         }
 204 #endif
 205 }