arch/arm/mach-shmobile/setup-sh7372.c

   1 /*
   2  * sh7372 processor support
   3  *
   4  * Copyright (C) 2010  Magnus Damm
   5  * Copyright (C) 2008  Yoshihiro Shimoda
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/irq.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/uio_driver.h>
  26 #include <linux/delay.h>
  27 #include <linux/input.h>
  28 #include <linux/io.h>
  29 #include <linux/serial_sci.h>
  30 #include <linux/sh_dma.h>
  31 #include <linux/sh_intc.h>
  32 #include <linux/sh_timer.h>
  33 #include <linux/pm_domain.h>
  34 #include <linux/dma-mapping.h>
  35 #include <mach/hardware.h>
  36 #include <mach/sh7372.h>
  37 #include <mach/common.h>
  38 #include <asm/mach/map.h>
  39 #include <asm/mach-types.h>
  40 #include <asm/mach/arch.h>
  41 #include <asm/mach/time.h>
  42
  43 static struct map_desc sh7372_io_desc[] __initdata = {
  44         /* create a 1:1 entity map for 0xe6xxxxxx
  45          * used by CPGA, INTC and PFC.
  46          */
  47         {
  48                 .virtual        = 0xe6000000,
  49                 .pfn            = __phys_to_pfn(0xe6000000),
  50                 .length         = 256 << 20,
  51                 .type           = MT_DEVICE_NONSHARED
  52         },
  53 };
  54
  55 void __init sh7372_map_io(void)
  56 {
  57         iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
  58
  59         /*
  60          * DMA memory at 0xff200000 - 0xffdfffff. The default 2MB size isn't
  61          * enough to allocate the frame buffer memory.
  62          */
  63         init_consistent_dma_size(12 << 20);
  64 }
  65
  66 /* SCIFA0 */
  67 static struct plat_sci_port scif0_platform_data = {
  68         .mapbase        = 0xe6c40000,
  69         .flags          = UPF_BOOT_AUTOCONF,
  70         .scscr          = SCSCR_RE | SCSCR_TE,
  71         .scbrr_algo_id  = SCBRR_ALGO_4,
  72         .type           = PORT_SCIFA,
  73         .irqs           = { evt2irq(0x0c00), evt2irq(0x0c00),
  74                             evt2irq(0x0c00), evt2irq(0x0c00) },
  75 };
  76
  77 static struct platform_device scif0_device = {
  78         .name           = "sh-sci",
  79         .id             = 0,
  80         .dev            = {
  81                 .platform_data  = &scif0_platform_data,
  82         },
  83 };
  84
  85 /* SCIFA1 */
  86 static struct plat_sci_port scif1_platform_data = {
  87         .mapbase        = 0xe6c50000,
  88         .flags          = UPF_BOOT_AUTOCONF,
  89         .scscr          = SCSCR_RE | SCSCR_TE,
  90         .scbrr_algo_id  = SCBRR_ALGO_4,
  91         .type           = PORT_SCIFA,
  92         .irqs           = { evt2irq(0x0c20), evt2irq(0x0c20),
  93                             evt2irq(0x0c20), evt2irq(0x0c20) },
  94 };
  95
  96 static struct platform_device scif1_device = {
  97         .name           = "sh-sci",
  98         .id             = 1,
  99         .dev            = {
 100                 .platform_data  = &scif1_platform_data,
 101         },
 102 };
 103
 104 /* SCIFA2 */
 105 static struct plat_sci_port scif2_platform_data = {
 106         .mapbase        = 0xe6c60000,
 107         .flags          = UPF_BOOT_AUTOCONF,
 108         .scscr          = SCSCR_RE | SCSCR_TE,
 109         .scbrr_algo_id  = SCBRR_ALGO_4,
 110         .type           = PORT_SCIFA,
 111         .irqs           = { evt2irq(0x0c40), evt2irq(0x0c40),
 112                             evt2irq(0x0c40), evt2irq(0x0c40) },
 113 };
 114
 115 static struct platform_device scif2_device = {
 116         .name           = "sh-sci",
 117         .id             = 2,
 118         .dev            = {
 119                 .platform_data  = &scif2_platform_data,
 120         },
 121 };
 122
 123 /* SCIFA3 */
 124 static struct plat_sci_port scif3_platform_data = {
 125         .mapbase        = 0xe6c70000,
 126         .flags          = UPF_BOOT_AUTOCONF,
 127         .scscr          = SCSCR_RE | SCSCR_TE,
 128         .scbrr_algo_id  = SCBRR_ALGO_4,
 129         .type           = PORT_SCIFA,
 130         .irqs           = { evt2irq(0x0c60), evt2irq(0x0c60),
 131                             evt2irq(0x0c60), evt2irq(0x0c60) },
 132 };
 133
 134 static struct platform_device scif3_device = {
 135         .name           = "sh-sci",
 136         .id             = 3,
 137         .dev            = {
 138                 .platform_data  = &scif3_platform_data,
 139         },
 140 };
 141
 142 /* SCIFA4 */
 143 static struct plat_sci_port scif4_platform_data = {
 144         .mapbase        = 0xe6c80000,
 145         .flags          = UPF_BOOT_AUTOCONF,
 146         .scscr          = SCSCR_RE | SCSCR_TE,
 147         .scbrr_algo_id  = SCBRR_ALGO_4,
 148         .type           = PORT_SCIFA,
 149         .irqs           = { evt2irq(0x0d20), evt2irq(0x0d20),
 150                             evt2irq(0x0d20), evt2irq(0x0d20) },
 151 };
 152
 153 static struct platform_device scif4_device = {
 154         .name           = "sh-sci",
 155         .id             = 4,
 156         .dev            = {
 157                 .platform_data  = &scif4_platform_data,
 158         },
 159 };
 160
 161 /* SCIFA5 */
 162 static struct plat_sci_port scif5_platform_data = {
 163         .mapbase        = 0xe6cb0000,
 164         .flags          = UPF_BOOT_AUTOCONF,
 165         .scscr          = SCSCR_RE | SCSCR_TE,
 166         .scbrr_algo_id  = SCBRR_ALGO_4,
 167         .type           = PORT_SCIFA,
 168         .irqs           = { evt2irq(0x0d40), evt2irq(0x0d40),
 169                             evt2irq(0x0d40), evt2irq(0x0d40) },
 170 };
 171
 172 static struct platform_device scif5_device = {
 173         .name           = "sh-sci",
 174         .id             = 5,
 175         .dev            = {
 176                 .platform_data  = &scif5_platform_data,
 177         },
 178 };
 179
 180 /* SCIFB */
 181 static struct plat_sci_port scif6_platform_data = {
 182         .mapbase        = 0xe6c30000,
 183         .flags          = UPF_BOOT_AUTOCONF,
 184         .scscr          = SCSCR_RE | SCSCR_TE,
 185         .scbrr_algo_id  = SCBRR_ALGO_4,
 186         .type           = PORT_SCIFB,
 187         .irqs           = { evt2irq(0x0d60), evt2irq(0x0d60),
 188                             evt2irq(0x0d60), evt2irq(0x0d60) },
 189 };
 190
 191 static struct platform_device scif6_device = {
 192         .name           = "sh-sci",
 193         .id             = 6,
 194         .dev            = {
 195                 .platform_data  = &scif6_platform_data,
 196         },
 197 };
 198
 199 /* CMT */
 200 static struct sh_timer_config cmt2_platform_data = {
 201         .name = "CMT2",
 202         .channel_offset = 0x40,
 203         .timer_bit = 5,
 204         .clockevent_rating = 125,
 205         .clocksource_rating = 125,
 206 };
 207
 208 static struct resource cmt2_resources[] = {
 209         [0] = {
 210                 .name   = "CMT2",
 211                 .start  = 0xe6130040,
 212                 .end    = 0xe613004b,
 213                 .flags  = IORESOURCE_MEM,
 214         },
 215         [1] = {
 216                 .start  = evt2irq(0x0b80), /* CMT2 */
 217                 .flags  = IORESOURCE_IRQ,
 218         },
 219 };
 220
 221 static struct platform_device cmt2_device = {
 222         .name           = "sh_cmt",
 223         .id             = 2,
 224         .dev = {
 225                 .platform_data  = &cmt2_platform_data,
 226         },
 227         .resource       = cmt2_resources,
 228         .num_resources  = ARRAY_SIZE(cmt2_resources),
 229 };
 230
 231 /* TMU */
 232 static struct sh_timer_config tmu00_platform_data = {
 233         .name = "TMU00",
 234         .channel_offset = 0x4,
 235         .timer_bit = 0,
 236         .clockevent_rating = 200,
 237 };
 238
 239 static struct resource tmu00_resources[] = {
 240         [0] = {
 241                 .name   = "TMU00",
 242                 .start  = 0xfff60008,
 243                 .end    = 0xfff60013,
 244                 .flags  = IORESOURCE_MEM,
 245         },
 246         [1] = {
 247                 .start  = intcs_evt2irq(0xe80), /* TMU_TUNI0 */
 248                 .flags  = IORESOURCE_IRQ,
 249         },
 250 };
 251
 252 static struct platform_device tmu00_device = {
 253         .name           = "sh_tmu",
 254         .id             = 0,
 255         .dev = {
 256                 .platform_data  = &tmu00_platform_data,
 257         },
 258         .resource       = tmu00_resources,
 259         .num_resources  = ARRAY_SIZE(tmu00_resources),
 260 };
 261
 262 static struct sh_timer_config tmu01_platform_data = {
 263         .name = "TMU01",
 264         .channel_offset = 0x10,
 265         .timer_bit = 1,
 266         .clocksource_rating = 200,
 267 };
 268
 269 static struct resource tmu01_resources[] = {
 270         [0] = {
 271                 .name   = "TMU01",
 272                 .start  = 0xfff60014,
 273                 .end    = 0xfff6001f,
 274                 .flags  = IORESOURCE_MEM,
 275         },
 276         [1] = {
 277                 .start  = intcs_evt2irq(0xea0), /* TMU_TUNI1 */
 278                 .flags  = IORESOURCE_IRQ,
 279         },
 280 };
 281
 282 static struct platform_device tmu01_device = {
 283         .name           = "sh_tmu",
 284         .id             = 1,
 285         .dev = {
 286                 .platform_data  = &tmu01_platform_data,
 287         },
 288         .resource       = tmu01_resources,
 289         .num_resources  = ARRAY_SIZE(tmu01_resources),
 290 };
 291
 292 /* I2C */
 293 static struct resource iic0_resources[] = {
 294         [0] = {
 295                 .name   = "IIC0",
 296                 .start  = 0xFFF20000,
 297                 .end    = 0xFFF20425 - 1,
 298                 .flags  = IORESOURCE_MEM,
 299         },
 300         [1] = {
 301                 .start  = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
 302                 .end    = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
 303                 .flags  = IORESOURCE_IRQ,
 304         },
 305 };
 306
 307 static struct platform_device iic0_device = {
 308         .name           = "i2c-sh_mobile",
 309         .id             = 0, /* "i2c0" clock */
 310         .num_resources  = ARRAY_SIZE(iic0_resources),
 311         .resource       = iic0_resources,
 312 };
 313
 314 static struct resource iic1_resources[] = {
 315         [0] = {
 316                 .name   = "IIC1",
 317                 .start  = 0xE6C20000,
 318                 .end    = 0xE6C20425 - 1,
 319                 .flags  = IORESOURCE_MEM,
 320         },
 321         [1] = {
 322                 .start  = evt2irq(0x780), /* IIC1_ALI1 */
 323                 .end    = evt2irq(0x7e0), /* IIC1_DTEI1 */
 324                 .flags  = IORESOURCE_IRQ,
 325         },
 326 };
 327
 328 static struct platform_device iic1_device = {
 329         .name           = "i2c-sh_mobile",
 330         .id             = 1, /* "i2c1" clock */
 331         .num_resources  = ARRAY_SIZE(iic1_resources),
 332         .resource       = iic1_resources,
 333 };
 334
 335 /* DMA */
 336 /* Transmit sizes and respective CHCR register values */
 337 enum {
 338         XMIT_SZ_8BIT            = 0,
 339         XMIT_SZ_16BIT           = 1,
 340         XMIT_SZ_32BIT           = 2,
 341         XMIT_SZ_64BIT           = 7,
 342         XMIT_SZ_128BIT          = 3,
 343         XMIT_SZ_256BIT          = 4,
 344         XMIT_SZ_512BIT          = 5,
 345 };
 346
 347 /* log2(size / 8) - used to calculate number of transfers */
 348 #define TS_SHIFT {                      \
 349         [XMIT_SZ_8BIT]          = 0,    \
 350         [XMIT_SZ_16BIT]         = 1,    \
 351         [XMIT_SZ_32BIT]         = 2,    \
 352         [XMIT_SZ_64BIT]         = 3,    \
 353         [XMIT_SZ_128BIT]        = 4,    \
 354         [XMIT_SZ_256BIT]        = 5,    \
 355         [XMIT_SZ_512BIT]        = 6,    \
 356 }
 357
 358 #define TS_INDEX2VAL(i) ((((i) & 3) << 3) | \
 359                          (((i) & 0xc) << (20 - 2)))
 360
 361 static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
 362         {
 363                 .slave_id       = SHDMA_SLAVE_SCIF0_TX,
 364                 .addr           = 0xe6c40020,
 365                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 366                 .mid_rid        = 0x21,
 367         }, {
 368                 .slave_id       = SHDMA_SLAVE_SCIF0_RX,
 369                 .addr           = 0xe6c40024,
 370                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 371                 .mid_rid        = 0x22,
 372         }, {
 373                 .slave_id       = SHDMA_SLAVE_SCIF1_TX,
 374                 .addr           = 0xe6c50020,
 375                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 376                 .mid_rid        = 0x25,
 377         }, {
 378                 .slave_id       = SHDMA_SLAVE_SCIF1_RX,
 379                 .addr           = 0xe6c50024,
 380                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 381                 .mid_rid        = 0x26,
 382         }, {
 383                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
 384                 .addr           = 0xe6c60020,
 385                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 386                 .mid_rid        = 0x29,
 387         }, {
 388                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
 389                 .addr           = 0xe6c60024,
 390                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 391                 .mid_rid        = 0x2a,
 392         }, {
 393                 .slave_id       = SHDMA_SLAVE_SCIF3_TX,
 394                 .addr           = 0xe6c70020,
 395                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 396                 .mid_rid        = 0x2d,
 397         }, {
 398                 .slave_id       = SHDMA_SLAVE_SCIF3_RX,
 399                 .addr           = 0xe6c70024,
 400                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 401                 .mid_rid        = 0x2e,
 402         }, {
 403                 .slave_id       = SHDMA_SLAVE_SCIF4_TX,
 404                 .addr           = 0xe6c80020,
 405                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 406                 .mid_rid        = 0x39,
 407         }, {
 408                 .slave_id       = SHDMA_SLAVE_SCIF4_RX,
 409                 .addr           = 0xe6c80024,
 410                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 411                 .mid_rid        = 0x3a,
 412         }, {
 413                 .slave_id       = SHDMA_SLAVE_SCIF5_TX,
 414                 .addr           = 0xe6cb0020,
 415                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 416                 .mid_rid        = 0x35,
 417         }, {
 418                 .slave_id       = SHDMA_SLAVE_SCIF5_RX,
 419                 .addr           = 0xe6cb0024,
 420                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 421                 .mid_rid        = 0x36,
 422         }, {
 423                 .slave_id       = SHDMA_SLAVE_SCIF6_TX,
 424                 .addr           = 0xe6c30040,
 425                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 426                 .mid_rid        = 0x3d,
 427         }, {
 428                 .slave_id       = SHDMA_SLAVE_SCIF6_RX,
 429                 .addr           = 0xe6c30060,
 430                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 431                 .mid_rid        = 0x3e,
 432         }, {
 433                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 434                 .addr           = 0xe6850030,
 435                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 436                 .mid_rid        = 0xc1,
 437         }, {
 438                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 439                 .addr           = 0xe6850030,
 440                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 441                 .mid_rid        = 0xc2,
 442         }, {
 443                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 444                 .addr           = 0xe6860030,
 445                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 446                 .mid_rid        = 0xc9,
 447         }, {
 448                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 449                 .addr           = 0xe6860030,
 450                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 451                 .mid_rid        = 0xca,
 452         }, {
 453                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
 454                 .addr           = 0xe6870030,
 455                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 456                 .mid_rid        = 0xcd,
 457         }, {
 458                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
 459                 .addr           = 0xe6870030,
 460                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 461                 .mid_rid        = 0xce,
 462         }, {
 463                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
 464                 .addr           = 0xe6bd0034,
 465                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
 466                 .mid_rid        = 0xd1,
 467         }, {
 468                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
 469                 .addr           = 0xe6bd0034,
 470                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
 471                 .mid_rid        = 0xd2,
 472         },
 473 };
 474
 475 #define SH7372_CHCLR 0x220
 476
 477 static const struct sh_dmae_channel sh7372_dmae_channels[] = {
 478         {
 479                 .offset = 0,
 480                 .dmars = 0,
 481                 .dmars_bit = 0,
 482                 .chclr_offset = SH7372_CHCLR + 0,
 483         }, {
 484                 .offset = 0x10,
 485                 .dmars = 0,
 486                 .dmars_bit = 8,
 487                 .chclr_offset = SH7372_CHCLR + 0x10,
 488         }, {
 489                 .offset = 0x20,
 490                 .dmars = 4,
 491                 .dmars_bit = 0,
 492                 .chclr_offset = SH7372_CHCLR + 0x20,
 493         }, {
 494                 .offset = 0x30,
 495                 .dmars = 4,
 496                 .dmars_bit = 8,
 497                 .chclr_offset = SH7372_CHCLR + 0x30,
 498         }, {
 499                 .offset = 0x50,
 500                 .dmars = 8,
 501                 .dmars_bit = 0,
 502                 .chclr_offset = SH7372_CHCLR + 0x50,
 503         }, {
 504                 .offset = 0x60,
 505                 .dmars = 8,
 506                 .dmars_bit = 8,
 507                 .chclr_offset = SH7372_CHCLR + 0x60,
 508         }
 509 };
 510
 511 static const unsigned int ts_shift[] = TS_SHIFT;
 512
 513 static struct sh_dmae_pdata dma_platform_data = {
 514         .slave          = sh7372_dmae_slaves,
 515         .slave_num      = ARRAY_SIZE(sh7372_dmae_slaves),
 516         .channel        = sh7372_dmae_channels,
 517         .channel_num    = ARRAY_SIZE(sh7372_dmae_channels),
 518         .ts_low_shift   = 3,
 519         .ts_low_mask    = 0x18,
 520         .ts_high_shift  = (20 - 2),     /* 2 bits for shifted low TS */
 521         .ts_high_mask   = 0x00300000,
 522         .ts_shift       = ts_shift,
 523         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 524         .dmaor_init     = DMAOR_DME,
 525         .chclr_present  = 1,
 526 };
 527
 528 /* Resource order important! */
 529 static struct resource sh7372_dmae0_resources[] = {
 530         {
 531                 /* Channel registers and DMAOR */
 532                 .start  = 0xfe008020,
 533                 .end    = 0xfe00828f,
 534                 .flags  = IORESOURCE_MEM,
 535         },
 536         {
 537                 /* DMARSx */
 538                 .start  = 0xfe009000,
 539                 .end    = 0xfe00900b,
 540                 .flags  = IORESOURCE_MEM,
 541         },
 542         {
 543                 .name   = "error_irq",
 544                 .start  = evt2irq(0x20c0),
 545                 .end    = evt2irq(0x20c0),
 546                 .flags  = IORESOURCE_IRQ,
 547         },
 548         {
 549                 /* IRQ for channels 0-5 */
 550                 .start  = evt2irq(0x2000),
 551                 .end    = evt2irq(0x20a0),
 552                 .flags  = IORESOURCE_IRQ,
 553         },
 554 };
 555
 556 /* Resource order important! */
 557 static struct resource sh7372_dmae1_resources[] = {
 558         {
 559                 /* Channel registers and DMAOR */
 560                 .start  = 0xfe018020,
 561                 .end    = 0xfe01828f,
 562                 .flags  = IORESOURCE_MEM,
 563         },
 564         {
 565                 /* DMARSx */
 566                 .start  = 0xfe019000,
 567                 .end    = 0xfe01900b,
 568                 .flags  = IORESOURCE_MEM,
 569         },
 570         {
 571                 .name   = "error_irq",
 572                 .start  = evt2irq(0x21c0),
 573                 .end    = evt2irq(0x21c0),
 574                 .flags  = IORESOURCE_IRQ,
 575         },
 576         {
 577                 /* IRQ for channels 0-5 */
 578                 .start  = evt2irq(0x2100),
 579                 .end    = evt2irq(0x21a0),
 580                 .flags  = IORESOURCE_IRQ,
 581         },
 582 };
 583
 584 /* Resource order important! */
 585 static struct resource sh7372_dmae2_resources[] = {
 586         {
 587                 /* Channel registers and DMAOR */
 588                 .start  = 0xfe028020,
 589                 .end    = 0xfe02828f,
 590                 .flags  = IORESOURCE_MEM,
 591         },
 592         {
 593                 /* DMARSx */
 594                 .start  = 0xfe029000,
 595                 .end    = 0xfe02900b,
 596                 .flags  = IORESOURCE_MEM,
 597         },
 598         {
 599                 .name   = "error_irq",
 600                 .start  = evt2irq(0x22c0),
 601                 .end    = evt2irq(0x22c0),
 602                 .flags  = IORESOURCE_IRQ,
 603         },
 604         {
 605                 /* IRQ for channels 0-5 */
 606                 .start  = evt2irq(0x2200),
 607                 .end    = evt2irq(0x22a0),
 608                 .flags  = IORESOURCE_IRQ,
 609         },
 610 };
 611
 612 static struct platform_device dma0_device = {
 613         .name           = "sh-dma-engine",
 614         .id             = 0,
 615         .resource       = sh7372_dmae0_resources,
 616         .num_resources  = ARRAY_SIZE(sh7372_dmae0_resources),
 617         .dev            = {
 618                 .platform_data  = &dma_platform_data,
 619         },
 620 };
 621
 622 static struct platform_device dma1_device = {
 623         .name           = "sh-dma-engine",
 624         .id             = 1,
 625         .resource       = sh7372_dmae1_resources,
 626         .num_resources  = ARRAY_SIZE(sh7372_dmae1_resources),
 627         .dev            = {
 628                 .platform_data  = &dma_platform_data,
 629         },
 630 };
 631
 632 static struct platform_device dma2_device = {
 633         .name           = "sh-dma-engine",
 634         .id             = 2,
 635         .resource       = sh7372_dmae2_resources,
 636         .num_resources  = ARRAY_SIZE(sh7372_dmae2_resources),
 637         .dev            = {
 638                 .platform_data  = &dma_platform_data,
 639         },
 640 };
 641
 642 /*
 643  * USB-DMAC
 644  */
 645
 646 unsigned int usbts_shift[] = {3, 4, 5};
 647
 648 enum {
 649         XMIT_SZ_8BYTE           = 0,
 650         XMIT_SZ_16BYTE          = 1,
 651         XMIT_SZ_32BYTE          = 2,
 652 };
 653
 654 #define USBTS_INDEX2VAL(i) (((i) & 3) << 6)
 655
 656 static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
 657         {
 658                 .offset = 0,
 659         }, {
 660                 .offset = 0x20,
 661         },
 662 };
 663
 664 /* USB DMAC0 */
 665 static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
 666         {
 667                 .slave_id       = SHDMA_SLAVE_USB0_TX,
 668                 .chcr           = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
 669         }, {
 670                 .slave_id       = SHDMA_SLAVE_USB0_RX,
 671                 .chcr           = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
 672         },
 673 };
 674
 675 static struct sh_dmae_pdata usb_dma0_platform_data = {
 676         .slave          = sh7372_usb_dmae0_slaves,
 677         .slave_num      = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
 678         .channel        = sh7372_usb_dmae_channels,
 679         .channel_num    = ARRAY_SIZE(sh7372_usb_dmae_channels),
 680         .ts_low_shift   = 6,
 681         .ts_low_mask    = 0xc0,
 682         .ts_high_shift  = 0,
 683         .ts_high_mask   = 0,
 684         .ts_shift       = usbts_shift,
 685         .ts_shift_num   = ARRAY_SIZE(usbts_shift),
 686         .dmaor_init     = DMAOR_DME,
 687         .chcr_offset    = 0x14,
 688         .chcr_ie_bit    = 1 << 5,
 689         .dmaor_is_32bit = 1,
 690         .needs_tend_set = 1,
 691         .no_dmars       = 1,
 692         .slave_only     = 1,
 693 };
 694
 695 static struct resource sh7372_usb_dmae0_resources[] = {
 696         {
 697                 /* Channel registers and DMAOR */
 698                 .start  = 0xe68a0020,
 699                 .end    = 0xe68a0064 - 1,
 700                 .flags  = IORESOURCE_MEM,
 701         },
 702         {
 703                 /* VCR/SWR/DMICR */
 704                 .start  = 0xe68a0000,
 705                 .end    = 0xe68a0014 - 1,
 706                 .flags  = IORESOURCE_MEM,
 707         },
 708         {
 709                 /* IRQ for channels */
 710                 .start  = evt2irq(0x0a00),
 711                 .end    = evt2irq(0x0a00),
 712                 .flags  = IORESOURCE_IRQ,
 713         },
 714 };
 715
 716 static struct platform_device usb_dma0_device = {
 717         .name           = "sh-dma-engine",
 718         .id             = 3,
 719         .resource       = sh7372_usb_dmae0_resources,
 720         .num_resources  = ARRAY_SIZE(sh7372_usb_dmae0_resources),
 721         .dev            = {
 722                 .platform_data  = &usb_dma0_platform_data,
 723         },
 724 };
 725
 726 /* USB DMAC1 */
 727 static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
 728         {
 729                 .slave_id       = SHDMA_SLAVE_USB1_TX,
 730                 .chcr           = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
 731         }, {
 732                 .slave_id       = SHDMA_SLAVE_USB1_RX,
 733                 .chcr           = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
 734         },
 735 };
 736
 737 static struct sh_dmae_pdata usb_dma1_platform_data = {
 738         .slave          = sh7372_usb_dmae1_slaves,
 739         .slave_num      = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
 740         .channel        = sh7372_usb_dmae_channels,
 741         .channel_num    = ARRAY_SIZE(sh7372_usb_dmae_channels),
 742         .ts_low_shift   = 6,
 743         .ts_low_mask    = 0xc0,
 744         .ts_high_shift  = 0,
 745         .ts_high_mask   = 0,
 746         .ts_shift       = usbts_shift,
 747         .ts_shift_num   = ARRAY_SIZE(usbts_shift),
 748         .dmaor_init     = DMAOR_DME,
 749         .chcr_offset    = 0x14,
 750         .chcr_ie_bit    = 1 << 5,
 751         .dmaor_is_32bit = 1,
 752         .needs_tend_set = 1,
 753         .no_dmars       = 1,
 754         .slave_only     = 1,
 755 };
 756
 757 static struct resource sh7372_usb_dmae1_resources[] = {
 758         {
 759                 /* Channel registers and DMAOR */
 760                 .start  = 0xe68c0020,
 761                 .end    = 0xe68c0064 - 1,
 762                 .flags  = IORESOURCE_MEM,
 763         },
 764         {
 765                 /* VCR/SWR/DMICR */
 766                 .start  = 0xe68c0000,
 767                 .end    = 0xe68c0014 - 1,
 768                 .flags  = IORESOURCE_MEM,
 769         },
 770         {
 771                 /* IRQ for channels */
 772                 .start  = evt2irq(0x1d00),
 773                 .end    = evt2irq(0x1d00),
 774                 .flags  = IORESOURCE_IRQ,
 775         },
 776 };
 777
 778 static struct platform_device usb_dma1_device = {
 779         .name           = "sh-dma-engine",
 780         .id             = 4,
 781         .resource       = sh7372_usb_dmae1_resources,
 782         .num_resources  = ARRAY_SIZE(sh7372_usb_dmae1_resources),
 783         .dev            = {
 784                 .platform_data  = &usb_dma1_platform_data,
 785         },
 786 };
 787
 788 /* VPU */
 789 static struct uio_info vpu_platform_data = {
 790         .name = "VPU5HG",
 791         .version = "0",
 792         .irq = intcs_evt2irq(0x980),
 793 };
 794
 795 static struct resource vpu_resources[] = {
 796         [0] = {
 797                 .name   = "VPU",
 798                 .start  = 0xfe900000,
 799                 .end    = 0xfe900157,
 800                 .flags  = IORESOURCE_MEM,
 801         },
 802 };
 803
 804 static struct platform_device vpu_device = {
 805         .name           = "uio_pdrv_genirq",
 806         .id             = 0,
 807         .dev = {
 808                 .platform_data  = &vpu_platform_data,
 809         },
 810         .resource       = vpu_resources,
 811         .num_resources  = ARRAY_SIZE(vpu_resources),
 812 };
 813
 814 /* VEU0 */
 815 static struct uio_info veu0_platform_data = {
 816         .name = "VEU0",
 817         .version = "0",
 818         .irq = intcs_evt2irq(0x700),
 819 };
 820
 821 static struct resource veu0_resources[] = {
 822         [0] = {
 823                 .name   = "VEU0",
 824                 .start  = 0xfe920000,
 825                 .end    = 0xfe9200cb,
 826                 .flags  = IORESOURCE_MEM,
 827         },
 828 };
 829
 830 static struct platform_device veu0_device = {
 831         .name           = "uio_pdrv_genirq",
 832         .id             = 1,
 833         .dev = {
 834                 .platform_data  = &veu0_platform_data,
 835         },
 836         .resource       = veu0_resources,
 837         .num_resources  = ARRAY_SIZE(veu0_resources),
 838 };
 839
 840 /* VEU1 */
 841 static struct uio_info veu1_platform_data = {
 842         .name = "VEU1",
 843         .version = "0",
 844         .irq = intcs_evt2irq(0x720),
 845 };
 846
 847 static struct resource veu1_resources[] = {
 848         [0] = {
 849                 .name   = "VEU1",
 850                 .start  = 0xfe924000,
 851                 .end    = 0xfe9240cb,
 852                 .flags  = IORESOURCE_MEM,
 853         },
 854 };
 855
 856 static struct platform_device veu1_device = {
 857         .name           = "uio_pdrv_genirq",
 858         .id             = 2,
 859         .dev = {
 860                 .platform_data  = &veu1_platform_data,
 861         },
 862         .resource       = veu1_resources,
 863         .num_resources  = ARRAY_SIZE(veu1_resources),
 864 };
 865
 866 /* VEU2 */
 867 static struct uio_info veu2_platform_data = {
 868         .name = "VEU2",
 869         .version = "0",
 870         .irq = intcs_evt2irq(0x740),
 871 };
 872
 873 static struct resource veu2_resources[] = {
 874         [0] = {
 875                 .name   = "VEU2",
 876                 .start  = 0xfe928000,
 877                 .end    = 0xfe928307,
 878                 .flags  = IORESOURCE_MEM,
 879         },
 880 };
 881
 882 static struct platform_device veu2_device = {
 883         .name           = "uio_pdrv_genirq",
 884         .id             = 3,
 885         .dev = {
 886                 .platform_data  = &veu2_platform_data,
 887         },
 888         .resource       = veu2_resources,
 889         .num_resources  = ARRAY_SIZE(veu2_resources),
 890 };
 891
 892 /* VEU3 */
 893 static struct uio_info veu3_platform_data = {
 894         .name = "VEU3",
 895         .version = "0",
 896         .irq = intcs_evt2irq(0x760),
 897 };
 898
 899 static struct resource veu3_resources[] = {
 900         [0] = {
 901                 .name   = "VEU3",
 902                 .start  = 0xfe92c000,
 903                 .end    = 0xfe92c307,
 904                 .flags  = IORESOURCE_MEM,
 905         },
 906 };
 907
 908 static struct platform_device veu3_device = {
 909         .name           = "uio_pdrv_genirq",
 910         .id             = 4,
 911         .dev = {
 912                 .platform_data  = &veu3_platform_data,
 913         },
 914         .resource       = veu3_resources,
 915         .num_resources  = ARRAY_SIZE(veu3_resources),
 916 };
 917
 918 /* JPU */
 919 static struct uio_info jpu_platform_data = {
 920         .name = "JPU",
 921         .version = "0",
 922         .irq = intcs_evt2irq(0x560),
 923 };
 924
 925 static struct resource jpu_resources[] = {
 926         [0] = {
 927                 .name   = "JPU",
 928                 .start  = 0xfe980000,
 929                 .end    = 0xfe9902d3,
 930                 .flags  = IORESOURCE_MEM,
 931         },
 932 };
 933
 934 static struct platform_device jpu_device = {
 935         .name           = "uio_pdrv_genirq",
 936         .id             = 5,
 937         .dev = {
 938                 .platform_data  = &jpu_platform_data,
 939         },
 940         .resource       = jpu_resources,
 941         .num_resources  = ARRAY_SIZE(jpu_resources),
 942 };
 943
 944 /* SPU2DSP0 */
 945 static struct uio_info spu0_platform_data = {
 946         .name = "SPU2DSP0",
 947         .version = "0",
 948         .irq = evt2irq(0x1800),
 949 };
 950
 951 static struct resource spu0_resources[] = {
 952         [0] = {
 953                 .name   = "SPU2DSP0",
 954                 .start  = 0xfe200000,
 955                 .end    = 0xfe2fffff,
 956                 .flags  = IORESOURCE_MEM,
 957         },
 958 };
 959
 960 static struct platform_device spu0_device = {
 961         .name           = "uio_pdrv_genirq",
 962         .id             = 6,
 963         .dev = {
 964                 .platform_data  = &spu0_platform_data,
 965         },
 966         .resource       = spu0_resources,
 967         .num_resources  = ARRAY_SIZE(spu0_resources),
 968 };
 969
 970 /* SPU2DSP1 */
 971 static struct uio_info spu1_platform_data = {
 972         .name = "SPU2DSP1",
 973         .version = "0",
 974         .irq = evt2irq(0x1820),
 975 };
 976
 977 static struct resource spu1_resources[] = {
 978         [0] = {
 979                 .name   = "SPU2DSP1",
 980                 .start  = 0xfe300000,
 981                 .end    = 0xfe3fffff,
 982                 .flags  = IORESOURCE_MEM,
 983         },
 984 };
 985
 986 static struct platform_device spu1_device = {
 987         .name           = "uio_pdrv_genirq",
 988         .id             = 7,
 989         .dev = {
 990                 .platform_data  = &spu1_platform_data,
 991         },
 992         .resource       = spu1_resources,
 993         .num_resources  = ARRAY_SIZE(spu1_resources),
 994 };
 995
 996 static struct platform_device *sh7372_early_devices[] __initdata = {
 997         &scif0_device,
 998         &scif1_device,
 999         &scif2_device,
1000         &scif3_device,
1001         &scif4_device,
1002         &scif5_device,
1003         &scif6_device,
1004         &cmt2_device,
1005         &tmu00_device,
1006         &tmu01_device,
1007 };
1008
1009 static struct platform_device *sh7372_late_devices[] __initdata = {
1010         &iic0_device,
1011         &iic1_device,
1012         &dma0_device,
1013         &dma1_device,
1014         &dma2_device,
1015         &usb_dma0_device,
1016         &usb_dma1_device,
1017         &vpu_device,
1018         &veu0_device,
1019         &veu1_device,
1020         &veu2_device,
1021         &veu3_device,
1022         &jpu_device,
1023         &spu0_device,
1024         &spu1_device,
1025 };
1026
1027 void __init sh7372_add_standard_devices(void)
1028 {
1029         sh7372_init_pm_domain(&sh7372_a4lc);
1030         sh7372_init_pm_domain(&sh7372_a4mp);
1031         sh7372_init_pm_domain(&sh7372_d4);
1032         sh7372_init_pm_domain(&sh7372_a4r);
1033         sh7372_init_pm_domain(&sh7372_a3rv);
1034         sh7372_init_pm_domain(&sh7372_a3ri);
1035         sh7372_init_pm_domain(&sh7372_a4s);
1036         sh7372_init_pm_domain(&sh7372_a3sp);
1037         sh7372_init_pm_domain(&sh7372_a3sg);
1038
1039         sh7372_pm_add_subdomain(&sh7372_a4lc, &sh7372_a3rv);
1040         sh7372_pm_add_subdomain(&sh7372_a4r, &sh7372_a4lc);
1041
1042         sh7372_pm_add_subdomain(&sh7372_a4s, &sh7372_a3sg);
1043         sh7372_pm_add_subdomain(&sh7372_a4s, &sh7372_a3sp);
1044
1045         platform_add_devices(sh7372_early_devices,
1046                             ARRAY_SIZE(sh7372_early_devices));
1047
1048         platform_add_devices(sh7372_late_devices,
1049                             ARRAY_SIZE(sh7372_late_devices));
1050
1051         sh7372_add_device_to_domain(&sh7372_a3rv, &vpu_device);
1052         sh7372_add_device_to_domain(&sh7372_a4mp, &spu0_device);
1053         sh7372_add_device_to_domain(&sh7372_a4mp, &spu1_device);
1054         sh7372_add_device_to_domain(&sh7372_a3sp, &scif0_device);
1055         sh7372_add_device_to_domain(&sh7372_a3sp, &scif1_device);
1056         sh7372_add_device_to_domain(&sh7372_a3sp, &scif2_device);
1057         sh7372_add_device_to_domain(&sh7372_a3sp, &scif3_device);
1058         sh7372_add_device_to_domain(&sh7372_a3sp, &scif4_device);
1059         sh7372_add_device_to_domain(&sh7372_a3sp, &scif5_device);
1060         sh7372_add_device_to_domain(&sh7372_a3sp, &scif6_device);
1061         sh7372_add_device_to_domain(&sh7372_a3sp, &iic1_device);
1062         sh7372_add_device_to_domain(&sh7372_a3sp, &dma0_device);
1063         sh7372_add_device_to_domain(&sh7372_a3sp, &dma1_device);
1064         sh7372_add_device_to_domain(&sh7372_a3sp, &dma2_device);
1065         sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma0_device);
1066         sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma1_device);
1067         sh7372_add_device_to_domain(&sh7372_a4r, &iic0_device);
1068         sh7372_add_device_to_domain(&sh7372_a4r, &veu0_device);
1069         sh7372_add_device_to_domain(&sh7372_a4r, &veu1_device);
1070         sh7372_add_device_to_domain(&sh7372_a4r, &veu2_device);
1071         sh7372_add_device_to_domain(&sh7372_a4r, &veu3_device);
1072         sh7372_add_device_to_domain(&sh7372_a4r, &jpu_device);
1073 }
1074
1075 static void __init sh7372_earlytimer_init(void)
1076 {
1077         sh7372_clock_init();
1078         shmobile_earlytimer_init();
1079 }
1080
1081 void __init sh7372_add_early_devices(void)
1082 {
1083         early_platform_add_devices(sh7372_early_devices,
1084                                    ARRAY_SIZE(sh7372_early_devices));
1085
1086         /* setup early console here as well */
1087         shmobile_setup_console();
1088
1089         /* override timer setup with soc-specific code */
1090         shmobile_timer.init = sh7372_earlytimer_init;
1091 }