arch/arm/mach-shmobile/setup-sh73a0.c

   1 /*
   2  * sh73a0 processor support
   3  *
   4  * Copyright (C) 2010  Takashi Yoshii
   5  * Copyright (C) 2010  Magnus Damm
   6  * Copyright (C) 2008  Yoshihiro Shimoda
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  20  */
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/irq.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/of_platform.h>
  27 #include <linux/delay.h>
  28 #include <linux/input.h>
  29 #include <linux/io.h>
  30 #include <linux/serial_sci.h>
  31 #include <linux/sh_dma.h>
  32 #include <linux/sh_intc.h>
  33 #include <linux/sh_timer.h>
  34 #include <linux/platform_data/sh_ipmmu.h>
  35 #include <mach/dma-register.h>
  36 #include <mach/hardware.h>
  37 #include <mach/irqs.h>
  38 #include <mach/sh73a0.h>
  39 #include <mach/common.h>
  40 #include <asm/mach-types.h>
  41 #include <asm/mach/map.h>
  42 #include <asm/mach/arch.h>
  43 #include <asm/mach/time.h>
  44
  45 static struct map_desc sh73a0_io_desc[] __initdata = {
  46         /* create a 1:1 entity map for 0xe6xxxxxx
  47          * used by CPGA, INTC and PFC.
  48          */
  49         {
  50                 .virtual        = 0xe6000000,
  51                 .pfn            = __phys_to_pfn(0xe6000000),
  52                 .length         = 256 << 20,
  53                 .type           = MT_DEVICE_NONSHARED
  54         },
  55 };
  56
  57 void __init sh73a0_map_io(void)
  58 {
  59         iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
  60 }
  61
  62 static struct resource sh73a0_pfc_resources[] = {
  63         [0] = {
  64                 .start  = 0xe6050000,
  65                 .end    = 0xe6057fff,
  66                 .flags  = IORESOURCE_MEM,
  67         },
  68         [1] = {
  69                 .start  = 0xe605801c,
  70                 .end    = 0xe6058027,
  71                 .flags  = IORESOURCE_MEM,
  72         }
  73 };
  74
  75 static struct platform_device sh73a0_pfc_device = {
  76         .name           = "pfc-sh73a0",
  77         .id             = -1,
  78         .resource       = sh73a0_pfc_resources,
  79         .num_resources  = ARRAY_SIZE(sh73a0_pfc_resources),
  80 };
  81
  82 void __init sh73a0_pinmux_init(void)
  83 {
  84         platform_device_register(&sh73a0_pfc_device);
  85 }
  86
  87 static struct plat_sci_port scif0_platform_data = {
  88         .mapbase        = 0xe6c40000,
  89         .flags          = UPF_BOOT_AUTOCONF,
  90         .scscr          = SCSCR_RE | SCSCR_TE,
  91         .scbrr_algo_id  = SCBRR_ALGO_4,
  92         .type           = PORT_SCIFA,
  93         .irqs           = { gic_spi(72), gic_spi(72),
  94                             gic_spi(72), gic_spi(72) },
  95 };
  96
  97 static struct platform_device scif0_device = {
  98         .name           = "sh-sci",
  99         .id             = 0,
 100         .dev            = {
 101                 .platform_data  = &scif0_platform_data,
 102         },
 103 };
 104
 105 static struct plat_sci_port scif1_platform_data = {
 106         .mapbase        = 0xe6c50000,
 107         .flags          = UPF_BOOT_AUTOCONF,
 108         .scscr          = SCSCR_RE | SCSCR_TE,
 109         .scbrr_algo_id  = SCBRR_ALGO_4,
 110         .type           = PORT_SCIFA,
 111         .irqs           = { gic_spi(73), gic_spi(73),
 112                             gic_spi(73), gic_spi(73) },
 113 };
 114
 115 static struct platform_device scif1_device = {
 116         .name           = "sh-sci",
 117         .id             = 1,
 118         .dev            = {
 119                 .platform_data  = &scif1_platform_data,
 120         },
 121 };
 122
 123 static struct plat_sci_port scif2_platform_data = {
 124         .mapbase        = 0xe6c60000,
 125         .flags          = UPF_BOOT_AUTOCONF,
 126         .scscr          = SCSCR_RE | SCSCR_TE,
 127         .scbrr_algo_id  = SCBRR_ALGO_4,
 128         .type           = PORT_SCIFA,
 129         .irqs           = { gic_spi(74), gic_spi(74),
 130                             gic_spi(74), gic_spi(74) },
 131 };
 132
 133 static struct platform_device scif2_device = {
 134         .name           = "sh-sci",
 135         .id             = 2,
 136         .dev            = {
 137                 .platform_data  = &scif2_platform_data,
 138         },
 139 };
 140
 141 static struct plat_sci_port scif3_platform_data = {
 142         .mapbase        = 0xe6c70000,
 143         .flags          = UPF_BOOT_AUTOCONF,
 144         .scscr          = SCSCR_RE | SCSCR_TE,
 145         .scbrr_algo_id  = SCBRR_ALGO_4,
 146         .type           = PORT_SCIFA,
 147         .irqs           = { gic_spi(75), gic_spi(75),
 148                             gic_spi(75), gic_spi(75) },
 149 };
 150
 151 static struct platform_device scif3_device = {
 152         .name           = "sh-sci",
 153         .id             = 3,
 154         .dev            = {
 155                 .platform_data  = &scif3_platform_data,
 156         },
 157 };
 158
 159 static struct plat_sci_port scif4_platform_data = {
 160         .mapbase        = 0xe6c80000,
 161         .flags          = UPF_BOOT_AUTOCONF,
 162         .scscr          = SCSCR_RE | SCSCR_TE,
 163         .scbrr_algo_id  = SCBRR_ALGO_4,
 164         .type           = PORT_SCIFA,
 165         .irqs           = { gic_spi(78), gic_spi(78),
 166                             gic_spi(78), gic_spi(78) },
 167 };
 168
 169 static struct platform_device scif4_device = {
 170         .name           = "sh-sci",
 171         .id             = 4,
 172         .dev            = {
 173                 .platform_data  = &scif4_platform_data,
 174         },
 175 };
 176
 177 static struct plat_sci_port scif5_platform_data = {
 178         .mapbase        = 0xe6cb0000,
 179         .flags          = UPF_BOOT_AUTOCONF,
 180         .scscr          = SCSCR_RE | SCSCR_TE,
 181         .scbrr_algo_id  = SCBRR_ALGO_4,
 182         .type           = PORT_SCIFA,
 183         .irqs           = { gic_spi(79), gic_spi(79),
 184                             gic_spi(79), gic_spi(79) },
 185 };
 186
 187 static struct platform_device scif5_device = {
 188         .name           = "sh-sci",
 189         .id             = 5,
 190         .dev            = {
 191                 .platform_data  = &scif5_platform_data,
 192         },
 193 };
 194
 195 static struct plat_sci_port scif6_platform_data = {
 196         .mapbase        = 0xe6cc0000,
 197         .flags          = UPF_BOOT_AUTOCONF,
 198         .scscr          = SCSCR_RE | SCSCR_TE,
 199         .scbrr_algo_id  = SCBRR_ALGO_4,
 200         .type           = PORT_SCIFA,
 201         .irqs           = { gic_spi(156), gic_spi(156),
 202                             gic_spi(156), gic_spi(156) },
 203 };
 204
 205 static struct platform_device scif6_device = {
 206         .name           = "sh-sci",
 207         .id             = 6,
 208         .dev            = {
 209                 .platform_data  = &scif6_platform_data,
 210         },
 211 };
 212
 213 static struct plat_sci_port scif7_platform_data = {
 214         .mapbase        = 0xe6cd0000,
 215         .flags          = UPF_BOOT_AUTOCONF,
 216         .scscr          = SCSCR_RE | SCSCR_TE,
 217         .scbrr_algo_id  = SCBRR_ALGO_4,
 218         .type           = PORT_SCIFA,
 219         .irqs           = { gic_spi(143), gic_spi(143),
 220                             gic_spi(143), gic_spi(143) },
 221 };
 222
 223 static struct platform_device scif7_device = {
 224         .name           = "sh-sci",
 225         .id             = 7,
 226         .dev            = {
 227                 .platform_data  = &scif7_platform_data,
 228         },
 229 };
 230
 231 static struct plat_sci_port scif8_platform_data = {
 232         .mapbase        = 0xe6c30000,
 233         .flags          = UPF_BOOT_AUTOCONF,
 234         .scscr          = SCSCR_RE | SCSCR_TE,
 235         .scbrr_algo_id  = SCBRR_ALGO_4,
 236         .type           = PORT_SCIFB,
 237         .irqs           = { gic_spi(80), gic_spi(80),
 238                             gic_spi(80), gic_spi(80) },
 239 };
 240
 241 static struct platform_device scif8_device = {
 242         .name           = "sh-sci",
 243         .id             = 8,
 244         .dev            = {
 245                 .platform_data  = &scif8_platform_data,
 246         },
 247 };
 248
 249 static struct sh_timer_config cmt10_platform_data = {
 250         .name = "CMT10",
 251         .channel_offset = 0x10,
 252         .timer_bit = 0,
 253         .clockevent_rating = 125,
 254         .clocksource_rating = 125,
 255 };
 256
 257 static struct resource cmt10_resources[] = {
 258         [0] = {
 259                 .name   = "CMT10",
 260                 .start  = 0xe6138010,
 261                 .end    = 0xe613801b,
 262                 .flags  = IORESOURCE_MEM,
 263         },
 264         [1] = {
 265                 .start  = gic_spi(65),
 266                 .flags  = IORESOURCE_IRQ,
 267         },
 268 };
 269
 270 static struct platform_device cmt10_device = {
 271         .name           = "sh_cmt",
 272         .id             = 10,
 273         .dev = {
 274                 .platform_data  = &cmt10_platform_data,
 275         },
 276         .resource       = cmt10_resources,
 277         .num_resources  = ARRAY_SIZE(cmt10_resources),
 278 };
 279
 280 /* TMU */
 281 static struct sh_timer_config tmu00_platform_data = {
 282         .name = "TMU00",
 283         .channel_offset = 0x4,
 284         .timer_bit = 0,
 285         .clockevent_rating = 200,
 286 };
 287
 288 static struct resource tmu00_resources[] = {
 289         [0] = {
 290                 .name   = "TMU00",
 291                 .start  = 0xfff60008,
 292                 .end    = 0xfff60013,
 293                 .flags  = IORESOURCE_MEM,
 294         },
 295         [1] = {
 296                 .start  = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */
 297                 .flags  = IORESOURCE_IRQ,
 298         },
 299 };
 300
 301 static struct platform_device tmu00_device = {
 302         .name           = "sh_tmu",
 303         .id             = 0,
 304         .dev = {
 305                 .platform_data  = &tmu00_platform_data,
 306         },
 307         .resource       = tmu00_resources,
 308         .num_resources  = ARRAY_SIZE(tmu00_resources),
 309 };
 310
 311 static struct sh_timer_config tmu01_platform_data = {
 312         .name = "TMU01",
 313         .channel_offset = 0x10,
 314         .timer_bit = 1,
 315         .clocksource_rating = 200,
 316 };
 317
 318 static struct resource tmu01_resources[] = {
 319         [0] = {
 320                 .name   = "TMU01",
 321                 .start  = 0xfff60014,
 322                 .end    = 0xfff6001f,
 323                 .flags  = IORESOURCE_MEM,
 324         },
 325         [1] = {
 326                 .start  = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */
 327                 .flags  = IORESOURCE_IRQ,
 328         },
 329 };
 330
 331 static struct platform_device tmu01_device = {
 332         .name           = "sh_tmu",
 333         .id             = 1,
 334         .dev = {
 335                 .platform_data  = &tmu01_platform_data,
 336         },
 337         .resource       = tmu01_resources,
 338         .num_resources  = ARRAY_SIZE(tmu01_resources),
 339 };
 340
 341 static struct resource i2c0_resources[] = {
 342         [0] = {
 343                 .name   = "IIC0",
 344                 .start  = 0xe6820000,
 345                 .end    = 0xe6820425 - 1,
 346                 .flags  = IORESOURCE_MEM,
 347         },
 348         [1] = {
 349                 .start  = gic_spi(167),
 350                 .end    = gic_spi(170),
 351                 .flags  = IORESOURCE_IRQ,
 352         },
 353 };
 354
 355 static struct resource i2c1_resources[] = {
 356         [0] = {
 357                 .name   = "IIC1",
 358                 .start  = 0xe6822000,
 359                 .end    = 0xe6822425 - 1,
 360                 .flags  = IORESOURCE_MEM,
 361         },
 362         [1] = {
 363                 .start  = gic_spi(51),
 364                 .end    = gic_spi(54),
 365                 .flags  = IORESOURCE_IRQ,
 366         },
 367 };
 368
 369 static struct resource i2c2_resources[] = {
 370         [0] = {
 371                 .name   = "IIC2",
 372                 .start  = 0xe6824000,
 373                 .end    = 0xe6824425 - 1,
 374                 .flags  = IORESOURCE_MEM,
 375         },
 376         [1] = {
 377                 .start  = gic_spi(171),
 378                 .end    = gic_spi(174),
 379                 .flags  = IORESOURCE_IRQ,
 380         },
 381 };
 382
 383 static struct resource i2c3_resources[] = {
 384         [0] = {
 385                 .name   = "IIC3",
 386                 .start  = 0xe6826000,
 387                 .end    = 0xe6826425 - 1,
 388                 .flags  = IORESOURCE_MEM,
 389         },
 390         [1] = {
 391                 .start  = gic_spi(183),
 392                 .end    = gic_spi(186),
 393                 .flags  = IORESOURCE_IRQ,
 394         },
 395 };
 396
 397 static struct resource i2c4_resources[] = {
 398         [0] = {
 399                 .name   = "IIC4",
 400                 .start  = 0xe6828000,
 401                 .end    = 0xe6828425 - 1,
 402                 .flags  = IORESOURCE_MEM,
 403         },
 404         [1] = {
 405                 .start  = gic_spi(187),
 406                 .end    = gic_spi(190),
 407                 .flags  = IORESOURCE_IRQ,
 408         },
 409 };
 410
 411 static struct platform_device i2c0_device = {
 412         .name           = "i2c-sh_mobile",
 413         .id             = 0,
 414         .resource       = i2c0_resources,
 415         .num_resources  = ARRAY_SIZE(i2c0_resources),
 416 };
 417
 418 static struct platform_device i2c1_device = {
 419         .name           = "i2c-sh_mobile",
 420         .id             = 1,
 421         .resource       = i2c1_resources,
 422         .num_resources  = ARRAY_SIZE(i2c1_resources),
 423 };
 424
 425 static struct platform_device i2c2_device = {
 426         .name           = "i2c-sh_mobile",
 427         .id             = 2,
 428         .resource       = i2c2_resources,
 429         .num_resources  = ARRAY_SIZE(i2c2_resources),
 430 };
 431
 432 static struct platform_device i2c3_device = {
 433         .name           = "i2c-sh_mobile",
 434         .id             = 3,
 435         .resource       = i2c3_resources,
 436         .num_resources  = ARRAY_SIZE(i2c3_resources),
 437 };
 438
 439 static struct platform_device i2c4_device = {
 440         .name           = "i2c-sh_mobile",
 441         .id             = 4,
 442         .resource       = i2c4_resources,
 443         .num_resources  = ARRAY_SIZE(i2c4_resources),
 444 };
 445
 446 static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
 447         {
 448                 .slave_id       = SHDMA_SLAVE_SCIF0_TX,
 449                 .addr           = 0xe6c40020,
 450                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 451                 .mid_rid        = 0x21,
 452         }, {
 453                 .slave_id       = SHDMA_SLAVE_SCIF0_RX,
 454                 .addr           = 0xe6c40024,
 455                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 456                 .mid_rid        = 0x22,
 457         }, {
 458                 .slave_id       = SHDMA_SLAVE_SCIF1_TX,
 459                 .addr           = 0xe6c50020,
 460                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 461                 .mid_rid        = 0x25,
 462         }, {
 463                 .slave_id       = SHDMA_SLAVE_SCIF1_RX,
 464                 .addr           = 0xe6c50024,
 465                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 466                 .mid_rid        = 0x26,
 467         }, {
 468                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
 469                 .addr           = 0xe6c60020,
 470                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 471                 .mid_rid        = 0x29,
 472         }, {
 473                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
 474                 .addr           = 0xe6c60024,
 475                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 476                 .mid_rid        = 0x2a,
 477         }, {
 478                 .slave_id       = SHDMA_SLAVE_SCIF3_TX,
 479                 .addr           = 0xe6c70020,
 480                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 481                 .mid_rid        = 0x2d,
 482         }, {
 483                 .slave_id       = SHDMA_SLAVE_SCIF3_RX,
 484                 .addr           = 0xe6c70024,
 485                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 486                 .mid_rid        = 0x2e,
 487         }, {
 488                 .slave_id       = SHDMA_SLAVE_SCIF4_TX,
 489                 .addr           = 0xe6c80020,
 490                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 491                 .mid_rid        = 0x39,
 492         }, {
 493                 .slave_id       = SHDMA_SLAVE_SCIF4_RX,
 494                 .addr           = 0xe6c80024,
 495                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 496                 .mid_rid        = 0x3a,
 497         }, {
 498                 .slave_id       = SHDMA_SLAVE_SCIF5_TX,
 499                 .addr           = 0xe6cb0020,
 500                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 501                 .mid_rid        = 0x35,
 502         }, {
 503                 .slave_id       = SHDMA_SLAVE_SCIF5_RX,
 504                 .addr           = 0xe6cb0024,
 505                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 506                 .mid_rid        = 0x36,
 507         }, {
 508                 .slave_id       = SHDMA_SLAVE_SCIF6_TX,
 509                 .addr           = 0xe6cc0020,
 510                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 511                 .mid_rid        = 0x1d,
 512         }, {
 513                 .slave_id       = SHDMA_SLAVE_SCIF6_RX,
 514                 .addr           = 0xe6cc0024,
 515                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 516                 .mid_rid        = 0x1e,
 517         }, {
 518                 .slave_id       = SHDMA_SLAVE_SCIF7_TX,
 519                 .addr           = 0xe6cd0020,
 520                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 521                 .mid_rid        = 0x19,
 522         }, {
 523                 .slave_id       = SHDMA_SLAVE_SCIF7_RX,
 524                 .addr           = 0xe6cd0024,
 525                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 526                 .mid_rid        = 0x1a,
 527         }, {
 528                 .slave_id       = SHDMA_SLAVE_SCIF8_TX,
 529                 .addr           = 0xe6c30040,
 530                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 531                 .mid_rid        = 0x3d,
 532         }, {
 533                 .slave_id       = SHDMA_SLAVE_SCIF8_RX,
 534                 .addr           = 0xe6c30060,
 535                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 536                 .mid_rid        = 0x3e,
 537         }, {
 538                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 539                 .addr           = 0xee100030,
 540                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 541                 .mid_rid        = 0xc1,
 542         }, {
 543                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 544                 .addr           = 0xee100030,
 545                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 546                 .mid_rid        = 0xc2,
 547         }, {
 548                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 549                 .addr           = 0xee120030,
 550                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 551                 .mid_rid        = 0xc9,
 552         }, {
 553                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 554                 .addr           = 0xee120030,
 555                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 556                 .mid_rid        = 0xca,
 557         }, {
 558                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
 559                 .addr           = 0xee140030,
 560                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 561                 .mid_rid        = 0xcd,
 562         }, {
 563                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
 564                 .addr           = 0xee140030,
 565                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 566                 .mid_rid        = 0xce,
 567         }, {
 568                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
 569                 .addr           = 0xe6bd0034,
 570                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 571                 .mid_rid        = 0xd1,
 572         }, {
 573                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
 574                 .addr           = 0xe6bd0034,
 575                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 576                 .mid_rid        = 0xd2,
 577         },
 578 };
 579
 580 #define DMAE_CHANNEL(_offset)                                   \
 581         {                                                       \
 582                 .offset         = _offset - 0x20,               \
 583                 .dmars          = _offset - 0x20 + 0x40,        \
 584         }
 585
 586 static const struct sh_dmae_channel sh73a0_dmae_channels[] = {
 587         DMAE_CHANNEL(0x8000),
 588         DMAE_CHANNEL(0x8080),
 589         DMAE_CHANNEL(0x8100),
 590         DMAE_CHANNEL(0x8180),
 591         DMAE_CHANNEL(0x8200),
 592         DMAE_CHANNEL(0x8280),
 593         DMAE_CHANNEL(0x8300),
 594         DMAE_CHANNEL(0x8380),
 595         DMAE_CHANNEL(0x8400),
 596         DMAE_CHANNEL(0x8480),
 597         DMAE_CHANNEL(0x8500),
 598         DMAE_CHANNEL(0x8580),
 599         DMAE_CHANNEL(0x8600),
 600         DMAE_CHANNEL(0x8680),
 601         DMAE_CHANNEL(0x8700),
 602         DMAE_CHANNEL(0x8780),
 603         DMAE_CHANNEL(0x8800),
 604         DMAE_CHANNEL(0x8880),
 605         DMAE_CHANNEL(0x8900),
 606         DMAE_CHANNEL(0x8980),
 607 };
 608
 609 static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
 610         .slave          = sh73a0_dmae_slaves,
 611         .slave_num      = ARRAY_SIZE(sh73a0_dmae_slaves),
 612         .channel        = sh73a0_dmae_channels,
 613         .channel_num    = ARRAY_SIZE(sh73a0_dmae_channels),
 614         .ts_low_shift   = TS_LOW_SHIFT,
 615         .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
 616         .ts_high_shift  = TS_HI_SHIFT,
 617         .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
 618         .ts_shift       = dma_ts_shift,
 619         .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
 620         .dmaor_init     = DMAOR_DME,
 621 };
 622
 623 static struct resource sh73a0_dmae_resources[] = {
 624         {
 625                 /* Registers including DMAOR and channels including DMARSx */
 626                 .start  = 0xfe000020,
 627                 .end    = 0xfe008a00 - 1,
 628                 .flags  = IORESOURCE_MEM,
 629         },
 630         {
 631                 .name   = "error_irq",
 632                 .start  = gic_spi(129),
 633                 .end    = gic_spi(129),
 634                 .flags  = IORESOURCE_IRQ,
 635         },
 636         {
 637                 /* IRQ for channels 0-19 */
 638                 .start  = gic_spi(109),
 639                 .end    = gic_spi(128),
 640                 .flags  = IORESOURCE_IRQ,
 641         },
 642 };
 643
 644 static struct platform_device dma0_device = {
 645         .name           = "sh-dma-engine",
 646         .id             = 0,
 647         .resource       = sh73a0_dmae_resources,
 648         .num_resources  = ARRAY_SIZE(sh73a0_dmae_resources),
 649         .dev            = {
 650                 .platform_data  = &sh73a0_dmae_platform_data,
 651         },
 652 };
 653
 654 /* MPDMAC */
 655 static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = {
 656         {
 657                 .slave_id       = SHDMA_SLAVE_FSI2A_RX,
 658                 .addr           = 0xec230020,
 659                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 660                 .mid_rid        = 0xd6, /* CHECK ME */
 661         }, {
 662                 .slave_id       = SHDMA_SLAVE_FSI2A_TX,
 663                 .addr           = 0xec230024,
 664                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 665                 .mid_rid        = 0xd5, /* CHECK ME */
 666         }, {
 667                 .slave_id       = SHDMA_SLAVE_FSI2C_RX,
 668                 .addr           = 0xec230060,
 669                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 670                 .mid_rid        = 0xda, /* CHECK ME */
 671         }, {
 672                 .slave_id       = SHDMA_SLAVE_FSI2C_TX,
 673                 .addr           = 0xec230064,
 674                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 675                 .mid_rid        = 0xd9, /* CHECK ME */
 676         }, {
 677                 .slave_id       = SHDMA_SLAVE_FSI2B_RX,
 678                 .addr           = 0xec240020,
 679                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 680                 .mid_rid        = 0x8e, /* CHECK ME */
 681         }, {
 682                 .slave_id       = SHDMA_SLAVE_FSI2B_TX,
 683                 .addr           = 0xec240024,
 684                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 685                 .mid_rid        = 0x8d, /* CHECK ME */
 686         }, {
 687                 .slave_id       = SHDMA_SLAVE_FSI2D_RX,
 688                 .addr           =  0xec240060,
 689                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 690                 .mid_rid        = 0x9a, /* CHECK ME */
 691         },
 692 };
 693
 694 #define MPDMA_CHANNEL(a, b, c)                  \
 695 {                                               \
 696         .offset         = a,                    \
 697         .dmars          = b,                    \
 698         .dmars_bit      = c,                    \
 699         .chclr_offset   = (0x220 - 0x20) + a    \
 700 }
 701
 702 static const struct sh_dmae_channel sh73a0_mpdma_channels[] = {
 703         MPDMA_CHANNEL(0x00, 0, 0),
 704         MPDMA_CHANNEL(0x10, 0, 8),
 705         MPDMA_CHANNEL(0x20, 4, 0),
 706         MPDMA_CHANNEL(0x30, 4, 8),
 707         MPDMA_CHANNEL(0x50, 8, 0),
 708         MPDMA_CHANNEL(0x70, 8, 8),
 709 };
 710
 711 static struct sh_dmae_pdata sh73a0_mpdma_platform_data = {
 712         .slave          = sh73a0_mpdma_slaves,
 713         .slave_num      = ARRAY_SIZE(sh73a0_mpdma_slaves),
 714         .channel        = sh73a0_mpdma_channels,
 715         .channel_num    = ARRAY_SIZE(sh73a0_mpdma_channels),
 716         .ts_low_shift   = TS_LOW_SHIFT,
 717         .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
 718         .ts_high_shift  = TS_HI_SHIFT,
 719         .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
 720         .ts_shift       = dma_ts_shift,
 721         .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
 722         .dmaor_init     = DMAOR_DME,
 723         .chclr_present  = 1,
 724 };
 725
 726 /* Resource order important! */
 727 static struct resource sh73a0_mpdma_resources[] = {
 728         {
 729                 /* Channel registers and DMAOR */
 730                 .start  = 0xec618020,
 731                 .end    = 0xec61828f,
 732                 .flags  = IORESOURCE_MEM,
 733         },
 734         {
 735                 /* DMARSx */
 736                 .start  = 0xec619000,
 737                 .end    = 0xec61900b,
 738                 .flags  = IORESOURCE_MEM,
 739         },
 740         {
 741                 .name   = "error_irq",
 742                 .start  = gic_spi(181),
 743                 .end    = gic_spi(181),
 744                 .flags  = IORESOURCE_IRQ,
 745         },
 746         {
 747                 /* IRQ for channels 0-5 */
 748                 .start  = gic_spi(175),
 749                 .end    = gic_spi(180),
 750                 .flags  = IORESOURCE_IRQ,
 751         },
 752 };
 753
 754 static struct platform_device mpdma0_device = {
 755         .name           = "sh-dma-engine",
 756         .id             = 1,
 757         .resource       = sh73a0_mpdma_resources,
 758         .num_resources  = ARRAY_SIZE(sh73a0_mpdma_resources),
 759         .dev            = {
 760                 .platform_data  = &sh73a0_mpdma_platform_data,
 761         },
 762 };
 763
 764 static struct resource pmu_resources[] = {
 765         [0] = {
 766                 .start  = gic_spi(55),
 767                 .end    = gic_spi(55),
 768                 .flags  = IORESOURCE_IRQ,
 769         },
 770         [1] = {
 771                 .start  = gic_spi(56),
 772                 .end    = gic_spi(56),
 773                 .flags  = IORESOURCE_IRQ,
 774         },
 775 };
 776
 777 static struct platform_device pmu_device = {
 778         .name           = "arm-pmu",
 779         .id             = -1,
 780         .num_resources  = ARRAY_SIZE(pmu_resources),
 781         .resource       = pmu_resources,
 782 };
 783
 784 /* an IPMMU module for ICB */
 785 static struct resource ipmmu_resources[] = {
 786         [0] = {
 787                 .name   = "IPMMU",
 788                 .start  = 0xfe951000,
 789                 .end    = 0xfe9510ff,
 790                 .flags  = IORESOURCE_MEM,
 791         },
 792 };
 793
 794 static const char * const ipmmu_dev_names[] = {
 795         "sh_mobile_lcdc_fb.0",
 796 };
 797
 798 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
 799         .dev_names = ipmmu_dev_names,
 800         .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
 801 };
 802
 803 static struct platform_device ipmmu_device = {
 804         .name           = "ipmmu",
 805         .id             = -1,
 806         .dev = {
 807                 .platform_data = &ipmmu_platform_data,
 808         },
 809         .resource       = ipmmu_resources,
 810         .num_resources  = ARRAY_SIZE(ipmmu_resources),
 811 };
 812
 813 static struct platform_device *sh73a0_early_devices_dt[] __initdata = {
 814         &scif0_device,
 815         &scif1_device,
 816         &scif2_device,
 817         &scif3_device,
 818         &scif4_device,
 819         &scif5_device,
 820         &scif6_device,
 821         &scif7_device,
 822         &scif8_device,
 823         &cmt10_device,
 824 };
 825
 826 static struct platform_device *sh73a0_early_devices[] __initdata = {
 827         &tmu00_device,
 828         &tmu01_device,
 829         &ipmmu_device,
 830 };
 831
 832 static struct platform_device *sh73a0_late_devices[] __initdata = {
 833         &i2c0_device,
 834         &i2c1_device,
 835         &i2c2_device,
 836         &i2c3_device,
 837         &i2c4_device,
 838         &dma0_device,
 839         &mpdma0_device,
 840         &pmu_device,
 841 };
 842
 843 #define SRCR2          IOMEM(0xe61580b0)
 844
 845 void __init sh73a0_add_standard_devices(void)
 846 {
 847         /* Clear software reset bit on SY-DMAC module */
 848         __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
 849
 850         platform_add_devices(sh73a0_early_devices_dt,
 851                             ARRAY_SIZE(sh73a0_early_devices_dt));
 852         platform_add_devices(sh73a0_early_devices,
 853                             ARRAY_SIZE(sh73a0_early_devices));
 854         platform_add_devices(sh73a0_late_devices,
 855                             ARRAY_SIZE(sh73a0_late_devices));
 856 }
 857
 858 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
 859 void __init __weak sh73a0_register_twd(void) { }
 860
 861 void __init sh73a0_earlytimer_init(void)
 862 {
 863         sh73a0_clock_init();
 864         shmobile_earlytimer_init();
 865         sh73a0_register_twd();
 866 }
 867
 868 void __init sh73a0_add_early_devices(void)
 869 {
 870         early_platform_add_devices(sh73a0_early_devices_dt,
 871                                    ARRAY_SIZE(sh73a0_early_devices_dt));
 872         early_platform_add_devices(sh73a0_early_devices,
 873                                    ARRAY_SIZE(sh73a0_early_devices));
 874
 875         /* setup early console here as well */
 876         shmobile_setup_console();
 877 }
 878
 879 #ifdef CONFIG_USE_OF
 880
 881 /* Please note that the clock initialisation shcheme used in
 882  * sh73a0_add_early_devices_dt() and sh73a0_add_standard_devices_dt()
 883  * does not work with SMP as there is a yet to be resolved lock-up in
 884  * workqueue initialisation.
 885  *
 886  * CONFIG_SMP should be disabled when using this code.
 887  */
 888
 889 void __init sh73a0_add_early_devices_dt(void)
 890 {
 891         shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */
 892
 893         early_platform_add_devices(sh73a0_early_devices_dt,
 894                                    ARRAY_SIZE(sh73a0_early_devices_dt));
 895
 896         /* setup early console here as well */
 897         shmobile_setup_console();
 898 }
 899
 900 static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = {
 901         {},
 902 };
 903
 904 void __init sh73a0_add_standard_devices_dt(void)
 905 {
 906         /* clocks are setup late during boot in the case of DT */
 907         sh73a0_clock_init();
 908
 909         platform_add_devices(sh73a0_early_devices_dt,
 910                              ARRAY_SIZE(sh73a0_early_devices_dt));
 911         of_platform_populate(NULL, of_default_bus_match_table,
 912                              sh73a0_auxdata_lookup, NULL);
 913 }
 914
 915 static const char *sh73a0_boards_compat_dt[] __initdata = {
 916         "renesas,sh73a0",
 917         NULL,
 918 };
 919
 920 DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
 921         .map_io         = sh73a0_map_io,
 922         .init_early     = sh73a0_add_early_devices_dt,
 923         .nr_irqs        = NR_IRQS_LEGACY,
 924         .init_irq       = sh73a0_init_irq_dt,
 925         .init_machine   = sh73a0_add_standard_devices_dt,
 926         .dt_compat      = sh73a0_boards_compat_dt,
 927 MACHINE_END
 928 #endif /* CONFIG_USE_OF */