arch/arm/mach-socfpga/platsmp.c

   1 /*
   2  * Copyright 2010-2011 Calxeda, Inc.
   3  * Copyright 2012 Pavel Machek <pavel@denx.de>
   4  * Based on platsmp.c, Copyright (C) 2002 ARM Ltd.
   5  * Copyright (C) 2012 Altera Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <linux/delay.h>
  20 #include <linux/init.h>
  21 #include <linux/smp.h>
  22 #include <linux/io.h>
  23 #include <linux/of.h>
  24 #include <linux/of_address.h>
  25
  26 #include <asm/cacheflush.h>
  27 #include <asm/smp_scu.h>
  28 #include <asm/smp_plat.h>
  29
  30 #include "core.h"
  31
  32 static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
  33 {
  34         int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
  35
  36         if (socfpga_cpu1start_addr) {
  37                 /* This will put CPU #1 into reset. */
  38                 writel(RSTMGR_MPUMODRST_CPU1,
  39                        rst_manager_base_addr + SOCFPGA_RSTMGR_MODMPURST);
  40
  41                 memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
  42
  43                 writel(virt_to_phys(socfpga_secondary_startup),
  44                        sys_manager_base_addr + (socfpga_cpu1start_addr & 0x000000ff));
  45
  46                 flush_cache_all();
  47                 smp_wmb();
  48                 outer_clean_range(0, trampoline_size);
  49
  50                 /* This will release CPU #1 out of reset. */
  51                 writel(0, rst_manager_base_addr + SOCFPGA_RSTMGR_MODMPURST);
  52         }
  53
  54         return 0;
  55 }
  56
  57 static void __init socfpga_smp_prepare_cpus(unsigned int max_cpus)
  58 {
  59         struct device_node *np;
  60         void __iomem *socfpga_scu_base_addr;
  61
  62         np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
  63         if (!np) {
  64                 pr_err("%s: missing scu\n", __func__);
  65                 return;
  66         }
  67
  68         socfpga_scu_base_addr = of_iomap(np, 0);
  69         if (!socfpga_scu_base_addr)
  70                 return;
  71         scu_enable(socfpga_scu_base_addr);
  72 }
  73
  74 /*
  75  * platform-specific code to shutdown a CPU
  76  *
  77  * Called with IRQs disabled
  78  */
  79 static void socfpga_cpu_die(unsigned int cpu)
  80 {
  81         /* Do WFI. If we wake up early, go back into WFI */
  82         while (1)
  83                 cpu_do_idle();
  84 }
  85
  86 static struct smp_operations socfpga_smp_ops __initdata = {
  87         .smp_prepare_cpus       = socfpga_smp_prepare_cpus,
  88         .smp_boot_secondary     = socfpga_boot_secondary,
  89 #ifdef CONFIG_HOTPLUG_CPU
  90         .cpu_die                = socfpga_cpu_die,
  91 #endif
  92 };
  93
  94 CPU_METHOD_OF_DECLARE(socfpga_smp, "altr,socfpga-smp", &socfpga_smp_ops);