arch/arm/mach-spear3xx/spear320.c

   1 /*
   2  * arch/arm/mach-spear3xx/spear320.c
   3  *
   4  * SPEAr320 machine source file
   5  *
   6  * Copyright (C) 2009 ST Microelectronics
   7  * Viresh Kumar<viresh.kumar@st.com>
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #define pr_fmt(fmt) "SPEAr320: " fmt
  15
  16 #include <linux/ptrace.h>
  17 #include <asm/irq.h>
  18 #include <plat/shirq.h>
  19 #include <mach/generic.h>
  20 #include <mach/hardware.h>
  21
  22 /* pad multiplexing support */
  23 /* muxing registers */
  24 #define PAD_MUX_CONFIG_REG      0x0C
  25 #define MODE_CONFIG_REG         0x10
  26
  27 /* modes */
  28 #define AUTO_NET_SMII_MODE      (1 << 0)
  29 #define AUTO_NET_MII_MODE       (1 << 1)
  30 #define AUTO_EXP_MODE           (1 << 2)
  31 #define SMALL_PRINTERS_MODE     (1 << 3)
  32 #define ALL_MODES               0xF
  33
  34 struct pmx_mode spear320_auto_net_smii_mode = {
  35         .id = AUTO_NET_SMII_MODE,
  36         .name = "Automation Networking SMII Mode",
  37         .mask = 0x00,
  38 };
  39
  40 struct pmx_mode spear320_auto_net_mii_mode = {
  41         .id = AUTO_NET_MII_MODE,
  42         .name = "Automation Networking MII Mode",
  43         .mask = 0x01,
  44 };
  45
  46 struct pmx_mode spear320_auto_exp_mode = {
  47         .id = AUTO_EXP_MODE,
  48         .name = "Automation Expanded Mode",
  49         .mask = 0x02,
  50 };
  51
  52 struct pmx_mode spear320_small_printers_mode = {
  53         .id = SMALL_PRINTERS_MODE,
  54         .name = "Small Printers Mode",
  55         .mask = 0x03,
  56 };
  57
  58 /* devices */
  59 static struct pmx_dev_mode pmx_clcd_modes[] = {
  60         {
  61                 .ids = AUTO_NET_SMII_MODE,
  62                 .mask = 0x0,
  63         },
  64 };
  65
  66 struct pmx_dev spear320_pmx_clcd = {
  67         .name = "clcd",
  68         .modes = pmx_clcd_modes,
  69         .mode_count = ARRAY_SIZE(pmx_clcd_modes),
  70         .enb_on_reset = 1,
  71 };
  72
  73 static struct pmx_dev_mode pmx_emi_modes[] = {
  74         {
  75                 .ids = AUTO_EXP_MODE,
  76                 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
  77         },
  78 };
  79
  80 struct pmx_dev spear320_pmx_emi = {
  81         .name = "emi",
  82         .modes = pmx_emi_modes,
  83         .mode_count = ARRAY_SIZE(pmx_emi_modes),
  84         .enb_on_reset = 1,
  85 };
  86
  87 static struct pmx_dev_mode pmx_fsmc_modes[] = {
  88         {
  89                 .ids = ALL_MODES,
  90                 .mask = 0x0,
  91         },
  92 };
  93
  94 struct pmx_dev spear320_pmx_fsmc = {
  95         .name = "fsmc",
  96         .modes = pmx_fsmc_modes,
  97         .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
  98         .enb_on_reset = 1,
  99 };
 100
 101 static struct pmx_dev_mode pmx_spp_modes[] = {
 102         {
 103                 .ids = SMALL_PRINTERS_MODE,
 104                 .mask = 0x0,
 105         },
 106 };
 107
 108 struct pmx_dev spear320_pmx_spp = {
 109         .name = "spp",
 110         .modes = pmx_spp_modes,
 111         .mode_count = ARRAY_SIZE(pmx_spp_modes),
 112         .enb_on_reset = 1,
 113 };
 114
 115 static struct pmx_dev_mode pmx_sdhci_modes[] = {
 116         {
 117                 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |
 118                         SMALL_PRINTERS_MODE,
 119                 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
 120         },
 121 };
 122
 123 struct pmx_dev spear320_pmx_sdhci = {
 124         .name = "sdhci",
 125         .modes = pmx_sdhci_modes,
 126         .mode_count = ARRAY_SIZE(pmx_sdhci_modes),
 127         .enb_on_reset = 1,
 128 };
 129
 130 static struct pmx_dev_mode pmx_i2s_modes[] = {
 131         {
 132                 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
 133                 .mask = PMX_UART0_MODEM_MASK,
 134         },
 135 };
 136
 137 struct pmx_dev spear320_pmx_i2s = {
 138         .name = "i2s",
 139         .modes = pmx_i2s_modes,
 140         .mode_count = ARRAY_SIZE(pmx_i2s_modes),
 141         .enb_on_reset = 1,
 142 };
 143
 144 static struct pmx_dev_mode pmx_uart1_modes[] = {
 145         {
 146                 .ids = ALL_MODES,
 147                 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
 148         },
 149 };
 150
 151 struct pmx_dev spear320_pmx_uart1 = {
 152         .name = "uart1",
 153         .modes = pmx_uart1_modes,
 154         .mode_count = ARRAY_SIZE(pmx_uart1_modes),
 155         .enb_on_reset = 1,
 156 };
 157
 158 static struct pmx_dev_mode pmx_uart1_modem_modes[] = {
 159         {
 160                 .ids = AUTO_EXP_MODE,
 161                 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK |
 162                         PMX_SSP_CS_MASK,
 163         }, {
 164                 .ids = SMALL_PRINTERS_MODE,
 165                 .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
 166                         PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
 167         },
 168 };
 169
 170 struct pmx_dev spear320_pmx_uart1_modem = {
 171         .name = "uart1_modem",
 172         .modes = pmx_uart1_modem_modes,
 173         .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
 174         .enb_on_reset = 1,
 175 };
 176
 177 static struct pmx_dev_mode pmx_uart2_modes[] = {
 178         {
 179                 .ids = ALL_MODES,
 180                 .mask = PMX_FIRDA_MASK,
 181         },
 182 };
 183
 184 struct pmx_dev spear320_pmx_uart2 = {
 185         .name = "uart2",
 186         .modes = pmx_uart2_modes,
 187         .mode_count = ARRAY_SIZE(pmx_uart2_modes),
 188         .enb_on_reset = 1,
 189 };
 190
 191 static struct pmx_dev_mode pmx_touchscreen_modes[] = {
 192         {
 193                 .ids = AUTO_NET_SMII_MODE,
 194                 .mask = PMX_SSP_CS_MASK,
 195         },
 196 };
 197
 198 struct pmx_dev spear320_pmx_touchscreen = {
 199         .name = "touchscreen",
 200         .modes = pmx_touchscreen_modes,
 201         .mode_count = ARRAY_SIZE(pmx_touchscreen_modes),
 202         .enb_on_reset = 1,
 203 };
 204
 205 static struct pmx_dev_mode pmx_can_modes[] = {
 206         {
 207                 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE,
 208                 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
 209                         PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
 210         },
 211 };
 212
 213 struct pmx_dev spear320_pmx_can = {
 214         .name = "can",
 215         .modes = pmx_can_modes,
 216         .mode_count = ARRAY_SIZE(pmx_can_modes),
 217         .enb_on_reset = 1,
 218 };
 219
 220 static struct pmx_dev_mode pmx_sdhci_led_modes[] = {
 221         {
 222                 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
 223                 .mask = PMX_SSP_CS_MASK,
 224         },
 225 };
 226
 227 struct pmx_dev spear320_pmx_sdhci_led = {
 228         .name = "sdhci_led",
 229         .modes = pmx_sdhci_led_modes,
 230         .mode_count = ARRAY_SIZE(pmx_sdhci_led_modes),
 231         .enb_on_reset = 1,
 232 };
 233
 234 static struct pmx_dev_mode pmx_pwm0_modes[] = {
 235         {
 236                 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
 237                 .mask = PMX_UART0_MODEM_MASK,
 238         }, {
 239                 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
 240                 .mask = PMX_MII_MASK,
 241         },
 242 };
 243
 244 struct pmx_dev spear320_pmx_pwm0 = {
 245         .name = "pwm0",
 246         .modes = pmx_pwm0_modes,
 247         .mode_count = ARRAY_SIZE(pmx_pwm0_modes),
 248         .enb_on_reset = 1,
 249 };
 250
 251 static struct pmx_dev_mode pmx_pwm1_modes[] = {
 252         {
 253                 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
 254                 .mask = PMX_UART0_MODEM_MASK,
 255         }, {
 256                 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
 257                 .mask = PMX_MII_MASK,
 258         },
 259 };
 260
 261 struct pmx_dev spear320_pmx_pwm1 = {
 262         .name = "pwm1",
 263         .modes = pmx_pwm1_modes,
 264         .mode_count = ARRAY_SIZE(pmx_pwm1_modes),
 265         .enb_on_reset = 1,
 266 };
 267
 268 static struct pmx_dev_mode pmx_pwm2_modes[] = {
 269         {
 270                 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
 271                 .mask = PMX_SSP_CS_MASK,
 272         }, {
 273                 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
 274                 .mask = PMX_MII_MASK,
 275         },
 276 };
 277
 278 struct pmx_dev spear320_pmx_pwm2 = {
 279         .name = "pwm2",
 280         .modes = pmx_pwm2_modes,
 281         .mode_count = ARRAY_SIZE(pmx_pwm2_modes),
 282         .enb_on_reset = 1,
 283 };
 284
 285 static struct pmx_dev_mode pmx_pwm3_modes[] = {
 286         {
 287                 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
 288                 .mask = PMX_MII_MASK,
 289         },
 290 };
 291
 292 struct pmx_dev spear320_pmx_pwm3 = {
 293         .name = "pwm3",
 294         .modes = pmx_pwm3_modes,
 295         .mode_count = ARRAY_SIZE(pmx_pwm3_modes),
 296         .enb_on_reset = 1,
 297 };
 298
 299 static struct pmx_dev_mode pmx_ssp1_modes[] = {
 300         {
 301                 .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
 302                 .mask = PMX_MII_MASK,
 303         },
 304 };
 305
 306 struct pmx_dev spear320_pmx_ssp1 = {
 307         .name = "ssp1",
 308         .modes = pmx_ssp1_modes,
 309         .mode_count = ARRAY_SIZE(pmx_ssp1_modes),
 310         .enb_on_reset = 1,
 311 };
 312
 313 static struct pmx_dev_mode pmx_ssp2_modes[] = {
 314         {
 315                 .ids = AUTO_NET_SMII_MODE,
 316                 .mask = PMX_MII_MASK,
 317         },
 318 };
 319
 320 struct pmx_dev spear320_pmx_ssp2 = {
 321         .name = "ssp2",
 322         .modes = pmx_ssp2_modes,
 323         .mode_count = ARRAY_SIZE(pmx_ssp2_modes),
 324         .enb_on_reset = 1,
 325 };
 326
 327 static struct pmx_dev_mode pmx_mii1_modes[] = {
 328         {
 329                 .ids = AUTO_NET_MII_MODE,
 330                 .mask = 0x0,
 331         },
 332 };
 333
 334 struct pmx_dev spear320_pmx_mii1 = {
 335         .name = "mii1",
 336         .modes = pmx_mii1_modes,
 337         .mode_count = ARRAY_SIZE(pmx_mii1_modes),
 338         .enb_on_reset = 1,
 339 };
 340
 341 static struct pmx_dev_mode pmx_smii0_modes[] = {
 342         {
 343                 .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
 344                 .mask = PMX_MII_MASK,
 345         },
 346 };
 347
 348 struct pmx_dev spear320_pmx_smii0 = {
 349         .name = "smii0",
 350         .modes = pmx_smii0_modes,
 351         .mode_count = ARRAY_SIZE(pmx_smii0_modes),
 352         .enb_on_reset = 1,
 353 };
 354
 355 static struct pmx_dev_mode pmx_smii1_modes[] = {
 356         {
 357                 .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE,
 358                 .mask = PMX_MII_MASK,
 359         },
 360 };
 361
 362 struct pmx_dev spear320_pmx_smii1 = {
 363         .name = "smii1",
 364         .modes = pmx_smii1_modes,
 365         .mode_count = ARRAY_SIZE(pmx_smii1_modes),
 366         .enb_on_reset = 1,
 367 };
 368
 369 static struct pmx_dev_mode pmx_i2c1_modes[] = {
 370         {
 371                 .ids = AUTO_EXP_MODE,
 372                 .mask = 0x0,
 373         },
 374 };
 375
 376 struct pmx_dev spear320_pmx_i2c1 = {
 377         .name = "i2c1",
 378         .modes = pmx_i2c1_modes,
 379         .mode_count = ARRAY_SIZE(pmx_i2c1_modes),
 380         .enb_on_reset = 1,
 381 };
 382
 383 /* pmx driver structure */
 384 static struct pmx_driver pmx_driver = {
 385         .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007},
 386         .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
 387 };
 388
 389 /* spear3xx shared irq */
 390 static struct shirq_dev_config shirq_ras1_config[] = {
 391         {
 392                 .virq = SPEAR320_VIRQ_EMI,
 393                 .status_mask = SPEAR320_EMI_IRQ_MASK,
 394                 .clear_mask = SPEAR320_EMI_IRQ_MASK,
 395         }, {
 396                 .virq = SPEAR320_VIRQ_CLCD,
 397                 .status_mask = SPEAR320_CLCD_IRQ_MASK,
 398                 .clear_mask = SPEAR320_CLCD_IRQ_MASK,
 399         }, {
 400                 .virq = SPEAR320_VIRQ_SPP,
 401                 .status_mask = SPEAR320_SPP_IRQ_MASK,
 402                 .clear_mask = SPEAR320_SPP_IRQ_MASK,
 403         },
 404 };
 405
 406 static struct spear_shirq shirq_ras1 = {
 407         .irq = SPEAR3XX_IRQ_GEN_RAS_1,
 408         .dev_config = shirq_ras1_config,
 409         .dev_count = ARRAY_SIZE(shirq_ras1_config),
 410         .regs = {
 411                 .enb_reg = -1,
 412                 .status_reg = SPEAR320_INT_STS_MASK_REG,
 413                 .status_reg_mask = SPEAR320_SHIRQ_RAS1_MASK,
 414                 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
 415                 .reset_to_clear = 1,
 416         },
 417 };
 418
 419 static struct shirq_dev_config shirq_ras3_config[] = {
 420         {
 421                 .virq = SPEAR320_VIRQ_PLGPIO,
 422                 .enb_mask = SPEAR320_GPIO_IRQ_MASK,
 423                 .status_mask = SPEAR320_GPIO_IRQ_MASK,
 424                 .clear_mask = SPEAR320_GPIO_IRQ_MASK,
 425         }, {
 426                 .virq = SPEAR320_VIRQ_I2S_PLAY,
 427                 .enb_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
 428                 .status_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
 429                 .clear_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
 430         }, {
 431                 .virq = SPEAR320_VIRQ_I2S_REC,
 432                 .enb_mask = SPEAR320_I2S_REC_IRQ_MASK,
 433                 .status_mask = SPEAR320_I2S_REC_IRQ_MASK,
 434                 .clear_mask = SPEAR320_I2S_REC_IRQ_MASK,
 435         },
 436 };
 437
 438 static struct spear_shirq shirq_ras3 = {
 439         .irq = SPEAR3XX_IRQ_GEN_RAS_3,
 440         .dev_config = shirq_ras3_config,
 441         .dev_count = ARRAY_SIZE(shirq_ras3_config),
 442         .regs = {
 443                 .enb_reg = SPEAR320_INT_ENB_MASK_REG,
 444                 .reset_to_enb = 1,
 445                 .status_reg = SPEAR320_INT_STS_MASK_REG,
 446                 .status_reg_mask = SPEAR320_SHIRQ_RAS3_MASK,
 447                 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
 448                 .reset_to_clear = 1,
 449         },
 450 };
 451
 452 static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
 453         {
 454                 .virq = SPEAR320_VIRQ_CANU,
 455                 .status_mask = SPEAR320_CAN_U_IRQ_MASK,
 456                 .clear_mask = SPEAR320_CAN_U_IRQ_MASK,
 457         }, {
 458                 .virq = SPEAR320_VIRQ_CANL,
 459                 .status_mask = SPEAR320_CAN_L_IRQ_MASK,
 460                 .clear_mask = SPEAR320_CAN_L_IRQ_MASK,
 461         }, {
 462                 .virq = SPEAR320_VIRQ_UART1,
 463                 .status_mask = SPEAR320_UART1_IRQ_MASK,
 464                 .clear_mask = SPEAR320_UART1_IRQ_MASK,
 465         }, {
 466                 .virq = SPEAR320_VIRQ_UART2,
 467                 .status_mask = SPEAR320_UART2_IRQ_MASK,
 468                 .clear_mask = SPEAR320_UART2_IRQ_MASK,
 469         }, {
 470                 .virq = SPEAR320_VIRQ_SSP1,
 471                 .status_mask = SPEAR320_SSP1_IRQ_MASK,
 472                 .clear_mask = SPEAR320_SSP1_IRQ_MASK,
 473         }, {
 474                 .virq = SPEAR320_VIRQ_SSP2,
 475                 .status_mask = SPEAR320_SSP2_IRQ_MASK,
 476                 .clear_mask = SPEAR320_SSP2_IRQ_MASK,
 477         }, {
 478                 .virq = SPEAR320_VIRQ_SMII0,
 479                 .status_mask = SPEAR320_SMII0_IRQ_MASK,
 480                 .clear_mask = SPEAR320_SMII0_IRQ_MASK,
 481         }, {
 482                 .virq = SPEAR320_VIRQ_MII1_SMII1,
 483                 .status_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
 484                 .clear_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
 485         }, {
 486                 .virq = SPEAR320_VIRQ_WAKEUP_SMII0,
 487                 .status_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
 488                 .clear_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
 489         }, {
 490                 .virq = SPEAR320_VIRQ_WAKEUP_MII1_SMII1,
 491                 .status_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
 492                 .clear_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
 493         }, {
 494                 .virq = SPEAR320_VIRQ_I2C1,
 495                 .status_mask = SPEAR320_I2C1_IRQ_MASK,
 496                 .clear_mask = SPEAR320_I2C1_IRQ_MASK,
 497         },
 498 };
 499
 500 static struct spear_shirq shirq_intrcomm_ras = {
 501         .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
 502         .dev_config = shirq_intrcomm_ras_config,
 503         .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
 504         .regs = {
 505                 .enb_reg = -1,
 506                 .status_reg = SPEAR320_INT_STS_MASK_REG,
 507                 .status_reg_mask = SPEAR320_SHIRQ_INTRCOMM_RAS_MASK,
 508                 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
 509                 .reset_to_clear = 1,
 510         },
 511 };
 512
 513 /* Add spear320 specific devices here */
 514
 515 /* spear320 routines */
 516 void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
 517                 u8 pmx_dev_count)
 518 {
 519         void __iomem *base;
 520         int ret = 0;
 521
 522         /* call spear3xx family common init function */
 523         spear3xx_init();
 524
 525         /* shared irq registration */
 526         base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K);
 527         if (base) {
 528                 /* shirq 1 */
 529                 shirq_ras1.regs.base = base;
 530                 ret = spear_shirq_register(&shirq_ras1);
 531                 if (ret)
 532                         pr_err("Error registering Shared IRQ 1\n");
 533
 534                 /* shirq 3 */
 535                 shirq_ras3.regs.base = base;
 536                 ret = spear_shirq_register(&shirq_ras3);
 537                 if (ret)
 538                         pr_err("Error registering Shared IRQ 3\n");
 539
 540                 /* shirq 4 */
 541                 shirq_intrcomm_ras.regs.base = base;
 542                 ret = spear_shirq_register(&shirq_intrcomm_ras);
 543                 if (ret)
 544                         pr_err("Error registering Shared IRQ 4\n");
 545         }
 546
 547         /* pmx initialization */
 548         pmx_driver.base = base;
 549         pmx_driver.mode = pmx_mode;
 550         pmx_driver.devs = pmx_devs;
 551         pmx_driver.devs_count = pmx_dev_count;
 552
 553         ret = pmx_register(&pmx_driver);
 554         if (ret)
 555                 pr_err("padmux: registration failed. err no: %d\n", ret);
 556 }