2 * arch/arm/mach-spear3xx/spear320.c
4 * SPEAr320 machine source file
6 * Copyright (C) 2009-2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #define pr_fmt(fmt) "SPEAr320: " fmt
16 #include <linux/amba/pl022.h>
17 #include <linux/amba/pl08x.h>
18 #include <linux/amba/serial.h>
19 #include <linux/of_platform.h>
20 #include <asm/hardware/vic.h>
21 #include <asm/mach/arch.h>
22 #include <plat/shirq.h>
23 #include <mach/generic.h>
24 #include <mach/spear.h>
26 #define SPEAR320_UART1_BASE UL(0xA3000000)
27 #define SPEAR320_UART2_BASE UL(0xA4000000)
28 #define SPEAR320_SSP0_BASE UL(0xA5000000)
29 #define SPEAR320_SSP1_BASE UL(0xA6000000)
31 /* Interrupt registers offsets and masks */
32 #define SPEAR320_INT_STS_MASK_REG 0x04
33 #define SPEAR320_INT_CLR_MASK_REG 0x04
34 #define SPEAR320_INT_ENB_MASK_REG 0x08
35 #define SPEAR320_GPIO_IRQ_MASK (1 << 0)
36 #define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1)
37 #define SPEAR320_I2S_REC_IRQ_MASK (1 << 2)
38 #define SPEAR320_EMI_IRQ_MASK (1 << 7)
39 #define SPEAR320_CLCD_IRQ_MASK (1 << 8)
40 #define SPEAR320_SPP_IRQ_MASK (1 << 9)
41 #define SPEAR320_SDHCI_IRQ_MASK (1 << 10)
42 #define SPEAR320_CAN_U_IRQ_MASK (1 << 11)
43 #define SPEAR320_CAN_L_IRQ_MASK (1 << 12)
44 #define SPEAR320_UART1_IRQ_MASK (1 << 13)
45 #define SPEAR320_UART2_IRQ_MASK (1 << 14)
46 #define SPEAR320_SSP1_IRQ_MASK (1 << 15)
47 #define SPEAR320_SSP2_IRQ_MASK (1 << 16)
48 #define SPEAR320_SMII0_IRQ_MASK (1 << 17)
49 #define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18)
50 #define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19)
51 #define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20)
52 #define SPEAR320_I2C1_IRQ_MASK (1 << 21)
54 #define SPEAR320_SHIRQ_RAS1_MASK 0x000380
55 #define SPEAR320_SHIRQ_RAS3_MASK 0x000007
56 #define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800
58 /* SPEAr320 Virtual irq definitions */
59 /* IRQs sharing IRQ_GEN_RAS_1 */
60 #define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0)
61 #define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1)
62 #define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2)
64 /* IRQs sharing IRQ_GEN_RAS_2 */
65 #define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2
67 /* IRQs sharing IRQ_GEN_RAS_3 */
68 #define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3)
69 #define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4)
70 #define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5)
72 /* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
73 #define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6)
74 #define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7)
75 #define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
76 #define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
77 #define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10)
78 #define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11)
79 #define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12)
80 #define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13)
81 #define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14)
82 #define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15)
83 #define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16)
85 /* spear3xx shared irq */
86 static struct shirq_dev_config shirq_ras1_config
[] = {
88 .virq
= SPEAR320_VIRQ_EMI
,
89 .status_mask
= SPEAR320_EMI_IRQ_MASK
,
90 .clear_mask
= SPEAR320_EMI_IRQ_MASK
,
92 .virq
= SPEAR320_VIRQ_CLCD
,
93 .status_mask
= SPEAR320_CLCD_IRQ_MASK
,
94 .clear_mask
= SPEAR320_CLCD_IRQ_MASK
,
96 .virq
= SPEAR320_VIRQ_SPP
,
97 .status_mask
= SPEAR320_SPP_IRQ_MASK
,
98 .clear_mask
= SPEAR320_SPP_IRQ_MASK
,
102 static struct spear_shirq shirq_ras1
= {
103 .irq
= SPEAR3XX_IRQ_GEN_RAS_1
,
104 .dev_config
= shirq_ras1_config
,
105 .dev_count
= ARRAY_SIZE(shirq_ras1_config
),
108 .status_reg
= SPEAR320_INT_STS_MASK_REG
,
109 .status_reg_mask
= SPEAR320_SHIRQ_RAS1_MASK
,
110 .clear_reg
= SPEAR320_INT_CLR_MASK_REG
,
115 static struct shirq_dev_config shirq_ras3_config
[] = {
117 .virq
= SPEAR320_VIRQ_PLGPIO
,
118 .enb_mask
= SPEAR320_GPIO_IRQ_MASK
,
119 .status_mask
= SPEAR320_GPIO_IRQ_MASK
,
120 .clear_mask
= SPEAR320_GPIO_IRQ_MASK
,
122 .virq
= SPEAR320_VIRQ_I2S_PLAY
,
123 .enb_mask
= SPEAR320_I2S_PLAY_IRQ_MASK
,
124 .status_mask
= SPEAR320_I2S_PLAY_IRQ_MASK
,
125 .clear_mask
= SPEAR320_I2S_PLAY_IRQ_MASK
,
127 .virq
= SPEAR320_VIRQ_I2S_REC
,
128 .enb_mask
= SPEAR320_I2S_REC_IRQ_MASK
,
129 .status_mask
= SPEAR320_I2S_REC_IRQ_MASK
,
130 .clear_mask
= SPEAR320_I2S_REC_IRQ_MASK
,
134 static struct spear_shirq shirq_ras3
= {
135 .irq
= SPEAR3XX_IRQ_GEN_RAS_3
,
136 .dev_config
= shirq_ras3_config
,
137 .dev_count
= ARRAY_SIZE(shirq_ras3_config
),
139 .enb_reg
= SPEAR320_INT_ENB_MASK_REG
,
141 .status_reg
= SPEAR320_INT_STS_MASK_REG
,
142 .status_reg_mask
= SPEAR320_SHIRQ_RAS3_MASK
,
143 .clear_reg
= SPEAR320_INT_CLR_MASK_REG
,
148 static struct shirq_dev_config shirq_intrcomm_ras_config
[] = {
150 .virq
= SPEAR320_VIRQ_CANU
,
151 .status_mask
= SPEAR320_CAN_U_IRQ_MASK
,
152 .clear_mask
= SPEAR320_CAN_U_IRQ_MASK
,
154 .virq
= SPEAR320_VIRQ_CANL
,
155 .status_mask
= SPEAR320_CAN_L_IRQ_MASK
,
156 .clear_mask
= SPEAR320_CAN_L_IRQ_MASK
,
158 .virq
= SPEAR320_VIRQ_UART1
,
159 .status_mask
= SPEAR320_UART1_IRQ_MASK
,
160 .clear_mask
= SPEAR320_UART1_IRQ_MASK
,
162 .virq
= SPEAR320_VIRQ_UART2
,
163 .status_mask
= SPEAR320_UART2_IRQ_MASK
,
164 .clear_mask
= SPEAR320_UART2_IRQ_MASK
,
166 .virq
= SPEAR320_VIRQ_SSP1
,
167 .status_mask
= SPEAR320_SSP1_IRQ_MASK
,
168 .clear_mask
= SPEAR320_SSP1_IRQ_MASK
,
170 .virq
= SPEAR320_VIRQ_SSP2
,
171 .status_mask
= SPEAR320_SSP2_IRQ_MASK
,
172 .clear_mask
= SPEAR320_SSP2_IRQ_MASK
,
174 .virq
= SPEAR320_VIRQ_SMII0
,
175 .status_mask
= SPEAR320_SMII0_IRQ_MASK
,
176 .clear_mask
= SPEAR320_SMII0_IRQ_MASK
,
178 .virq
= SPEAR320_VIRQ_MII1_SMII1
,
179 .status_mask
= SPEAR320_MII1_SMII1_IRQ_MASK
,
180 .clear_mask
= SPEAR320_MII1_SMII1_IRQ_MASK
,
182 .virq
= SPEAR320_VIRQ_WAKEUP_SMII0
,
183 .status_mask
= SPEAR320_WAKEUP_SMII0_IRQ_MASK
,
184 .clear_mask
= SPEAR320_WAKEUP_SMII0_IRQ_MASK
,
186 .virq
= SPEAR320_VIRQ_WAKEUP_MII1_SMII1
,
187 .status_mask
= SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK
,
188 .clear_mask
= SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK
,
190 .virq
= SPEAR320_VIRQ_I2C1
,
191 .status_mask
= SPEAR320_I2C1_IRQ_MASK
,
192 .clear_mask
= SPEAR320_I2C1_IRQ_MASK
,
196 static struct spear_shirq shirq_intrcomm_ras
= {
197 .irq
= SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
,
198 .dev_config
= shirq_intrcomm_ras_config
,
199 .dev_count
= ARRAY_SIZE(shirq_intrcomm_ras_config
),
202 .status_reg
= SPEAR320_INT_STS_MASK_REG
,
203 .status_reg_mask
= SPEAR320_SHIRQ_INTRCOMM_RAS_MASK
,
204 .clear_reg
= SPEAR320_INT_CLR_MASK_REG
,
209 /* DMAC platform data's slave info */
210 struct pl08x_channel_data spear320_dma_info
[] = {
212 .bus_id
= "uart0_rx",
217 .periph_buses
= PL08X_AHB1
,
219 .bus_id
= "uart0_tx",
224 .periph_buses
= PL08X_AHB1
,
231 .periph_buses
= PL08X_AHB1
,
238 .periph_buses
= PL08X_AHB1
,
245 .periph_buses
= PL08X_AHB1
,
252 .periph_buses
= PL08X_AHB1
,
259 .periph_buses
= PL08X_AHB1
,
266 .periph_buses
= PL08X_AHB1
,
273 .periph_buses
= PL08X_AHB1
,
275 .bus_id
= "from_jpeg",
280 .periph_buses
= PL08X_AHB1
,
287 .periph_buses
= PL08X_AHB2
,
294 .periph_buses
= PL08X_AHB2
,
301 .periph_buses
= PL08X_AHB2
,
308 .periph_buses
= PL08X_AHB2
,
310 .bus_id
= "uart1_rx",
315 .periph_buses
= PL08X_AHB2
,
317 .bus_id
= "uart1_tx",
322 .periph_buses
= PL08X_AHB2
,
324 .bus_id
= "uart2_rx",
329 .periph_buses
= PL08X_AHB2
,
331 .bus_id
= "uart2_tx",
336 .periph_buses
= PL08X_AHB2
,
343 .periph_buses
= PL08X_AHB2
,
350 .periph_buses
= PL08X_AHB2
,
357 .periph_buses
= PL08X_AHB2
,
364 .periph_buses
= PL08X_AHB2
,
371 .periph_buses
= PL08X_AHB2
,
378 .periph_buses
= PL08X_AHB2
,
380 .bus_id
= "rs485_rx",
385 .periph_buses
= PL08X_AHB2
,
387 .bus_id
= "rs485_tx",
392 .periph_buses
= PL08X_AHB2
,
396 static struct pl022_ssp_controller spear320_ssp_data
[] = {
400 .dma_filter
= pl08x_filter_id
,
401 .dma_tx_param
= "ssp1_tx",
402 .dma_rx_param
= "ssp1_rx",
407 .dma_filter
= pl08x_filter_id
,
408 .dma_tx_param
= "ssp2_tx",
409 .dma_rx_param
= "ssp2_rx",
414 static struct amba_pl011_data spear320_uart_data
[] = {
416 .dma_filter
= pl08x_filter_id
,
417 .dma_tx_param
= "uart1_tx",
418 .dma_rx_param
= "uart1_rx",
420 .dma_filter
= pl08x_filter_id
,
421 .dma_tx_param
= "uart2_tx",
422 .dma_rx_param
= "uart2_rx",
426 /* Add SPEAr310 auxdata to pass platform data */
427 static struct of_dev_auxdata spear320_auxdata_lookup
[] __initdata
= {
428 OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE
, NULL
,
430 OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE
, NULL
,
432 OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE
, NULL
,
433 &spear320_ssp_data
[0]),
434 OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE
, NULL
,
435 &spear320_ssp_data
[1]),
436 OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART1_BASE
, NULL
,
437 &spear320_uart_data
[0]),
438 OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART2_BASE
, NULL
,
439 &spear320_uart_data
[1]),
443 static void __init
spear320_dt_init(void)
448 pl080_plat_data
.slave_channels
= spear320_dma_info
;
449 pl080_plat_data
.num_slave_channels
= ARRAY_SIZE(spear320_dma_info
);
451 of_platform_populate(NULL
, of_default_bus_match_table
,
452 spear320_auxdata_lookup
, NULL
);
454 /* shared irq registration */
455 base
= ioremap(SPEAR320_SOC_CONFIG_BASE
, SZ_4K
);
458 shirq_ras1
.regs
.base
= base
;
459 ret
= spear_shirq_register(&shirq_ras1
);
461 pr_err("Error registering Shared IRQ 1\n");
464 shirq_ras3
.regs
.base
= base
;
465 ret
= spear_shirq_register(&shirq_ras3
);
467 pr_err("Error registering Shared IRQ 3\n");
470 shirq_intrcomm_ras
.regs
.base
= base
;
471 ret
= spear_shirq_register(&shirq_intrcomm_ras
);
473 pr_err("Error registering Shared IRQ 4\n");
477 static const char * const spear320_dt_board_compat
[] = {
483 struct map_desc spear320_io_desc
[] __initdata
= {
485 .virtual = VA_SPEAR320_SOC_CONFIG_BASE
,
486 .pfn
= __phys_to_pfn(SPEAR320_SOC_CONFIG_BASE
),
492 static void __init
spear320_map_io(void)
494 iotable_init(spear320_io_desc
, ARRAY_SIZE(spear320_io_desc
));
498 DT_MACHINE_START(SPEAR320_DT
, "ST SPEAr320 SoC with Flattened Device Tree")
499 .map_io
= spear320_map_io
,
500 .init_irq
= spear3xx_dt_init_irq
,
501 .handle_irq
= vic_handle_irq
,
502 .timer
= &spear3xx_timer
,
503 .init_machine
= spear320_dt_init
,
504 .restart
= spear_restart
,
505 .dt_compat
= spear320_dt_board_compat
,