2 * arch/arm/mach-spear3xx/spear3xx.c
4 * SPEAr3XX machines common source file
6 * Copyright (C) 2009-2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #define pr_fmt(fmt) "SPEAr3xx: " fmt
16 #include <linux/amba/pl022.h>
17 #include <linux/amba/pl08x.h>
18 #include <linux/of_irq.h>
20 #include <asm/hardware/pl080.h>
21 #include <asm/hardware/vic.h>
22 #include <plat/pl080.h>
23 #include <mach/generic.h>
24 #include <mach/spear.h>
26 /* ssp device registration */
27 struct pl022_ssp_controller pl022_plat_data
= {
30 .dma_filter
= pl08x_filter_id
,
31 .dma_tx_param
= "ssp0_tx",
32 .dma_rx_param
= "ssp0_rx",
34 * This is number of spi devices that can be connected to spi. There are
35 * two type of chipselects on which slave devices can work. One is chip
36 * select provided by spi masters other is controlled through external
37 * gpio's. We can't use chipselect provided from spi master (because as
38 * soon as FIFO becomes empty, CS is disabled and transfer ends). So
39 * this number now depends on number of gpios available for spi. each
40 * slave on each master requires a separate gpio pin.
45 /* dmac device registration */
46 struct pl08x_platform_data pl080_plat_data
= {
49 .cctl
= (PL080_BSIZE_16
<< PL080_CONTROL_SB_SIZE_SHIFT
| \
50 PL080_BSIZE_16
<< PL080_CONTROL_DB_SIZE_SHIFT
| \
51 PL080_WIDTH_32BIT
<< PL080_CONTROL_SWIDTH_SHIFT
| \
52 PL080_WIDTH_32BIT
<< PL080_CONTROL_DWIDTH_SHIFT
| \
53 PL080_CONTROL_PROT_BUFF
| PL080_CONTROL_PROT_CACHE
| \
54 PL080_CONTROL_PROT_SYS
),
56 .lli_buses
= PL08X_AHB1
,
57 .mem_buses
= PL08X_AHB1
,
58 .get_signal
= pl080_get_signal
,
59 .put_signal
= pl080_put_signal
,
63 * Following will create 16MB static virtual/physical mappings
65 * 0xD0000000 0xFD000000
66 * 0xFC000000 0xFC000000
68 struct map_desc spear3xx_io_desc
[] __initdata
= {
70 .virtual = VA_SPEAR3XX_ICM1_2_BASE
,
71 .pfn
= __phys_to_pfn(SPEAR3XX_ICM1_2_BASE
),
75 .virtual = VA_SPEAR3XX_ICM3_SMI_CTRL_BASE
,
76 .pfn
= __phys_to_pfn(SPEAR3XX_ICM3_SMI_CTRL_BASE
),
82 /* This will create static memory mapping for selected devices */
83 void __init
spear3xx_map_io(void)
85 iotable_init(spear3xx_io_desc
, ARRAY_SIZE(spear3xx_io_desc
));
88 static void __init
spear3xx_timer_init(void)
90 char pclk_name
[] = "pll3_48m_clk";
91 struct clk
*gpt_clk
, *pclk
;
95 /* get the system timer clock */
96 gpt_clk
= clk_get_sys("gpt0", NULL
);
97 if (IS_ERR(gpt_clk
)) {
98 pr_err("%s:couldn't get clk for gpt\n", __func__
);
102 /* get the suitable parent clock for timer*/
103 pclk
= clk_get(NULL
, pclk_name
);
105 pr_err("%s:couldn't get %s as parent for gpt\n",
106 __func__
, pclk_name
);
110 clk_set_parent(gpt_clk
, pclk
);
114 spear_setup_of_timer();
117 struct sys_timer spear3xx_timer
= {
118 .init
= spear3xx_timer_init
,
121 static const struct of_device_id vic_of_match
[] __initconst
= {
122 { .compatible
= "arm,pl190-vic", .data
= vic_of_init
, },
126 void __init
spear3xx_dt_init_irq(void)
128 of_irq_init(vic_of_match
);