arch/arm/mach-tegra/clock.c

   1 /*
   2  *
   3  * Copyright (C) 2010 Google, Inc.
   4  * Copyright (c) 2012 NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * Author:
   7  *      Colin Cross <ccross@google.com>
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/clk.h>
  22 #include <linux/clkdev.h>
  23 #include <linux/init.h>
  24 #include <linux/list.h>
  25 #include <linux/module.h>
  26 #include <linux/sched.h>
  27 #include <linux/seq_file.h>
  28 #include <linux/slab.h>
  29
  30 #include <mach/clk.h>
  31
  32 #include "board.h"
  33 #include "clock.h"
  34
  35 /*
  36  * Locking:
  37  *
  38  * An additional mutex, clock_list_lock, is used to protect the list of all
  39  * clocks.
  40  *
  41  */
  42 static DEFINE_MUTEX(clock_list_lock);
  43 static LIST_HEAD(clocks);
  44
  45 void tegra_clk_add(struct clk *clk)
  46 {
  47         struct clk_tegra *c = to_clk_tegra(__clk_get_hw(clk));
  48
  49         mutex_lock(&clock_list_lock);
  50         list_add(&c->node, &clocks);
  51         mutex_unlock(&clock_list_lock);
  52 }
  53
  54 struct clk *tegra_get_clock_by_name(const char *name)
  55 {
  56         struct clk_tegra *c;
  57         struct clk *ret = NULL;
  58         mutex_lock(&clock_list_lock);
  59         list_for_each_entry(c, &clocks, node) {
  60                 if (strcmp(__clk_get_name(c->hw.clk), name) == 0) {
  61                         ret = c->hw.clk;
  62                         break;
  63                 }
  64         }
  65         mutex_unlock(&clock_list_lock);
  66         return ret;
  67 }
  68
  69 static int tegra_clk_init_one_from_table(struct tegra_clk_init_table *table)
  70 {
  71         struct clk *c;
  72         struct clk *p;
  73         struct clk *parent;
  74
  75         int ret = 0;
  76
  77         c = tegra_get_clock_by_name(table->name);
  78
  79         if (!c) {
  80                 pr_warn("Unable to initialize clock %s\n",
  81                         table->name);
  82                 return -ENODEV;
  83         }
  84
  85         parent = clk_get_parent(c);
  86
  87         if (table->parent) {
  88                 p = tegra_get_clock_by_name(table->parent);
  89                 if (!p) {
  90                         pr_warn("Unable to find parent %s of clock %s\n",
  91                                 table->parent, table->name);
  92                         return -ENODEV;
  93                 }
  94
  95                 if (parent != p) {
  96                         ret = clk_set_parent(c, p);
  97                         if (ret) {
  98                                 pr_warn("Unable to set parent %s of clock %s: %d\n",
  99                                         table->parent, table->name, ret);
 100                                 return -EINVAL;
 101                         }
 102                 }
 103         }
 104
 105         if (table->rate && table->rate != clk_get_rate(c)) {
 106                 ret = clk_set_rate(c, table->rate);
 107                 if (ret) {
 108                         pr_warn("Unable to set clock %s to rate %lu: %d\n",
 109                                 table->name, table->rate, ret);
 110                         return -EINVAL;
 111                 }
 112         }
 113
 114         if (table->enabled) {
 115                 ret = clk_prepare_enable(c);
 116                 if (ret) {
 117                         pr_warn("Unable to enable clock %s: %d\n",
 118                                 table->name, ret);
 119                         return -EINVAL;
 120                 }
 121         }
 122
 123         return 0;
 124 }
 125
 126 void tegra_clk_init_from_table(struct tegra_clk_init_table *table)
 127 {
 128         for (; table->name; table++)
 129                 tegra_clk_init_one_from_table(table);
 130 }
 131
 132 void tegra_periph_reset_deassert(struct clk *c)
 133 {
 134         struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
 135         BUG_ON(!clk->reset);
 136         clk->reset(__clk_get_hw(c), false);
 137 }
 138 EXPORT_SYMBOL(tegra_periph_reset_deassert);
 139
 140 void tegra_periph_reset_assert(struct clk *c)
 141 {
 142         struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
 143         BUG_ON(!clk->reset);
 144         clk->reset(__clk_get_hw(c), true);
 145 }
 146 EXPORT_SYMBOL(tegra_periph_reset_assert);
 147
 148 /* Several extended clock configuration bits (e.g., clock routing, clock
 149  * phase control) are included in PLL and peripheral clock source
 150  * registers. */
 151 int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
 152 {
 153         int ret = 0;
 154         struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
 155
 156         if (!clk->clk_cfg_ex) {
 157                 ret = -ENOSYS;
 158                 goto out;
 159         }
 160         ret = clk->clk_cfg_ex(__clk_get_hw(c), p, setting);
 161
 162 out:
 163         return ret;
 164 }