arch/arm/mach-tegra/clock.h

   1 /*
   2  * arch/arm/mach-tegra/include/mach/clock.h
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  * Copyright (c) 2012 NVIDIA CORPORATION.  All rights reserved.
   6  *
   7  * Author:
   8  *      Colin Cross <ccross@google.com>
   9  *
  10  * This software is licensed under the terms of the GNU General Public
  11  * License version 2, as published by the Free Software Foundation, and
  12  * may be copied, distributed, and modified under those terms.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  */
  20
  21 #ifndef __MACH_TEGRA_CLOCK_H
  22 #define __MACH_TEGRA_CLOCK_H
  23
  24 #include <linux/clk-provider.h>
  25 #include <linux/clkdev.h>
  26 #include <linux/list.h>
  27
  28 #include <mach/clk.h>
  29
  30 #define DIV_BUS                 (1 << 0)
  31 #define DIV_U71                 (1 << 1)
  32 #define DIV_U71_FIXED           (1 << 2)
  33 #define DIV_2                   (1 << 3)
  34 #define DIV_U16                 (1 << 4)
  35 #define PLL_FIXED               (1 << 5)
  36 #define PLL_HAS_CPCON           (1 << 6)
  37 #define MUX                     (1 << 7)
  38 #define PLLD                    (1 << 8)
  39 #define PERIPH_NO_RESET         (1 << 9)
  40 #define PERIPH_NO_ENB           (1 << 10)
  41 #define PERIPH_EMC_ENB          (1 << 11)
  42 #define PERIPH_MANUAL_RESET     (1 << 12)
  43 #define PLL_ALT_MISC_REG        (1 << 13)
  44 #define PLLU                    (1 << 14)
  45 #define PLLX                    (1 << 15)
  46 #define MUX_PWM                 (1 << 16)
  47 #define MUX8                    (1 << 17)
  48 #define DIV_U71_UART            (1 << 18)
  49 #define MUX_CLK_OUT             (1 << 19)
  50 #define PLLM                    (1 << 20)
  51 #define DIV_U71_INT             (1 << 21)
  52 #define DIV_U71_IDLE            (1 << 22)
  53 #define ENABLE_ON_INIT          (1 << 28)
  54 #define PERIPH_ON_APB           (1 << 29)
  55
  56 struct clk_tegra;
  57 #define to_clk_tegra(_hw) container_of(_hw, struct clk_tegra, hw)
  58
  59 struct clk_mux_sel {
  60         struct clk      *input;
  61         u32             value;
  62 };
  63
  64 struct clk_pll_freq_table {
  65         unsigned long   input_rate;
  66         unsigned long   output_rate;
  67         u16             n;
  68         u16             m;
  69         u8              p;
  70         u8              cpcon;
  71 };
  72
  73 enum clk_state {
  74         UNINITIALIZED = 0,
  75         ON,
  76         OFF,
  77 };
  78
  79 struct clk_tegra {
  80         /* node for master clocks list */
  81         struct list_head        node;   /* node for list of all clocks */
  82         struct clk_lookup       lookup;
  83         struct clk_hw           hw;
  84
  85         bool                    set;
  86         unsigned long           fixed_rate;
  87         unsigned long           max_rate;
  88         unsigned long           min_rate;
  89         u32                     flags;
  90         const char              *name;
  91
  92         enum clk_state          state;
  93         u32                     div;
  94         u32                     mul;
  95
  96         u32                             reg;
  97         u32                             reg_shift;
  98
  99         struct list_head                shared_bus_list;
 100
 101         union {
 102                 struct {
 103                         unsigned int                    clk_num;
 104                 } periph;
 105                 struct {
 106                         unsigned long                   input_min;
 107                         unsigned long                   input_max;
 108                         unsigned long                   cf_min;
 109                         unsigned long                   cf_max;
 110                         unsigned long                   vco_min;
 111                         unsigned long                   vco_max;
 112                         const struct clk_pll_freq_table *freq_table;
 113                         int                             lock_delay;
 114                         unsigned long                   fixed_rate;
 115                 } pll;
 116                 struct {
 117                         u32                             sel;
 118                         u32                             reg_mask;
 119                 } mux;
 120                 struct {
 121                         struct clk                      *main;
 122                         struct clk                      *backup;
 123                 } cpu;
 124                 struct {
 125                         struct list_head                node;
 126                         bool                            enabled;
 127                         unsigned long                   rate;
 128                 } shared_bus_user;
 129         } u;
 130
 131         void (*reset)(struct clk_hw *, bool);
 132         int (*clk_cfg_ex)(struct clk_hw *, enum tegra_clk_ex_param, u32);
 133 };
 134
 135 struct clk_duplicate {
 136         const char *name;
 137         struct clk_lookup lookup;
 138 };
 139
 140 struct tegra_clk_init_table {
 141         const char *name;
 142         const char *parent;
 143         unsigned long rate;
 144         bool enabled;
 145 };
 146
 147 void tegra_clk_add(struct clk *c);
 148 void tegra2_init_clocks(void);
 149 void tegra30_init_clocks(void);
 150 struct clk *tegra_get_clock_by_name(const char *name);
 151 void tegra_clk_init_from_table(struct tegra_clk_init_table *table);
 152
 153 #endif