arch/arm/mach-tegra/common.c

   1 /*
   2  * arch/arm/mach-tegra/common.c
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  *
   6  * Author:
   7  *      Colin Cross <ccross@android.com>
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/io.h>
  22 #include <linux/clk.h>
  23 #include <linux/delay.h>
  24 #include <linux/of_irq.h>
  25
  26 #include <asm/hardware/cache-l2x0.h>
  27 #include <asm/hardware/gic.h>
  28
  29 #include <mach/powergate.h>
  30
  31 #include "board.h"
  32 #include "clock.h"
  33 #include "common.h"
  34 #include "fuse.h"
  35 #include "iomap.h"
  36 #include "pmc.h"
  37 #include "apbio.h"
  38 #include "sleep.h"
  39
  40 /*
  41  * Storage for debug-macro.S's state.
  42  *
  43  * This must be in .data not .bss so that it gets initialized each time the
  44  * kernel is loaded. The data is declared here rather than debug-macro.S so
  45  * that multiple inclusions of debug-macro.S point at the same data.
  46  */
  47 u32 tegra_uart_config[3] = {
  48         /* Debug UART initialization required */
  49         1,
  50         /* Debug UART physical address */
  51         0,
  52         /* Debug UART virtual address */
  53         0,
  54 };
  55
  56 #ifdef CONFIG_OF
  57 static const struct of_device_id tegra_dt_irq_match[] __initconst = {
  58         { .compatible = "arm,cortex-a9-gic", .data = gic_of_init },
  59         { }
  60 };
  61
  62 void __init tegra_dt_init_irq(void)
  63 {
  64         tegra_init_irq();
  65         of_irq_init(tegra_dt_irq_match);
  66 }
  67 #endif
  68
  69 void tegra_assert_system_reset(char mode, const char *cmd)
  70 {
  71         void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
  72         u32 reg;
  73
  74         reg = readl_relaxed(reset);
  75         reg |= 0x10;
  76         writel_relaxed(reg, reset);
  77 }
  78
  79 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
  80 static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
  81         /* name         parent          rate            enabled */
  82         { "clk_m",      NULL,           0,              true },
  83         { "pll_p",      "clk_m",        216000000,      true },
  84         { "pll_p_out1", "pll_p",        28800000,       true },
  85         { "pll_p_out2", "pll_p",        48000000,       true },
  86         { "pll_p_out3", "pll_p",        72000000,       true },
  87         { "pll_p_out4", "pll_p",        24000000,       true },
  88         { "pll_c",      "clk_m",        600000000,      true },
  89         { "pll_c_out1", "pll_c",        120000000,      true },
  90         { "sclk",       "pll_c_out1",   120000000,      true },
  91         { "hclk",       "sclk",         120000000,      true },
  92         { "pclk",       "hclk",         60000000,       true },
  93         { "csite",      NULL,           0,              true },
  94         { "emc",        NULL,           0,              true },
  95         { "cpu",        NULL,           0,              true },
  96         { NULL,         NULL,           0,              0},
  97 };
  98 #endif
  99
 100 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
 101 static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = {
 102         /* name         parent          rate            enabled */
 103         { "clk_m",      NULL,           0,              true },
 104         { "pll_p",      "clk_m",        408000000,      true },
 105         { "pll_p_out1", "pll_p",        9600000,        true },
 106         { "pll_p_out4", "pll_p",        102000000,      true },
 107         { "sclk",       "pll_p_out4",   102000000,      true },
 108         { "hclk",       "sclk",         102000000,      true },
 109         { "pclk",       "hclk",         51000000,       true },
 110         { NULL,         NULL,           0,              0},
 111 };
 112 #endif
 113
 114
 115 static void __init tegra_init_cache(void)
 116 {
 117 #ifdef CONFIG_CACHE_L2X0
 118         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
 119         u32 aux_ctrl, cache_type;
 120
 121         cache_type = readl(p + L2X0_CACHE_TYPE);
 122         aux_ctrl = (cache_type & 0x700) << (17-8);
 123         aux_ctrl |= 0x7C400001;
 124
 125         l2x0_of_init(aux_ctrl, 0x8200c3fe);
 126 #endif
 127
 128 }
 129
 130 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
 131 void __init tegra20_init_early(void)
 132 {
 133         tegra_apb_io_init();
 134         tegra_init_fuse();
 135         tegra2_init_clocks();
 136         tegra_clk_init_from_table(tegra20_clk_init_table);
 137         tegra_init_cache();
 138         tegra_pmc_init();
 139         tegra_powergate_init();
 140         tegra20_hotplug_init();
 141 }
 142 #endif
 143 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
 144 void __init tegra30_init_early(void)
 145 {
 146         tegra_apb_io_init();
 147         tegra_init_fuse();
 148         tegra30_init_clocks();
 149         tegra_clk_init_from_table(tegra30_clk_init_table);
 150         tegra_init_cache();
 151         tegra_pmc_init();
 152         tegra_powergate_init();
 153         tegra30_hotplug_init();
 154 }
 155 #endif
 156
 157 void __init tegra_init_late(void)
 158 {
 159         tegra_powergate_debugfs_init();
 160 }