arch/arm/mach-tegra/common.c

   1 /*
   2  * arch/arm/mach-tegra/common.c
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  *
   6  * Author:
   7  *      Colin Cross <ccross@android.com>
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/io.h>
  22 #include <linux/clk.h>
  23 #include <linux/delay.h>
  24 #include <linux/of_irq.h>
  25
  26 #include <asm/hardware/cache-l2x0.h>
  27 #include <asm/hardware/gic.h>
  28
  29 #include <mach/iomap.h>
  30 #include <mach/powergate.h>
  31
  32 #include "board.h"
  33 #include "clock.h"
  34 #include "fuse.h"
  35 #include "pmc.h"
  36 #include "apbio.h"
  37
  38 /*
  39  * Storage for debug-macro.S's state.
  40  *
  41  * This must be in .data not .bss so that it gets initialized each time the
  42  * kernel is loaded. The data is declared here rather than debug-macro.S so
  43  * that multiple inclusions of debug-macro.S point at the same data.
  44  */
  45 #define TEGRA_DEBUG_UART_OFFSET (TEGRA_DEBUG_UART_BASE & 0xFFFF)
  46 u32 tegra_uart_config[3] = {
  47         /* Debug UART initialization required */
  48         1,
  49         /* Debug UART physical address */
  50         (u32)(IO_APB_PHYS + TEGRA_DEBUG_UART_OFFSET),
  51         /* Debug UART virtual address */
  52         (u32)(IO_APB_VIRT + TEGRA_DEBUG_UART_OFFSET),
  53 };
  54
  55 #ifdef CONFIG_OF
  56 static const struct of_device_id tegra_dt_irq_match[] __initconst = {
  57         { .compatible = "arm,cortex-a9-gic", .data = gic_of_init },
  58         { }
  59 };
  60
  61 void __init tegra_dt_init_irq(void)
  62 {
  63         tegra_init_irq();
  64         of_irq_init(tegra_dt_irq_match);
  65 }
  66 #endif
  67
  68 void tegra_assert_system_reset(char mode, const char *cmd)
  69 {
  70         void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
  71         u32 reg;
  72
  73         reg = readl_relaxed(reset);
  74         reg |= 0x10;
  75         writel_relaxed(reg, reset);
  76 }
  77
  78 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
  79 static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
  80         /* name         parent          rate            enabled */
  81         { "clk_m",      NULL,           0,              true },
  82         { "pll_p",      "clk_m",        216000000,      true },
  83         { "pll_p_out1", "pll_p",        28800000,       true },
  84         { "pll_p_out2", "pll_p",        48000000,       true },
  85         { "pll_p_out3", "pll_p",        72000000,       true },
  86         { "pll_p_out4", "pll_p",        24000000,       true },
  87         { "pll_c",      "clk_m",        600000000,      true },
  88         { "pll_c_out1", "pll_c",        120000000,      true },
  89         { "sclk",       "pll_c_out1",   120000000,      true },
  90         { "hclk",       "sclk",         120000000,      true },
  91         { "pclk",       "hclk",         60000000,       true },
  92         { "csite",      NULL,           0,              true },
  93         { "emc",        NULL,           0,              true },
  94         { "cpu",        NULL,           0,              true },
  95         { NULL,         NULL,           0,              0},
  96 };
  97 #endif
  98
  99 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
 100 static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = {
 101         /* name         parent          rate            enabled */
 102         { "clk_m",      NULL,           0,              true },
 103         { "pll_p",      "clk_m",        408000000,      true },
 104         { "pll_p_out1", "pll_p",        9600000,        true },
 105         { NULL,         NULL,           0,              0},
 106 };
 107 #endif
 108
 109
 110 static void __init tegra_init_cache(u32 tag_latency, u32 data_latency)
 111 {
 112 #ifdef CONFIG_CACHE_L2X0
 113         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
 114         u32 aux_ctrl, cache_type;
 115
 116         writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
 117         writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
 118
 119         cache_type = readl(p + L2X0_CACHE_TYPE);
 120         aux_ctrl = (cache_type & 0x700) << (17-8);
 121         aux_ctrl |= 0x6C000001;
 122
 123         l2x0_init(p, aux_ctrl, 0x8200c3fe);
 124 #endif
 125
 126 }
 127
 128 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
 129 void __init tegra20_init_early(void)
 130 {
 131         tegra_apb_io_init();
 132         tegra_init_fuse();
 133         tegra2_init_clocks();
 134         tegra_clk_init_from_table(tegra20_clk_init_table);
 135         tegra_init_cache(0x331, 0x441);
 136         tegra_pmc_init();
 137         tegra_powergate_init();
 138 }
 139 #endif
 140 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
 141 void __init tegra30_init_early(void)
 142 {
 143         tegra_apb_io_init();
 144         tegra_init_fuse();
 145         tegra30_init_clocks();
 146         tegra_clk_init_from_table(tegra30_clk_init_table);
 147         tegra_init_cache(0x441, 0x551);
 148         tegra_pmc_init();
 149         tegra_powergate_init();
 150 }
 151 #endif
 152
 153 void __init tegra_init_late(void)
 154 {
 155         tegra_clk_debugfs_init();
 156         tegra_powergate_debugfs_init();
 157 }