arch/arm/mach-tegra/fuse.c

   1 /*
   2  * arch/arm/mach-tegra/fuse.c
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  *
   6  * Author:
   7  *      Colin Cross <ccross@android.com>
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/io.h>
  22 #include <linux/export.h>
  23
  24 #include "fuse.h"
  25 #include "iomap.h"
  26 #include "apbio.h"
  27
  28 #define FUSE_UID_LOW            0x108
  29 #define FUSE_UID_HIGH           0x10c
  30 #define FUSE_SKU_INFO           0x110
  31
  32 #define TEGRA20_FUSE_SPARE_BIT          0x200
  33 #define TEGRA30_FUSE_SPARE_BIT          0x244
  34
  35 int tegra_sku_id;
  36 int tegra_cpu_process_id;
  37 int tegra_core_process_id;
  38 int tegra_chip_id;
  39 int tegra_cpu_speedo_id;                /* only exist in Tegra30 and later */
  40 int tegra_soc_speedo_id;
  41 enum tegra_revision tegra_revision;
  42
  43 static int tegra_fuse_spare_bit;
  44 static void (*tegra_init_speedo_data)(void);
  45
  46 /* The BCT to use at boot is specified by board straps that can be read
  47  * through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs.
  48  */
  49 int tegra_bct_strapping;
  50
  51 #define STRAP_OPT 0x008
  52 #define GMI_AD0 (1 << 4)
  53 #define GMI_AD1 (1 << 5)
  54 #define RAM_ID_MASK (GMI_AD0 | GMI_AD1)
  55 #define RAM_CODE_SHIFT 4
  56
  57 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
  58         [TEGRA_REVISION_UNKNOWN] = "unknown",
  59         [TEGRA_REVISION_A01]     = "A01",
  60         [TEGRA_REVISION_A02]     = "A02",
  61         [TEGRA_REVISION_A03]     = "A03",
  62         [TEGRA_REVISION_A03p]    = "A03 prime",
  63         [TEGRA_REVISION_A04]     = "A04",
  64 };
  65
  66 u32 tegra_fuse_readl(unsigned long offset)
  67 {
  68         return tegra_apb_readl(TEGRA_FUSE_BASE + offset);
  69 }
  70
  71 bool tegra_spare_fuse(int bit)
  72 {
  73         return tegra_fuse_readl(tegra_fuse_spare_bit + bit * 4);
  74 }
  75
  76 static enum tegra_revision tegra_get_revision(u32 id)
  77 {
  78         u32 minor_rev = (id >> 16) & 0xf;
  79
  80         switch (minor_rev) {
  81         case 1:
  82                 return TEGRA_REVISION_A01;
  83         case 2:
  84                 return TEGRA_REVISION_A02;
  85         case 3:
  86                 if (tegra_chip_id == TEGRA20 &&
  87                         (tegra_spare_fuse(18) || tegra_spare_fuse(19)))
  88                         return TEGRA_REVISION_A03p;
  89                 else
  90                         return TEGRA_REVISION_A03;
  91         case 4:
  92                 return TEGRA_REVISION_A04;
  93         default:
  94                 return TEGRA_REVISION_UNKNOWN;
  95         }
  96 }
  97
  98 static void tegra_get_process_id(void)
  99 {
 100         u32 reg;
 101
 102         reg = tegra_fuse_readl(tegra_fuse_spare_bit);
 103         tegra_cpu_process_id = (reg >> 6) & 3;
 104         reg = tegra_fuse_readl(tegra_fuse_spare_bit);
 105         tegra_core_process_id = (reg >> 12) & 3;
 106 }
 107
 108 void tegra_init_fuse(void)
 109 {
 110         u32 id;
 111
 112         u32 reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
 113         reg |= 1 << 28;
 114         writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
 115
 116         reg = tegra_fuse_readl(FUSE_SKU_INFO);
 117         tegra_sku_id = reg & 0xFF;
 118
 119         reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
 120         tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
 121
 122         id = readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
 123         tegra_chip_id = (id >> 8) & 0xff;
 124
 125         switch (tegra_chip_id) {
 126         case TEGRA20:
 127                 tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
 128                 tegra_init_speedo_data = &tegra20_init_speedo_data;
 129                 break;
 130         case TEGRA30:
 131                 tegra_fuse_spare_bit = TEGRA30_FUSE_SPARE_BIT;
 132                 tegra_init_speedo_data = &tegra30_init_speedo_data;
 133                 break;
 134         default:
 135                 pr_warn("Tegra: unknown chip id %d\n", tegra_chip_id);
 136                 tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
 137                 tegra_init_speedo_data = &tegra_get_process_id;
 138         }
 139
 140         tegra_revision = tegra_get_revision(id);
 141         tegra_init_speedo_data();
 142
 143         pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
 144                 tegra_revision_name[tegra_revision],
 145                 tegra_sku_id, tegra_cpu_process_id,
 146                 tegra_core_process_id);
 147 }
 148
 149 unsigned long long tegra_chip_uid(void)
 150 {
 151         unsigned long long lo, hi;
 152
 153         lo = tegra_fuse_readl(FUSE_UID_LOW);
 154         hi = tegra_fuse_readl(FUSE_UID_HIGH);
 155         return (hi << 32ull) | lo;
 156 }
 157 EXPORT_SYMBOL(tegra_chip_uid);