arch/arm/mach-tegra/include/mach/dma.h

   1 /*
   2  * arch/arm/mach-tegra/include/mach/dma.h
   3  *
   4  * Copyright (c) 2008-2009, NVIDIA Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along
  17  * with this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  19  */
  20
  21 #ifndef __MACH_TEGRA_DMA_H
  22 #define __MACH_TEGRA_DMA_H
  23
  24 #include <linux/list.h>
  25
  26 #define TEGRA_DMA_REQ_SEL_CNTR                  0
  27 #define TEGRA_DMA_REQ_SEL_I2S_2                 1
  28 #define TEGRA_DMA_REQ_SEL_I2S_1                 2
  29 #define TEGRA_DMA_REQ_SEL_SPD_I                 3
  30 #define TEGRA_DMA_REQ_SEL_UI_I                  4
  31 #define TEGRA_DMA_REQ_SEL_MIPI                  5
  32 #define TEGRA_DMA_REQ_SEL_I2S2_2                6
  33 #define TEGRA_DMA_REQ_SEL_I2S2_1                7
  34 #define TEGRA_DMA_REQ_SEL_UARTA                 8
  35 #define TEGRA_DMA_REQ_SEL_UARTB                 9
  36 #define TEGRA_DMA_REQ_SEL_UARTC                 10
  37 #define TEGRA_DMA_REQ_SEL_SPI                   11
  38 #define TEGRA_DMA_REQ_SEL_AC97                  12
  39 #define TEGRA_DMA_REQ_SEL_ACMODEM               13
  40 #define TEGRA_DMA_REQ_SEL_SL4B                  14
  41 #define TEGRA_DMA_REQ_SEL_SL2B1                 15
  42 #define TEGRA_DMA_REQ_SEL_SL2B2                 16
  43 #define TEGRA_DMA_REQ_SEL_SL2B3                 17
  44 #define TEGRA_DMA_REQ_SEL_SL2B4                 18
  45 #define TEGRA_DMA_REQ_SEL_UARTD                 19
  46 #define TEGRA_DMA_REQ_SEL_UARTE                 20
  47 #define TEGRA_DMA_REQ_SEL_I2C                   21
  48 #define TEGRA_DMA_REQ_SEL_I2C2                  22
  49 #define TEGRA_DMA_REQ_SEL_I2C3                  23
  50 #define TEGRA_DMA_REQ_SEL_DVC_I2C               24
  51 #define TEGRA_DMA_REQ_SEL_OWR                   25
  52 #define TEGRA_DMA_REQ_SEL_INVALID               31
  53
  54 struct tegra_dma_req;
  55 struct tegra_dma_channel;
  56
  57 enum tegra_dma_mode {
  58         TEGRA_DMA_SHARED = 1,
  59         TEGRA_DMA_MODE_CONTINOUS = 2,
  60         TEGRA_DMA_MODE_ONESHOT = 4,
  61 };
  62
  63 enum tegra_dma_req_error {
  64         TEGRA_DMA_REQ_SUCCESS = 0,
  65         TEGRA_DMA_REQ_ERROR_ABORTED,
  66         TEGRA_DMA_REQ_INFLIGHT,
  67 };
  68
  69 enum tegra_dma_req_buff_status {
  70         TEGRA_DMA_REQ_BUF_STATUS_EMPTY = 0,
  71         TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL,
  72         TEGRA_DMA_REQ_BUF_STATUS_FULL,
  73 };
  74
  75 struct tegra_dma_req {
  76         struct list_head node;
  77         unsigned int modid;
  78         int instance;
  79
  80         /* Called when the req is complete and from the DMA ISR context.
  81          * When this is called the req structure is no longer queued by
  82          * the DMA channel.
  83          *
  84          * State of the DMA depends on the number of req it has. If there are
  85          * no DMA requests queued up, then it will STOP the DMA. It there are
  86          * more requests in the DMA, then it will queue the next request.
  87          */
  88         void (*complete)(struct tegra_dma_req *req);
  89
  90         /*  This is a called from the DMA ISR context when the DMA is still in
  91          *  progress and is actively filling same buffer.
  92          *
  93          *  In case of continuous mode receive, this threshold is 1/2 the buffer
  94          *  size. In other cases, this will not even be called as there is no
  95          *  hardware support for it.
  96          *
  97          * In the case of continuous mode receive, if there is next req already
  98          * queued, DMA programs the HW to use that req when this req is
  99          * completed. If there is no "next req" queued, then DMA ISR doesn't do
 100          * anything before calling this callback.
 101          *
 102          *      This is mainly used by the cases, where the clients has queued
 103          *      only one req and want to get some sort of DMA threshold
 104          *      callback to program the next buffer.
 105          *
 106          */
 107         void (*threshold)(struct tegra_dma_req *req);
 108
 109         /* 1 to copy to memory.
 110          * 0 to copy from the memory to device FIFO */
 111         int to_memory;
 112
 113         void *virt_addr;
 114
 115         unsigned long source_addr;
 116         unsigned long dest_addr;
 117         unsigned long dest_wrap;
 118         unsigned long source_wrap;
 119         unsigned long source_bus_width;
 120         unsigned long dest_bus_width;
 121         unsigned long req_sel;
 122         unsigned int size;
 123
 124         /* Updated by the DMA driver on the conpletion of the request. */
 125         int bytes_transferred;
 126         int status;
 127
 128         /* DMA completion tracking information */
 129         int buffer_status;
 130
 131         /* Client specific data */
 132         void *dev;
 133 };
 134
 135 int tegra_dma_enqueue_req(struct tegra_dma_channel *ch,
 136         struct tegra_dma_req *req);
 137 int tegra_dma_dequeue_req(struct tegra_dma_channel *ch,
 138         struct tegra_dma_req *req);
 139 void tegra_dma_dequeue(struct tegra_dma_channel *ch);
 140 void tegra_dma_flush(struct tegra_dma_channel *ch);
 141
 142 bool tegra_dma_is_req_inflight(struct tegra_dma_channel *ch,
 143         struct tegra_dma_req *req);
 144 bool tegra_dma_is_empty(struct tegra_dma_channel *ch);
 145
 146 struct tegra_dma_channel *tegra_dma_allocate_channel(int mode);
 147 void tegra_dma_free_channel(struct tegra_dma_channel *ch);
 148
 149 int __init tegra_dma_init(void);
 150
 151 #endif