2 * Copyright (C) 2011 Google, Inc.
5 * Colin Cross <ccross@android.com>
7 * Copyright (C) 2010, NVIDIA Corporation
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/kernel.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
26 #include <asm/hardware/gic.h>
28 #include <mach/iomap.h>
32 #define ICTLR_CPU_IEP_VFIQ 0x08
33 #define ICTLR_CPU_IEP_FIR 0x14
34 #define ICTLR_CPU_IEP_FIR_SET 0x18
35 #define ICTLR_CPU_IEP_FIR_CLR 0x1c
37 #define ICTLR_CPU_IER 0x20
38 #define ICTLR_CPU_IER_SET 0x24
39 #define ICTLR_CPU_IER_CLR 0x28
40 #define ICTLR_CPU_IEP_CLASS 0x2C
42 #define ICTLR_COP_IER 0x30
43 #define ICTLR_COP_IER_SET 0x34
44 #define ICTLR_COP_IER_CLR 0x38
45 #define ICTLR_COP_IEP_CLASS 0x3c
47 #define FIRST_LEGACY_IRQ 32
49 static int num_ictlrs
;
51 static void __iomem
*ictlr_reg_base
[] = {
52 IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE
),
53 IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE
),
54 IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE
),
55 IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE
),
56 IO_ADDRESS(TEGRA_QUINARY_ICTLR_BASE
),
59 static inline void tegra_irq_write_mask(unsigned int irq
, unsigned long reg
)
64 BUG_ON(irq
< FIRST_LEGACY_IRQ
||
65 irq
>= FIRST_LEGACY_IRQ
+ num_ictlrs
* 32);
67 base
= ictlr_reg_base
[(irq
- FIRST_LEGACY_IRQ
) / 32];
68 mask
= BIT((irq
- FIRST_LEGACY_IRQ
) % 32);
70 __raw_writel(mask
, base
+ reg
);
73 static void tegra_mask(struct irq_data
*d
)
75 if (d
->irq
< FIRST_LEGACY_IRQ
)
78 tegra_irq_write_mask(d
->irq
, ICTLR_CPU_IER_CLR
);
81 static void tegra_unmask(struct irq_data
*d
)
83 if (d
->irq
< FIRST_LEGACY_IRQ
)
86 tegra_irq_write_mask(d
->irq
, ICTLR_CPU_IER_SET
);
89 static void tegra_ack(struct irq_data
*d
)
91 if (d
->irq
< FIRST_LEGACY_IRQ
)
94 tegra_irq_write_mask(d
->irq
, ICTLR_CPU_IEP_FIR_CLR
);
97 static void tegra_eoi(struct irq_data
*d
)
99 if (d
->irq
< FIRST_LEGACY_IRQ
)
102 tegra_irq_write_mask(d
->irq
, ICTLR_CPU_IEP_FIR_CLR
);
105 static int tegra_retrigger(struct irq_data
*d
)
107 if (d
->irq
< FIRST_LEGACY_IRQ
)
110 tegra_irq_write_mask(d
->irq
, ICTLR_CPU_IEP_FIR_SET
);
115 void __init
tegra_init_irq(void)
118 void __iomem
*distbase
;
120 distbase
= IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE
);
121 num_ictlrs
= readl_relaxed(distbase
+ GIC_DIST_CTR
) & 0x1f;
123 if (num_ictlrs
> ARRAY_SIZE(ictlr_reg_base
)) {
124 WARN(1, "Too many (%d) interrupt controllers found. Maximum is %d.",
125 num_ictlrs
, ARRAY_SIZE(ictlr_reg_base
));
126 num_ictlrs
= ARRAY_SIZE(ictlr_reg_base
);
129 for (i
= 0; i
< num_ictlrs
; i
++) {
130 void __iomem
*ictlr
= ictlr_reg_base
[i
];
131 writel(~0, ictlr
+ ICTLR_CPU_IER_CLR
);
132 writel(0, ictlr
+ ICTLR_CPU_IEP_CLASS
);
135 gic_arch_extn
.irq_ack
= tegra_ack
;
136 gic_arch_extn
.irq_eoi
= tegra_eoi
;
137 gic_arch_extn
.irq_mask
= tegra_mask
;
138 gic_arch_extn
.irq_unmask
= tegra_unmask
;
139 gic_arch_extn
.irq_retrigger
= tegra_retrigger
;
142 * Check if there is a devicetree present, since the GIC will be
143 * initialized elsewhere under DT.
145 if (!of_have_populated_dt())
146 gic_init(0, 29, distbase
,
147 IO_ADDRESS(TEGRA_ARM_PERIF_BASE
+ 0x100));