arch/arm/mach-tegra/reset-handler.S

   1 /*
   2  * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/linkage.h>
  18 #include <linux/init.h>
  19
  20 #include <asm/cache.h>
  21 #include <asm/asm-offsets.h>
  22 #include <asm/hardware/cache-l2x0.h>
  23
  24 #include "flowctrl.h"
  25 #include "iomap.h"
  26 #include "reset.h"
  27 #include "sleep.h"
  28
  29 #define APB_MISC_GP_HIDREV      0x804
  30 #define PMC_SCRATCH41   0x140
  31
  32 #define RESET_DATA(x)   ((TEGRA_RESET_##x)*4)
  33
  34 #ifdef CONFIG_PM_SLEEP
  35 /*
  36  *      tegra_resume
  37  *
  38  *        CPU boot vector when restarting the a CPU following
  39  *        an LP2 transition. Also branched to by LP0 and LP1 resume after
  40  *        re-enabling sdram.
  41  */
  42 ENTRY(tegra_resume)
  43         bl      v7_invalidate_l1
  44         /* Enable coresight */
  45         mov32   r0, 0xC5ACCE55
  46         mcr     p14, 0, r0, c7, c12, 6
  47
  48         cpu_id  r0
  49         cmp     r0, #0                          @ CPU0?
  50         bne     cpu_resume                      @ no
  51
  52 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
  53         /* Are we on Tegra20? */
  54         mov32   r6, TEGRA_APB_MISC_BASE
  55         ldr     r0, [r6, #APB_MISC_GP_HIDREV]
  56         and     r0, r0, #0xff00
  57         cmp     r0, #(0x20 << 8)
  58         beq     1f                              @ Yes
  59         /* Clear the flow controller flags for this CPU. */
  60         mov32   r2, TEGRA_FLOW_CTRL_BASE + FLOW_CTRL_CPU0_CSR   @ CPU0 CSR
  61         ldr     r1, [r2]
  62         /* Clear event & intr flag */
  63         orr     r1, r1, \
  64                 #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
  65         movw    r0, #0x0FFD     @ enable, cluster_switch, immed, & bitmaps
  66         bic     r1, r1, r0
  67         str     r1, [r2]
  68 1:
  69 #endif
  70
  71 #ifdef CONFIG_HAVE_ARM_SCU
  72         /* enable SCU */
  73         mov32   r0, TEGRA_ARM_PERIF_BASE
  74         ldr     r1, [r0]
  75         orr     r1, r1, #1
  76         str     r1, [r0]
  77 #endif
  78
  79         /* L2 cache resume & re-enable */
  80         l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr
  81
  82         b       cpu_resume
  83 ENDPROC(tegra_resume)
  84 #endif
  85
  86 #ifdef CONFIG_CACHE_L2X0
  87         .globl  l2x0_saved_regs_addr
  88 l2x0_saved_regs_addr:
  89         .long   0
  90 #endif
  91
  92         .align L1_CACHE_SHIFT
  93 ENTRY(__tegra_cpu_reset_handler_start)
  94
  95 /*
  96  * __tegra_cpu_reset_handler:
  97  *
  98  * Common handler for all CPU reset events.
  99  *
 100  * Register usage within the reset handler:
 101  *
 102  *      Others: scratch
 103  *      R6  = SoC ID << 8
 104  *      R7  = CPU present (to the OS) mask
 105  *      R8  = CPU in LP1 state mask
 106  *      R9  = CPU in LP2 state mask
 107  *      R10 = CPU number
 108  *      R11 = CPU mask
 109  *      R12 = pointer to reset handler data
 110  *
 111  * NOTE: This code is copied to IRAM. All code and data accesses
 112  *       must be position-independent.
 113  */
 114
 115         .align L1_CACHE_SHIFT
 116 ENTRY(__tegra_cpu_reset_handler)
 117
 118         cpsid   aif, 0x13                       @ SVC mode, interrupts disabled
 119
 120         mov32   r6, TEGRA_APB_MISC_BASE
 121         ldr     r6, [r6, #APB_MISC_GP_HIDREV]
 122         and     r6, r6, #0xff00
 123 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
 124 t20_check:
 125         cmp     r6, #(0x20 << 8)
 126         bne     after_t20_check
 127 t20_errata:
 128         # Tegra20 is a Cortex-A9 r1p1
 129         mrc     p15, 0, r0, c1, c0, 0   @ read system control register
 130         orr     r0, r0, #1 << 14        @ erratum 716044
 131         mcr     p15, 0, r0, c1, c0, 0   @ write system control register
 132         mrc     p15, 0, r0, c15, c0, 1  @ read diagnostic register
 133         orr     r0, r0, #1 << 4         @ erratum 742230
 134         orr     r0, r0, #1 << 11        @ erratum 751472
 135         mcr     p15, 0, r0, c15, c0, 1  @ write diagnostic register
 136         b       after_errata
 137 after_t20_check:
 138 #endif
 139 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
 140 t30_check:
 141         cmp     r6, #(0x30 << 8)
 142         bne     after_t30_check
 143 t30_errata:
 144         # Tegra30 is a Cortex-A9 r2p9
 145         mrc     p15, 0, r0, c15, c0, 1  @ read diagnostic register
 146         orr     r0, r0, #1 << 6         @ erratum 743622
 147         orr     r0, r0, #1 << 11        @ erratum 751472
 148         mcr     p15, 0, r0, c15, c0, 1  @ write diagnostic register
 149         b       after_errata
 150 after_t30_check:
 151 #endif
 152 after_errata:
 153         mrc     p15, 0, r10, c0, c0, 5          @ MPIDR
 154         and     r10, r10, #0x3                  @ R10 = CPU number
 155         mov     r11, #1
 156         mov     r11, r11, lsl r10               @ R11 = CPU mask
 157         adr     r12, __tegra_cpu_reset_handler_data
 158
 159 #ifdef CONFIG_SMP
 160         /* Does the OS know about this CPU? */
 161         ldr     r7, [r12, #RESET_DATA(MASK_PRESENT)]
 162         tst     r7, r11                         @ if !present
 163         bleq    __die                           @ CPU not present (to OS)
 164 #endif
 165
 166 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
 167         /* Are we on Tegra20? */
 168         cmp     r6, #(0x20 << 8)
 169         bne     1f
 170         /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
 171         mov32   r5, TEGRA_PMC_BASE
 172         mov     r0, #0
 173         cmp     r10, #0
 174         strne   r0, [r5, #PMC_SCRATCH41]
 175 1:
 176 #endif
 177
 178         /* Waking up from LP2? */
 179         ldr     r9, [r12, #RESET_DATA(MASK_LP2)]
 180         tst     r9, r11                         @ if in_lp2
 181         beq     __is_not_lp2
 182         ldr     lr, [r12, #RESET_DATA(STARTUP_LP2)]
 183         cmp     lr, #0
 184         bleq    __die                           @ no LP2 startup handler
 185         bx      lr
 186
 187 __is_not_lp2:
 188
 189 #ifdef CONFIG_SMP
 190         /*
 191          * Can only be secondary boot (initial or hotplug) but CPU 0
 192          * cannot be here.
 193          */
 194         cmp     r10, #0
 195         bleq    __die                           @ CPU0 cannot be here
 196         ldr     lr, [r12, #RESET_DATA(STARTUP_SECONDARY)]
 197         cmp     lr, #0
 198         bleq    __die                           @ no secondary startup handler
 199         bx      lr
 200 #endif
 201
 202 /*
 203  * We don't know why the CPU reset. Just kill it.
 204  * The LR register will contain the address we died at + 4.
 205  */
 206
 207 __die:
 208         sub     lr, lr, #4
 209         mov32   r7, TEGRA_PMC_BASE
 210         str     lr, [r7, #PMC_SCRATCH41]
 211
 212         mov32   r7, TEGRA_CLK_RESET_BASE
 213
 214         /* Are we on Tegra20? */
 215         mov32   r6, TEGRA_APB_MISC_BASE
 216         ldr     r0, [r6, #APB_MISC_GP_HIDREV]
 217         and     r0, r0, #0xff00
 218         cmp     r0, #(0x20 << 8)
 219         bne     1f
 220
 221 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
 222         mov32   r0, 0x1111
 223         mov     r1, r0, lsl r10
 224         str     r1, [r7, #0x340]                @ CLK_RST_CPU_CMPLX_SET
 225 #endif
 226 1:
 227 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
 228         mov32   r6, TEGRA_FLOW_CTRL_BASE
 229
 230         cmp     r10, #0
 231         moveq   r1, #FLOW_CTRL_HALT_CPU0_EVENTS
 232         moveq   r2, #FLOW_CTRL_CPU0_CSR
 233         movne   r1, r10, lsl #3
 234         addne   r2, r1, #(FLOW_CTRL_CPU1_CSR-8)
 235         addne   r1, r1, #(FLOW_CTRL_HALT_CPU1_EVENTS-8)
 236
 237         /* Clear CPU "event" and "interrupt" flags and power gate
 238            it when halting but not before it is in the "WFI" state. */
 239         ldr     r0, [r6, +r2]
 240         orr     r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
 241         orr     r0, r0, #FLOW_CTRL_CSR_ENABLE
 242         str     r0, [r6, +r2]
 243
 244         /* Unconditionally halt this CPU */
 245         mov     r0, #FLOW_CTRL_WAITEVENT
 246         str     r0, [r6, +r1]
 247         ldr     r0, [r6, +r1]                   @ memory barrier
 248
 249         dsb
 250         isb
 251         wfi                                     @ CPU should be power gated here
 252
 253         /* If the CPU didn't power gate above just kill it's clock. */
 254
 255         mov     r0, r11, lsl #8
 256         str     r0, [r7, #348]                  @ CLK_CPU_CMPLX_SET
 257 #endif
 258
 259         /* If the CPU still isn't dead, just spin here. */
 260         b       .
 261 ENDPROC(__tegra_cpu_reset_handler)
 262
 263         .align L1_CACHE_SHIFT
 264         .type   __tegra_cpu_reset_handler_data, %object
 265         .globl  __tegra_cpu_reset_handler_data
 266 __tegra_cpu_reset_handler_data:
 267         .rept   TEGRA_RESET_DATA_SIZE
 268         .long   0
 269         .endr
 270         .align L1_CACHE_SHIFT
 271
 272 ENTRY(__tegra_cpu_reset_handler_end)