arch/arm/mach-tegra/reset.c

   1 /*
   2  * arch/arm/mach-tegra/reset.c
   3  *
   4  * Copyright (C) 2011,2012 NVIDIA Corporation.
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/init.h>
  18 #include <linux/io.h>
  19 #include <linux/cpumask.h>
  20 #include <linux/bitops.h>
  21
  22 #include <asm/cacheflush.h>
  23 #include <asm/hardware/cache-l2x0.h>
  24
  25 #include "iomap.h"
  26 #include "irammap.h"
  27 #include "reset.h"
  28 #include "fuse.h"
  29
  30 #define TEGRA_IRAM_RESET_BASE (TEGRA_IRAM_BASE + \
  31                                 TEGRA_IRAM_RESET_HANDLER_OFFSET)
  32
  33 static bool is_enabled;
  34
  35 static void __init tegra_cpu_reset_handler_enable(void)
  36 {
  37         void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE);
  38         void __iomem *evp_cpu_reset =
  39                 IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE + 0x100);
  40         void __iomem *sb_ctrl = IO_ADDRESS(TEGRA_SB_BASE);
  41         u32 reg;
  42
  43         BUG_ON(is_enabled);
  44         BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE);
  45
  46         memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start,
  47                         tegra_cpu_reset_handler_size);
  48
  49         /*
  50          * NOTE: This must be the one and only write to the EVP CPU reset
  51          *       vector in the entire system.
  52          */
  53         writel(TEGRA_IRAM_RESET_BASE + tegra_cpu_reset_handler_offset,
  54                         evp_cpu_reset);
  55         wmb();
  56         reg = readl(evp_cpu_reset);
  57
  58         /*
  59          * Prevent further modifications to the physical reset vector.
  60          *  NOTE: Has no effect on chips prior to Tegra30.
  61          */
  62         if (tegra_chip_id != TEGRA20) {
  63                 reg = readl(sb_ctrl);
  64                 reg |= 2;
  65                 writel(reg, sb_ctrl);
  66                 wmb();
  67         }
  68
  69         is_enabled = true;
  70 }
  71
  72 void __init tegra_cpu_reset_handler_init(void)
  73 {
  74
  75 #ifdef CONFIG_SMP
  76         __tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] =
  77                 *((u32 *)cpu_present_mask);
  78         __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] =
  79                 virt_to_phys((void *)tegra_secondary_startup);
  80 #endif
  81
  82         tegra_cpu_reset_handler_enable();
  83 }