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Merge tag 'v3.12'
[deliverable/linux.git] / arch / arm / mach-tegra / sleep-tegra30.S
1 /*
2 * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17 #include <linux/linkage.h>
18
19 #include <asm/assembler.h>
20 #include <asm/asm-offsets.h>
21 #include <asm/cache.h>
22
23 #include "fuse.h"
24 #include "sleep.h"
25 #include "flowctrl.h"
26
27 #define EMC_CFG 0xc
28 #define EMC_ADR_CFG 0x10
29 #define EMC_TIMING_CONTROL 0x28
30 #define EMC_REFRESH 0x70
31 #define EMC_NOP 0xdc
32 #define EMC_SELF_REF 0xe0
33 #define EMC_MRW 0xe8
34 #define EMC_FBIO_CFG5 0x104
35 #define EMC_AUTO_CAL_CONFIG 0x2a4
36 #define EMC_AUTO_CAL_INTERVAL 0x2a8
37 #define EMC_AUTO_CAL_STATUS 0x2ac
38 #define EMC_REQ_CTRL 0x2b0
39 #define EMC_CFG_DIG_DLL 0x2bc
40 #define EMC_EMC_STATUS 0x2b4
41 #define EMC_ZCAL_INTERVAL 0x2e0
42 #define EMC_ZQ_CAL 0x2ec
43 #define EMC_XM2VTTGENPADCTRL 0x310
44 #define EMC_XM2VTTGENPADCTRL2 0x314
45
46 #define PMC_CTRL 0x0
47 #define PMC_CTRL_SIDE_EFFECT_LP0 (1 << 14) /* enter LP0 when CPU pwr gated */
48
49 #define PMC_PLLP_WB0_OVERRIDE 0xf8
50 #define PMC_IO_DPD_REQ 0x1b8
51 #define PMC_IO_DPD_STATUS 0x1bc
52
53 #define CLK_RESET_CCLK_BURST 0x20
54 #define CLK_RESET_CCLK_DIVIDER 0x24
55 #define CLK_RESET_SCLK_BURST 0x28
56 #define CLK_RESET_SCLK_DIVIDER 0x2c
57
58 #define CLK_RESET_PLLC_BASE 0x80
59 #define CLK_RESET_PLLC_MISC 0x8c
60 #define CLK_RESET_PLLM_BASE 0x90
61 #define CLK_RESET_PLLM_MISC 0x9c
62 #define CLK_RESET_PLLP_BASE 0xa0
63 #define CLK_RESET_PLLP_MISC 0xac
64 #define CLK_RESET_PLLA_BASE 0xb0
65 #define CLK_RESET_PLLA_MISC 0xbc
66 #define CLK_RESET_PLLX_BASE 0xe0
67 #define CLK_RESET_PLLX_MISC 0xe4
68 #define CLK_RESET_PLLX_MISC3 0x518
69 #define CLK_RESET_PLLX_MISC3_IDDQ 3
70 #define CLK_RESET_PLLM_MISC_IDDQ 5
71 #define CLK_RESET_PLLC_MISC_IDDQ 26
72
73 #define CLK_RESET_CLK_SOURCE_MSELECT 0x3b4
74
75 #define MSELECT_CLKM (0x3 << 30)
76
77 #define LOCK_DELAY 50 /* safety delay after lock is detected */
78
79 #define TEGRA30_POWER_HOTPLUG_SHUTDOWN (1 << 27) /* Hotplug shutdown */
80
81 .macro emc_device_mask, rd, base
82 ldr \rd, [\base, #EMC_ADR_CFG]
83 tst \rd, #0x1
84 moveq \rd, #(0x1 << 8) @ just 1 device
85 movne \rd, #(0x3 << 8) @ 2 devices
86 .endm
87
88 .macro emc_timing_update, rd, base
89 mov \rd, #1
90 str \rd, [\base, #EMC_TIMING_CONTROL]
91 1001:
92 ldr \rd, [\base, #EMC_EMC_STATUS]
93 tst \rd, #(0x1<<23) @ wait EMC_STATUS_TIMING_UPDATE_STALLED is clear
94 bne 1001b
95 .endm
96
97 .macro pll_enable, rd, r_car_base, pll_base, pll_misc
98 ldr \rd, [\r_car_base, #\pll_base]
99 tst \rd, #(1 << 30)
100 orreq \rd, \rd, #(1 << 30)
101 streq \rd, [\r_car_base, #\pll_base]
102 /* Enable lock detector */
103 .if \pll_misc
104 ldr \rd, [\r_car_base, #\pll_misc]
105 bic \rd, \rd, #(1 << 18)
106 str \rd, [\r_car_base, #\pll_misc]
107 ldr \rd, [\r_car_base, #\pll_misc]
108 ldr \rd, [\r_car_base, #\pll_misc]
109 orr \rd, \rd, #(1 << 18)
110 str \rd, [\r_car_base, #\pll_misc]
111 .endif
112 .endm
113
114 .macro pll_locked, rd, r_car_base, pll_base
115 1:
116 ldr \rd, [\r_car_base, #\pll_base]
117 tst \rd, #(1 << 27)
118 beq 1b
119 .endm
120
121 .macro pll_iddq_exit, rd, car, iddq, iddq_bit
122 ldr \rd, [\car, #\iddq]
123 bic \rd, \rd, #(1<<\iddq_bit)
124 str \rd, [\car, #\iddq]
125 .endm
126
127 .macro pll_iddq_entry, rd, car, iddq, iddq_bit
128 ldr \rd, [\car, #\iddq]
129 orr \rd, \rd, #(1<<\iddq_bit)
130 str \rd, [\car, #\iddq]
131 .endm
132
133 #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
134 /*
135 * tegra30_hotplug_shutdown(void)
136 *
137 * Powergates the current CPU.
138 * Should never return.
139 */
140 ENTRY(tegra30_hotplug_shutdown)
141 /* Powergate this CPU */
142 mov r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
143 bl tegra30_cpu_shutdown
144 mov pc, lr @ should never get here
145 ENDPROC(tegra30_hotplug_shutdown)
146
147 /*
148 * tegra30_cpu_shutdown(unsigned long flags)
149 *
150 * Puts the current CPU in wait-for-event mode on the flow controller
151 * and powergates it -- flags (in R0) indicate the request type.
152 *
153 * r10 = SoC ID
154 * corrupts r0-r4, r10-r12
155 */
156 ENTRY(tegra30_cpu_shutdown)
157 cpu_id r3
158 tegra_get_soc_id TEGRA_APB_MISC_VIRT, r10
159 cmp r10, #TEGRA30
160 bne _no_cpu0_chk @ It's not Tegra30
161
162 cmp r3, #0
163 moveq pc, lr @ Must never be called for CPU 0
164 _no_cpu0_chk:
165
166 ldr r12, =TEGRA_FLOW_CTRL_VIRT
167 cpu_to_csr_reg r1, r3
168 add r1, r1, r12 @ virtual CSR address for this CPU
169 cpu_to_halt_reg r2, r3
170 add r2, r2, r12 @ virtual HALT_EVENTS address for this CPU
171
172 /*
173 * Clear this CPU's "event" and "interrupt" flags and power gate
174 * it when halting but not before it is in the "WFE" state.
175 */
176 movw r12, \
177 FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \
178 FLOW_CTRL_CSR_ENABLE
179 cmp r10, #TEGRA30
180 moveq r4, #(1 << 4) @ wfe bitmap
181 movne r4, #(1 << 8) @ wfi bitmap
182 ARM( orr r12, r12, r4, lsl r3 )
183 THUMB( lsl r4, r4, r3 )
184 THUMB( orr r12, r12, r4 )
185 str r12, [r1]
186
187 /* Halt this CPU. */
188 mov r3, #0x400
189 delay_1:
190 subs r3, r3, #1 @ delay as a part of wfe war.
191 bge delay_1;
192 cpsid a @ disable imprecise aborts.
193 ldr r3, [r1] @ read CSR
194 str r3, [r1] @ clear CSR
195
196 tst r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
197 beq flow_ctrl_setting_for_lp2
198
199 /* flow controller set up for hotplug */
200 mov r3, #FLOW_CTRL_WAITEVENT @ For hotplug
201 b flow_ctrl_done
202 flow_ctrl_setting_for_lp2:
203 /* flow controller set up for LP2 */
204 cmp r10, #TEGRA30
205 moveq r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT @ For LP2
206 movne r3, #FLOW_CTRL_WAITEVENT
207 orrne r3, r3, #FLOW_CTRL_HALT_GIC_IRQ
208 orrne r3, r3, #FLOW_CTRL_HALT_GIC_FIQ
209 flow_ctrl_done:
210 cmp r10, #TEGRA30
211 str r3, [r2]
212 ldr r0, [r2]
213 b wfe_war
214
215 __cpu_reset_again:
216 dsb
217 .align 5
218 wfeeq @ CPU should be power gated here
219 wfine
220 wfe_war:
221 b __cpu_reset_again
222
223 /*
224 * 38 nop's, which fills reset of wfe cache line and
225 * 4 more cachelines with nop
226 */
227 .rept 38
228 nop
229 .endr
230 b . @ should never get here
231
232 ENDPROC(tegra30_cpu_shutdown)
233 #endif
234
235 #ifdef CONFIG_PM_SLEEP
236 /*
237 * tegra30_sleep_core_finish(unsigned long v2p)
238 *
239 * Enters suspend in LP0 or LP1 by turning off the MMU and jumping to
240 * tegra30_tear_down_core in IRAM
241 */
242 ENTRY(tegra30_sleep_core_finish)
243 /* Flush, disable the L1 data cache and exit SMP */
244 bl tegra_disable_clean_inv_dcache
245
246 /*
247 * Preload all the address literals that are needed for the
248 * CPU power-gating process, to avoid loading from SDRAM which
249 * are not supported once SDRAM is put into self-refresh.
250 * LP0 / LP1 use physical address, since the MMU needs to be
251 * disabled before putting SDRAM into self-refresh to avoid
252 * memory access due to page table walks.
253 */
254 mov32 r4, TEGRA_PMC_BASE
255 mov32 r5, TEGRA_CLK_RESET_BASE
256 mov32 r6, TEGRA_FLOW_CTRL_BASE
257 mov32 r7, TEGRA_TMRUS_BASE
258
259 mov32 r3, tegra_shut_off_mmu
260 add r3, r3, r0
261
262 mov32 r0, tegra30_tear_down_core
263 mov32 r1, tegra30_iram_start
264 sub r0, r0, r1
265 mov32 r1, TEGRA_IRAM_CODE_AREA
266 add r0, r0, r1
267
268 mov pc, r3
269 ENDPROC(tegra30_sleep_core_finish)
270
271 /*
272 * tegra30_sleep_cpu_secondary_finish(unsigned long v2p)
273 *
274 * Enters LP2 on secondary CPU by exiting coherency and powergating the CPU.
275 */
276 ENTRY(tegra30_sleep_cpu_secondary_finish)
277 mov r7, lr
278
279 /* Flush and disable the L1 data cache */
280 mov r0, #TEGRA_FLUSH_CACHE_LOUIS
281 bl tegra_disable_clean_inv_dcache
282
283 /* Powergate this CPU. */
284 mov r0, #0 @ power mode flags (!hotplug)
285 bl tegra30_cpu_shutdown
286 mov r0, #1 @ never return here
287 mov pc, r7
288 ENDPROC(tegra30_sleep_cpu_secondary_finish)
289
290 /*
291 * tegra30_tear_down_cpu
292 *
293 * Switches the CPU to enter sleep.
294 */
295 ENTRY(tegra30_tear_down_cpu)
296 mov32 r6, TEGRA_FLOW_CTRL_BASE
297
298 b tegra30_enter_sleep
299 ENDPROC(tegra30_tear_down_cpu)
300
301 /* START OF ROUTINES COPIED TO IRAM */
302 .align L1_CACHE_SHIFT
303 .globl tegra30_iram_start
304 tegra30_iram_start:
305
306 /*
307 * tegra30_lp1_reset
308 *
309 * reset vector for LP1 restore; copied into IRAM during suspend.
310 * Brings the system back up to a safe staring point (SDRAM out of
311 * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLX,
312 * system clock running on the same PLL that it suspended at), and
313 * jumps to tegra_resume to restore virtual addressing.
314 * The physical address of tegra_resume expected to be stored in
315 * PMC_SCRATCH41.
316 *
317 * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_CODE_AREA.
318 */
319 ENTRY(tegra30_lp1_reset)
320 /*
321 * The CPU and system bus are running at 32KHz and executing from
322 * IRAM when this code is executed; immediately switch to CLKM and
323 * enable PLLP, PLLM, PLLC, PLLA and PLLX.
324 */
325 mov32 r0, TEGRA_CLK_RESET_BASE
326
327 mov r1, #(1 << 28)
328 str r1, [r0, #CLK_RESET_SCLK_BURST]
329 str r1, [r0, #CLK_RESET_CCLK_BURST]
330 mov r1, #0
331 str r1, [r0, #CLK_RESET_CCLK_DIVIDER]
332 str r1, [r0, #CLK_RESET_SCLK_DIVIDER]
333
334 tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
335 cmp r10, #TEGRA30
336 beq _no_pll_iddq_exit
337
338 pll_iddq_exit r1, r0, CLK_RESET_PLLM_MISC, CLK_RESET_PLLM_MISC_IDDQ
339 pll_iddq_exit r1, r0, CLK_RESET_PLLC_MISC, CLK_RESET_PLLC_MISC_IDDQ
340 pll_iddq_exit r1, r0, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
341
342 mov32 r7, TEGRA_TMRUS_BASE
343 ldr r1, [r7]
344 add r1, r1, #2
345 wait_until r1, r7, r3
346
347 /* enable PLLM via PMC */
348 mov32 r2, TEGRA_PMC_BASE
349 ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
350 orr r1, r1, #(1 << 12)
351 str r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
352
353 pll_enable r1, r0, CLK_RESET_PLLM_BASE, 0
354 pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0
355 pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0
356
357 b _pll_m_c_x_done
358
359 _no_pll_iddq_exit:
360 /* enable PLLM via PMC */
361 mov32 r2, TEGRA_PMC_BASE
362 ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
363 orr r1, r1, #(1 << 12)
364 str r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
365
366 pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC
367 pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC
368 pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC
369
370 _pll_m_c_x_done:
371 pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC
372 pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC
373
374 pll_locked r1, r0, CLK_RESET_PLLM_BASE
375 pll_locked r1, r0, CLK_RESET_PLLP_BASE
376 pll_locked r1, r0, CLK_RESET_PLLA_BASE
377 pll_locked r1, r0, CLK_RESET_PLLC_BASE
378 pll_locked r1, r0, CLK_RESET_PLLX_BASE
379
380 mov32 r7, TEGRA_TMRUS_BASE
381 ldr r1, [r7]
382 add r1, r1, #LOCK_DELAY
383 wait_until r1, r7, r3
384
385 adr r5, tegra30_sdram_pad_save
386
387 ldr r4, [r5, #0x18] @ restore CLK_SOURCE_MSELECT
388 str r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT]
389
390 ldr r4, [r5, #0x1C] @ restore SCLK_BURST
391 str r4, [r0, #CLK_RESET_SCLK_BURST]
392
393 cmp r10, #TEGRA30
394 movweq r4, #:lower16:((1 << 28) | (0x8)) @ burst policy is PLLX
395 movteq r4, #:upper16:((1 << 28) | (0x8))
396 movwne r4, #:lower16:((1 << 28) | (0xe))
397 movtne r4, #:upper16:((1 << 28) | (0xe))
398 str r4, [r0, #CLK_RESET_CCLK_BURST]
399
400 /* Restore pad power state to normal */
401 ldr r1, [r5, #0x14] @ PMC_IO_DPD_STATUS
402 mvn r1, r1
403 bic r1, r1, #(1 << 31)
404 orr r1, r1, #(1 << 30)
405 str r1, [r2, #PMC_IO_DPD_REQ] @ DPD_OFF
406
407 cmp r10, #TEGRA30
408 movweq r0, #:lower16:TEGRA_EMC_BASE @ r0 reserved for emc base
409 movteq r0, #:upper16:TEGRA_EMC_BASE
410 movwne r0, #:lower16:TEGRA_EMC0_BASE
411 movtne r0, #:upper16:TEGRA_EMC0_BASE
412
413 exit_self_refresh:
414 ldr r1, [r5, #0xC] @ restore EMC_XM2VTTGENPADCTRL
415 str r1, [r0, #EMC_XM2VTTGENPADCTRL]
416 ldr r1, [r5, #0x10] @ restore EMC_XM2VTTGENPADCTRL2
417 str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
418 ldr r1, [r5, #0x8] @ restore EMC_AUTO_CAL_INTERVAL
419 str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
420
421 /* Relock DLL */
422 ldr r1, [r0, #EMC_CFG_DIG_DLL]
423 orr r1, r1, #(1 << 30) @ set DLL_RESET
424 str r1, [r0, #EMC_CFG_DIG_DLL]
425
426 emc_timing_update r1, r0
427
428 cmp r10, #TEGRA114
429 movweq r1, #:lower16:TEGRA_EMC1_BASE
430 movteq r1, #:upper16:TEGRA_EMC1_BASE
431 cmpeq r0, r1
432
433 ldr r1, [r0, #EMC_AUTO_CAL_CONFIG]
434 orr r1, r1, #(1 << 31) @ set AUTO_CAL_ACTIVE
435 orreq r1, r1, #(1 << 27) @ set slave mode for channel 1
436 str r1, [r0, #EMC_AUTO_CAL_CONFIG]
437
438 emc_wait_auto_cal_onetime:
439 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
440 tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared
441 bne emc_wait_auto_cal_onetime
442
443 ldr r1, [r0, #EMC_CFG]
444 bic r1, r1, #(1 << 31) @ disable DRAM_CLK_STOP_PD
445 str r1, [r0, #EMC_CFG]
446
447 mov r1, #0
448 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
449 mov r1, #1
450 cmp r10, #TEGRA30
451 streq r1, [r0, #EMC_NOP]
452 streq r1, [r0, #EMC_NOP]
453 streq r1, [r0, #EMC_REFRESH]
454
455 emc_device_mask r1, r0
456
457 exit_selfrefresh_loop:
458 ldr r2, [r0, #EMC_EMC_STATUS]
459 ands r2, r2, r1
460 bne exit_selfrefresh_loop
461
462 lsr r1, r1, #8 @ devSel, bit0:dev0, bit1:dev1
463
464 mov32 r7, TEGRA_TMRUS_BASE
465 ldr r2, [r0, #EMC_FBIO_CFG5]
466
467 and r2, r2, #3 @ check DRAM_TYPE
468 cmp r2, #2
469 beq emc_lpddr2
470
471 /* Issue a ZQ_CAL for dev0 - DDR3 */
472 mov32 r2, 0x80000011 @ DEV_SELECTION=2, LENGTH=LONG, CMD=1
473 str r2, [r0, #EMC_ZQ_CAL]
474 ldr r2, [r7]
475 add r2, r2, #10
476 wait_until r2, r7, r3
477
478 tst r1, #2
479 beq zcal_done
480
481 /* Issue a ZQ_CAL for dev1 - DDR3 */
482 mov32 r2, 0x40000011 @ DEV_SELECTION=1, LENGTH=LONG, CMD=1
483 str r2, [r0, #EMC_ZQ_CAL]
484 ldr r2, [r7]
485 add r2, r2, #10
486 wait_until r2, r7, r3
487 b zcal_done
488
489 emc_lpddr2:
490 /* Issue a ZQ_CAL for dev0 - LPDDR2 */
491 mov32 r2, 0x800A00AB @ DEV_SELECTION=2, MA=10, OP=0xAB
492 str r2, [r0, #EMC_MRW]
493 ldr r2, [r7]
494 add r2, r2, #1
495 wait_until r2, r7, r3
496
497 tst r1, #2
498 beq zcal_done
499
500 /* Issue a ZQ_CAL for dev0 - LPDDR2 */
501 mov32 r2, 0x400A00AB @ DEV_SELECTION=1, MA=10, OP=0xAB
502 str r2, [r0, #EMC_MRW]
503 ldr r2, [r7]
504 add r2, r2, #1
505 wait_until r2, r7, r3
506
507 zcal_done:
508 mov r1, #0 @ unstall all transactions
509 str r1, [r0, #EMC_REQ_CTRL]
510 ldr r1, [r5, #0x4] @ restore EMC_ZCAL_INTERVAL
511 str r1, [r0, #EMC_ZCAL_INTERVAL]
512 ldr r1, [r5, #0x0] @ restore EMC_CFG
513 str r1, [r0, #EMC_CFG]
514
515 /* Tegra114 had dual EMC channel, now config the other one */
516 cmp r10, #TEGRA114
517 bne __no_dual_emc_chanl
518 mov32 r1, TEGRA_EMC1_BASE
519 cmp r0, r1
520 movne r0, r1
521 addne r5, r5, #0x20
522 bne exit_self_refresh
523 __no_dual_emc_chanl:
524
525 mov32 r0, TEGRA_PMC_BASE
526 ldr r0, [r0, #PMC_SCRATCH41]
527 mov pc, r0 @ jump to tegra_resume
528 ENDPROC(tegra30_lp1_reset)
529
530 .align L1_CACHE_SHIFT
531 tegra30_sdram_pad_address:
532 .word TEGRA_EMC_BASE + EMC_CFG @0x0
533 .word TEGRA_EMC_BASE + EMC_ZCAL_INTERVAL @0x4
534 .word TEGRA_EMC_BASE + EMC_AUTO_CAL_INTERVAL @0x8
535 .word TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL @0xc
536 .word TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL2 @0x10
537 .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
538 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
539 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
540
541 tegra114_sdram_pad_address:
542 .word TEGRA_EMC0_BASE + EMC_CFG @0x0
543 .word TEGRA_EMC0_BASE + EMC_ZCAL_INTERVAL @0x4
544 .word TEGRA_EMC0_BASE + EMC_AUTO_CAL_INTERVAL @0x8
545 .word TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL @0xc
546 .word TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL2 @0x10
547 .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
548 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
549 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
550 .word TEGRA_EMC1_BASE + EMC_CFG @0x20
551 .word TEGRA_EMC1_BASE + EMC_ZCAL_INTERVAL @0x24
552 .word TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL @0x28
553 .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL @0x2c
554 .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2 @0x30
555
556 tegra30_sdram_pad_size:
557 .word tegra114_sdram_pad_address - tegra30_sdram_pad_address
558
559 tegra114_sdram_pad_size:
560 .word tegra30_sdram_pad_size - tegra114_sdram_pad_address
561
562 .type tegra30_sdram_pad_save, %object
563 tegra30_sdram_pad_save:
564 .rept (tegra30_sdram_pad_size - tegra114_sdram_pad_address) / 4
565 .long 0
566 .endr
567
568 /*
569 * tegra30_tear_down_core
570 *
571 * copied into and executed from IRAM
572 * puts memory in self-refresh for LP0 and LP1
573 */
574 tegra30_tear_down_core:
575 bl tegra30_sdram_self_refresh
576 bl tegra30_switch_cpu_to_clk32k
577 b tegra30_enter_sleep
578
579 /*
580 * tegra30_switch_cpu_to_clk32k
581 *
582 * In LP0 and LP1 all PLLs will be turned off. Switching the CPU and System CLK
583 * to the 32KHz clock.
584 * r4 = TEGRA_PMC_BASE
585 * r5 = TEGRA_CLK_RESET_BASE
586 * r6 = TEGRA_FLOW_CTRL_BASE
587 * r7 = TEGRA_TMRUS_BASE
588 * r10= SoC ID
589 */
590 tegra30_switch_cpu_to_clk32k:
591 /*
592 * start by jumping to CLKM to safely disable PLLs, then jump to
593 * CLKS.
594 */
595 mov r0, #(1 << 28)
596 str r0, [r5, #CLK_RESET_SCLK_BURST]
597 /* 2uS delay delay between changing SCLK and CCLK */
598 ldr r1, [r7]
599 add r1, r1, #2
600 wait_until r1, r7, r9
601 str r0, [r5, #CLK_RESET_CCLK_BURST]
602 mov r0, #0
603 str r0, [r5, #CLK_RESET_CCLK_DIVIDER]
604 str r0, [r5, #CLK_RESET_SCLK_DIVIDER]
605
606 /* switch the clock source of mselect to be CLK_M */
607 ldr r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
608 orr r0, r0, #MSELECT_CLKM
609 str r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
610
611 /* 2uS delay delay between changing SCLK and disabling PLLs */
612 ldr r1, [r7]
613 add r1, r1, #2
614 wait_until r1, r7, r9
615
616 /* disable PLLM via PMC in LP1 */
617 ldr r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
618 bic r0, r0, #(1 << 12)
619 str r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
620
621 /* disable PLLP, PLLA, PLLC and PLLX */
622 ldr r0, [r5, #CLK_RESET_PLLP_BASE]
623 bic r0, r0, #(1 << 30)
624 str r0, [r5, #CLK_RESET_PLLP_BASE]
625 ldr r0, [r5, #CLK_RESET_PLLA_BASE]
626 bic r0, r0, #(1 << 30)
627 str r0, [r5, #CLK_RESET_PLLA_BASE]
628 ldr r0, [r5, #CLK_RESET_PLLC_BASE]
629 bic r0, r0, #(1 << 30)
630 str r0, [r5, #CLK_RESET_PLLC_BASE]
631 ldr r0, [r5, #CLK_RESET_PLLX_BASE]
632 bic r0, r0, #(1 << 30)
633 str r0, [r5, #CLK_RESET_PLLX_BASE]
634
635 cmp r10, #TEGRA30
636 beq _no_pll_in_iddq
637 pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
638 _no_pll_in_iddq:
639
640 /* switch to CLKS */
641 mov r0, #0 /* brust policy = 32KHz */
642 str r0, [r5, #CLK_RESET_SCLK_BURST]
643
644 mov pc, lr
645
646 /*
647 * tegra30_enter_sleep
648 *
649 * uses flow controller to enter sleep state
650 * executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1
651 * executes from SDRAM with target state is LP2
652 * r6 = TEGRA_FLOW_CTRL_BASE
653 */
654 tegra30_enter_sleep:
655 cpu_id r1
656
657 cpu_to_csr_reg r2, r1
658 ldr r0, [r6, r2]
659 orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
660 orr r0, r0, #FLOW_CTRL_CSR_ENABLE
661 str r0, [r6, r2]
662
663 tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
664 cmp r10, #TEGRA30
665 mov r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
666 orreq r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
667 orrne r0, r0, #FLOW_CTRL_HALT_LIC_IRQ | FLOW_CTRL_HALT_LIC_FIQ
668
669 cpu_to_halt_reg r2, r1
670 str r0, [r6, r2]
671 dsb
672 ldr r0, [r6, r2] /* memory barrier */
673
674 halted:
675 isb
676 dsb
677 wfi /* CPU should be power gated here */
678
679 /* !!!FIXME!!! Implement halt failure handler */
680 b halted
681
682 /*
683 * tegra30_sdram_self_refresh
684 *
685 * called with MMU off and caches disabled
686 * must be executed from IRAM
687 * r4 = TEGRA_PMC_BASE
688 * r5 = TEGRA_CLK_RESET_BASE
689 * r6 = TEGRA_FLOW_CTRL_BASE
690 * r7 = TEGRA_TMRUS_BASE
691 * r10= SoC ID
692 */
693 tegra30_sdram_self_refresh:
694
695 adr r8, tegra30_sdram_pad_save
696 tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
697 cmp r10, #TEGRA30
698 adreq r2, tegra30_sdram_pad_address
699 ldreq r3, tegra30_sdram_pad_size
700 adrne r2, tegra114_sdram_pad_address
701 ldrne r3, tegra114_sdram_pad_size
702 mov r9, #0
703
704 padsave:
705 ldr r0, [r2, r9] @ r0 is the addr in the pad_address
706
707 ldr r1, [r0]
708 str r1, [r8, r9] @ save the content of the addr
709
710 add r9, r9, #4
711 cmp r3, r9
712 bne padsave
713 padsave_done:
714
715 dsb
716
717 cmp r10, #TEGRA30
718 ldreq r0, =TEGRA_EMC_BASE @ r0 reserved for emc base addr
719 ldrne r0, =TEGRA_EMC0_BASE
720
721 enter_self_refresh:
722 cmp r10, #TEGRA30
723 mov r1, #0
724 str r1, [r0, #EMC_ZCAL_INTERVAL]
725 str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
726 ldr r1, [r0, #EMC_CFG]
727 bic r1, r1, #(1 << 28)
728 bicne r1, r1, #(1 << 29)
729 str r1, [r0, #EMC_CFG] @ disable DYN_SELF_REF
730
731 emc_timing_update r1, r0
732
733 ldr r1, [r7]
734 add r1, r1, #5
735 wait_until r1, r7, r2
736
737 emc_wait_auto_cal:
738 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
739 tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared
740 bne emc_wait_auto_cal
741
742 mov r1, #3
743 str r1, [r0, #EMC_REQ_CTRL] @ stall incoming DRAM requests
744
745 emcidle:
746 ldr r1, [r0, #EMC_EMC_STATUS]
747 tst r1, #4
748 beq emcidle
749
750 mov r1, #1
751 str r1, [r0, #EMC_SELF_REF]
752
753 emc_device_mask r1, r0
754
755 emcself:
756 ldr r2, [r0, #EMC_EMC_STATUS]
757 and r2, r2, r1
758 cmp r2, r1
759 bne emcself @ loop until DDR in self-refresh
760
761 /* Put VTTGEN in the lowest power mode */
762 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL]
763 mov32 r2, 0xF8F8FFFF @ clear XM2VTTGEN_DRVUP and XM2VTTGEN_DRVDN
764 and r1, r1, r2
765 str r1, [r0, #EMC_XM2VTTGENPADCTRL]
766 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL2]
767 cmp r10, #TEGRA30
768 orreq r1, r1, #7 @ set E_NO_VTTGEN
769 orrne r1, r1, #0x3f
770 str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
771
772 emc_timing_update r1, r0
773
774 /* Tegra114 had dual EMC channel, now config the other one */
775 cmp r10, #TEGRA114
776 bne no_dual_emc_chanl
777 mov32 r1, TEGRA_EMC1_BASE
778 cmp r0, r1
779 movne r0, r1
780 bne enter_self_refresh
781 no_dual_emc_chanl:
782
783 ldr r1, [r4, #PMC_CTRL]
784 tst r1, #PMC_CTRL_SIDE_EFFECT_LP0
785 bne pmc_io_dpd_skip
786 /*
787 * Put DDR_DATA, DISC_ADDR_CMD, DDR_ADDR_CMD, POP_ADDR_CMD, POP_CLK
788 * and COMP in the lowest power mode when LP1.
789 */
790 mov32 r1, 0x8EC00000
791 str r1, [r4, #PMC_IO_DPD_REQ]
792 pmc_io_dpd_skip:
793
794 dsb
795
796 mov pc, lr
797
798 .ltorg
799 /* dummy symbol for end of IRAM */
800 .align L1_CACHE_SHIFT
801 .global tegra30_iram_end
802 tegra30_iram_end:
803 b .
804 #endif
Linux kernel - Deliverables
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