2 * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 #include <linux/linkage.h>
19 #include <asm/assembler.h>
20 #include <asm/asm-offsets.h>
25 #define TEGRA30_POWER_HOTPLUG_SHUTDOWN (1 << 27) /* Hotplug shutdown */
27 #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
29 * tegra30_hotplug_shutdown(void)
31 * Powergates the current CPU.
32 * Should never return.
34 ENTRY(tegra30_hotplug_shutdown)
35 /* Turn off SMP coherency */
38 /* Powergate this CPU */
39 mov r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
40 bl tegra30_cpu_shutdown
41 mov pc, lr @ should never get here
42 ENDPROC(tegra30_hotplug_shutdown)
45 * tegra30_cpu_shutdown(unsigned long flags)
47 * Puts the current CPU in wait-for-event mode on the flow controller
48 * and powergates it -- flags (in R0) indicate the request type.
49 * Must never be called for CPU 0.
53 ENTRY(tegra30_cpu_shutdown)
56 moveq pc, lr @ Must never be called for CPU 0
58 ldr r12, =TEGRA_FLOW_CTRL_VIRT
60 add r1, r1, r12 @ virtual CSR address for this CPU
61 cpu_to_halt_reg r2, r3
62 add r2, r2, r12 @ virtual HALT_EVENTS address for this CPU
65 * Clear this CPU's "event" and "interrupt" flags and power gate
66 * it when halting but not before it is in the "WFE" state.
69 FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \
72 orr r12, r12, r4, lsl r3
78 subs r3, r3, #1 @ delay as a part of wfe war.
80 cpsid a @ disable imprecise aborts.
81 ldr r3, [r1] @ read CSR
82 str r3, [r1] @ clear CSR
83 tst r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
84 moveq r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT @ For LP2
85 movne r3, #FLOW_CTRL_WAITEVENT @ For hotplug
93 wfe @ CPU should be power gated here
98 * 38 nop's, which fills reset of wfe cache line and
99 * 4 more cachelines with nop
104 b . @ should never get here
106 ENDPROC(tegra30_cpu_shutdown)
109 #ifdef CONFIG_PM_SLEEP
111 * tegra30_sleep_cpu_secondary_finish(unsigned long v2p)
113 * Enters LP2 on secondary CPU by exiting coherency and powergating the CPU.
115 ENTRY(tegra30_sleep_cpu_secondary_finish)
118 /* Flush and disable the L1 data cache */
119 bl tegra_disable_clean_inv_dcache
121 /* Powergate this CPU. */
122 mov r0, #0 @ power mode flags (!hotplug)
123 bl tegra30_cpu_shutdown
124 mov r0, #1 @ never return here
126 ENDPROC(tegra30_sleep_cpu_secondary_finish)
129 * tegra30_tear_down_cpu
131 * Switches the CPU to enter sleep.
133 ENTRY(tegra30_tear_down_cpu)
134 mov32 r6, TEGRA_FLOW_CTRL_BASE
136 b tegra30_enter_sleep
137 ENDPROC(tegra30_tear_down_cpu)
140 * tegra30_enter_sleep
142 * uses flow controller to enter sleep state
143 * executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1
144 * executes from SDRAM with target state is LP2
145 * r6 = TEGRA_FLOW_CTRL_BASE
150 cpu_to_csr_reg r2, r1
152 orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
153 orr r0, r0, #FLOW_CTRL_CSR_ENABLE
156 mov r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
157 orr r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
158 cpu_to_halt_reg r2, r1
161 ldr r0, [r6, r2] /* memory barrier */
166 wfi /* CPU should be power gated here */
168 /* !!!FIXME!!! Implement halt failure handler */