2 * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 #ifndef __MACH_TEGRA_SLEEP_H
18 #define __MACH_TEGRA_SLEEP_H
22 #define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \
24 #define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
26 #define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \
30 /* returns the offset of the flow controller halt register for a cpu */
31 .macro cpu_to_halt_reg rd
, rcpu
34 movne
\rd
, \rd
, lsl
#3
39 /* returns the offset of the flow controller csr register for a cpu */
40 .macro cpu_to_csr_reg rd
, rcpu
43 movne
\rd
, \rd
, lsl
#3
48 /* returns the ID of the current processor */
50 mrc p15
, 0, \rd
, c0
, c0
, 5
54 /* loads a 32-bit value into a register without a data access */
55 .macro mov32
, reg
, val
56 movw
\reg
, #:lower16:\val
57 movt
\reg
, #:upper16:\val
60 /* Macro to exit SMP coherency. */
61 .macro exit_smp
, tmp1
, tmp2
62 mrc p15
, 0, \tmp
1, c1
, c0
, 1 @ ACTLR
63 bic
\tmp
1, \tmp
1, #(1<<6) | (1<<0) @ clear ACTLR.SMP | ACTLR.FW
64 mcr p15
, 0, \tmp
1, c1
, c0
, 1 @ ACTLR
67 mov
\tmp
1, \tmp
1, lsl
#2
69 mov
\tmp
2, \tmp
2, lsl
\tmp
1
70 mov32
\tmp
1, TEGRA_ARM_PERIF_VIRT
+ 0xC
71 str
\tmp
2, [\tmp
1] @ invalidate SCU tags
for CPU
75 /* Macro to resume & re-enable L2 cache */
77 #define L2X0_CTRL_EN 1
80 #ifdef CONFIG_CACHE_L2X0
81 .macro l2_cache_resume
, tmp1
, tmp2
, tmp3
, phys_l2x0_saved_regs
82 adr
\tmp
1, \phys_l2x0_saved_regs
84 ldr
\tmp
2, [\tmp
1, #L2X0_R_PHY_BASE]
85 ldr
\tmp
3, [\tmp
2, #L2X0_CTRL]
86 tst
\tmp
3, #L2X0_CTRL_EN
88 ldr
\tmp
3, [\tmp
1, #L2X0_R_TAG_LATENCY]
89 str
\tmp
3, [\tmp
2, #L2X0_TAG_LATENCY_CTRL]
90 ldr
\tmp
3, [\tmp
1, #L2X0_R_DATA_LATENCY]
91 str
\tmp
3, [\tmp
2, #L2X0_DATA_LATENCY_CTRL]
92 ldr
\tmp
3, [\tmp
1, #L2X0_R_PREFETCH_CTRL]
93 str
\tmp
3, [\tmp
2, #L2X0_PREFETCH_CTRL]
94 ldr
\tmp
3, [\tmp
1, #L2X0_R_PWR_CTRL]
95 str
\tmp
3, [\tmp
2, #L2X0_POWER_CTRL]
96 ldr
\tmp
3, [\tmp
1, #L2X0_R_AUX_CTRL]
97 str
\tmp
3, [\tmp
2, #L2X0_AUX_CTRL]
98 mov
\tmp
3, #L2X0_CTRL_EN
99 str
\tmp
3, [\tmp
2, #L2X0_CTRL]
102 #else /* CONFIG_CACHE_L2X0 */
103 .macro l2_cache_resume
, tmp1
, tmp2
, tmp3
, phys_l2x0_saved_regs
105 #endif /* CONFIG_CACHE_L2X0 */
107 void tegra_resume(void);
108 int tegra_sleep_cpu_finish(unsigned long);
110 #ifdef CONFIG_HOTPLUG_CPU
111 void tegra20_hotplug_init(void);
112 void tegra30_hotplug_init(void);
114 static inline void tegra20_hotplug_init(void) {}
115 static inline void tegra30_hotplug_init(void) {}
118 int tegra30_sleep_cpu_secondary_finish(unsigned long);
119 void tegra30_tear_down_cpu(void);
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