arch/arm/mach-tegra/sleep.h

   1 /*
   2  * Copyright (c) 2010-2013, NVIDIA Corporation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #ifndef __MACH_TEGRA_SLEEP_H
  18 #define __MACH_TEGRA_SLEEP_H
  19
  20 #include "iomap.h"
  21
  22 #define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \
  23                                         + IO_CPU_VIRT)
  24 #define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
  25                                         + IO_PPSB_VIRT)
  26 #define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \
  27                                         + IO_PPSB_VIRT)
  28 #define TEGRA_APB_MISC_VIRT (TEGRA_APB_MISC_BASE - IO_APB_PHYS \
  29                                         + IO_APB_VIRT)
  30 #define TEGRA_PMC_VIRT  (TEGRA_PMC_BASE - IO_APB_PHYS + IO_APB_VIRT)
  31
  32 /* PMC_SCRATCH37-39 and 41 are used for tegra_pen_lock and idle */
  33 #define PMC_SCRATCH37   0x130
  34 #define PMC_SCRATCH38   0x134
  35 #define PMC_SCRATCH39   0x138
  36 #define PMC_SCRATCH41   0x140
  37
  38 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
  39 #define CPU_RESETTABLE          2
  40 #define CPU_RESETTABLE_SOON     1
  41 #define CPU_NOT_RESETTABLE      0
  42 #endif
  43
  44 #ifdef __ASSEMBLY__
  45 /* returns the offset of the flow controller halt register for a cpu */
  46 .macro cpu_to_halt_reg rd, rcpu
  47         cmp     \rcpu, #0
  48         subne   \rd, \rcpu, #1
  49         movne   \rd, \rd, lsl #3
  50         addne   \rd, \rd, #0x14
  51         moveq   \rd, #0
  52 .endm
  53
  54 /* returns the offset of the flow controller csr register for a cpu */
  55 .macro cpu_to_csr_reg rd, rcpu
  56         cmp     \rcpu, #0
  57         subne   \rd, \rcpu, #1
  58         movne   \rd, \rd, lsl #3
  59         addne   \rd, \rd, #0x18
  60         moveq   \rd, #8
  61 .endm
  62
  63 /* returns the ID of the current processor */
  64 .macro cpu_id, rd
  65         mrc     p15, 0, \rd, c0, c0, 5
  66         and     \rd, \rd, #0xF
  67 .endm
  68
  69 /* loads a 32-bit value into a register without a data access */
  70 .macro mov32, reg, val
  71         movw    \reg, #:lower16:\val
  72         movt    \reg, #:upper16:\val
  73 .endm
  74
  75 /* Marco to check CPU part num */
  76 .macro check_cpu_part_num part_num, tmp1, tmp2
  77         mrc     p15, 0, \tmp1, c0, c0, 0
  78         ubfx    \tmp1, \tmp1, #4, #12
  79         mov32   \tmp2, \part_num
  80         cmp     \tmp1, \tmp2
  81 .endm
  82
  83 /* Macro to exit SMP coherency. */
  84 .macro exit_smp, tmp1, tmp2
  85         mrc     p15, 0, \tmp1, c1, c0, 1        @ ACTLR
  86         bic     \tmp1, \tmp1, #(1<<6) | (1<<0)  @ clear ACTLR.SMP | ACTLR.FW
  87         mcr     p15, 0, \tmp1, c1, c0, 1        @ ACTLR
  88         isb
  89 #ifdef CONFIG_HAVE_ARM_SCU
  90         check_cpu_part_num 0xc09, \tmp1, \tmp2
  91         mrceq   p15, 0, \tmp1, c0, c0, 5
  92         andeq   \tmp1, \tmp1, #0xF
  93         moveq   \tmp1, \tmp1, lsl #2
  94         moveq   \tmp2, #0xf
  95         moveq   \tmp2, \tmp2, lsl \tmp1
  96         ldreq   \tmp1, =(TEGRA_ARM_PERIF_VIRT + 0xC)
  97         streq   \tmp2, [\tmp1]                  @ invalidate SCU tags for CPU
  98         dsb
  99 #endif
 100 .endm
 101
 102 /* Macro to check Tegra revision */
 103 #define APB_MISC_GP_HIDREV      0x804
 104 .macro tegra_get_soc_id base, tmp1
 105         mov32   \tmp1, \base
 106         ldr     \tmp1, [\tmp1, #APB_MISC_GP_HIDREV]
 107         and     \tmp1, \tmp1, #0xff00
 108         mov     \tmp1, \tmp1, lsr #8
 109 .endm
 110
 111 /* Macro to resume & re-enable L2 cache */
 112 #ifndef L2X0_CTRL_EN
 113 #define L2X0_CTRL_EN    1
 114 #endif
 115
 116 #ifdef CONFIG_CACHE_L2X0
 117 .macro l2_cache_resume, tmp1, tmp2, tmp3, phys_l2x0_saved_regs
 118         W(adr)  \tmp1, \phys_l2x0_saved_regs
 119         ldr     \tmp1, [\tmp1]
 120         ldr     \tmp2, [\tmp1, #L2X0_R_PHY_BASE]
 121         ldr     \tmp3, [\tmp2, #L2X0_CTRL]
 122         tst     \tmp3, #L2X0_CTRL_EN
 123         bne     exit_l2_resume
 124         ldr     \tmp3, [\tmp1, #L2X0_R_TAG_LATENCY]
 125         str     \tmp3, [\tmp2, #L2X0_TAG_LATENCY_CTRL]
 126         ldr     \tmp3, [\tmp1, #L2X0_R_DATA_LATENCY]
 127         str     \tmp3, [\tmp2, #L2X0_DATA_LATENCY_CTRL]
 128         ldr     \tmp3, [\tmp1, #L2X0_R_PREFETCH_CTRL]
 129         str     \tmp3, [\tmp2, #L2X0_PREFETCH_CTRL]
 130         ldr     \tmp3, [\tmp1, #L2X0_R_PWR_CTRL]
 131         str     \tmp3, [\tmp2, #L2X0_POWER_CTRL]
 132         ldr     \tmp3, [\tmp1, #L2X0_R_AUX_CTRL]
 133         str     \tmp3, [\tmp2, #L2X0_AUX_CTRL]
 134         mov     \tmp3, #L2X0_CTRL_EN
 135         str     \tmp3, [\tmp2, #L2X0_CTRL]
 136 exit_l2_resume:
 137 .endm
 138 #else /* CONFIG_CACHE_L2X0 */
 139 .macro l2_cache_resume, tmp1, tmp2, tmp3, phys_l2x0_saved_regs
 140 .endm
 141 #endif /* CONFIG_CACHE_L2X0 */
 142 #else
 143 void tegra_pen_lock(void);
 144 void tegra_pen_unlock(void);
 145 void tegra_resume(void);
 146 int tegra_sleep_cpu_finish(unsigned long);
 147 void tegra_disable_clean_inv_dcache(void);
 148
 149 #ifdef CONFIG_HOTPLUG_CPU
 150 void tegra20_hotplug_shutdown(void);
 151 void tegra30_hotplug_shutdown(void);
 152 void tegra_hotplug_init(void);
 153 #else
 154 static inline void tegra_hotplug_init(void) {}
 155 #endif
 156
 157 void tegra20_cpu_shutdown(int cpu);
 158 int tegra20_cpu_is_resettable_soon(void);
 159 void tegra20_cpu_clear_resettable(void);
 160 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
 161 void tegra20_cpu_set_resettable_soon(void);
 162 #else
 163 static inline void tegra20_cpu_set_resettable_soon(void) {}
 164 #endif
 165
 166 int tegra20_sleep_cpu_secondary_finish(unsigned long);
 167 void tegra20_tear_down_cpu(void);
 168 int tegra30_sleep_cpu_secondary_finish(unsigned long);
 169 void tegra30_tear_down_cpu(void);
 170
 171 #endif
 172 #endif