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Merge tag 'for-v3.8-merged' of git://git.infradead.org/battery-2.6
[deliverable/linux.git] / arch / arm / mach-tegra / tegra20_clocks_data.c
1 /*
2 * arch/arm/mach-tegra/tegra2_clocks.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (c) 2012 NVIDIA CORPORATION. All rights reserved.
6 *
7 * Author:
8 * Colin Cross <ccross@google.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21 #include <linux/clk-private.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/list.h>
25 #include <linux/spinlock.h>
26 #include <linux/delay.h>
27 #include <linux/io.h>
28 #include <linux/clk.h>
29
30 #include "clock.h"
31 #include "fuse.h"
32 #include "tegra2_emc.h"
33 #include "tegra20_clocks.h"
34 #include "tegra_cpu_car.h"
35
36 /* Clock definitions */
37
38 #define DEFINE_CLK_TEGRA(_name, _rate, _ops, _flags, \
39 _parent_names, _parents, _parent) \
40 static struct clk tegra_##_name = { \
41 .hw = &tegra_##_name##_hw.hw, \
42 .name = #_name, \
43 .rate = _rate, \
44 .ops = _ops, \
45 .flags = _flags, \
46 .parent_names = _parent_names, \
47 .parents = _parents, \
48 .num_parents = ARRAY_SIZE(_parent_names), \
49 .parent = _parent, \
50 };
51
52 static struct clk tegra_clk_32k;
53 static struct clk_tegra tegra_clk_32k_hw = {
54 .hw = {
55 .clk = &tegra_clk_32k,
56 },
57 .fixed_rate = 32768,
58 };
59
60 static struct clk tegra_clk_32k = {
61 .name = "clk_32k",
62 .rate = 32768,
63 .ops = &tegra_clk_32k_ops,
64 .hw = &tegra_clk_32k_hw.hw,
65 .flags = CLK_IS_ROOT,
66 };
67
68 static struct clk tegra_clk_m;
69 static struct clk_tegra tegra_clk_m_hw = {
70 .hw = {
71 .clk = &tegra_clk_m,
72 },
73 .flags = ENABLE_ON_INIT,
74 .reg = 0x1fc,
75 .reg_shift = 28,
76 .max_rate = 26000000,
77 .fixed_rate = 0,
78 };
79
80 static struct clk tegra_clk_m = {
81 .name = "clk_m",
82 .ops = &tegra_clk_m_ops,
83 .hw = &tegra_clk_m_hw.hw,
84 .flags = CLK_IS_ROOT,
85 };
86
87 #define DEFINE_PLL(_name, _flags, _reg, _max_rate, _input_min, \
88 _input_max, _cf_min, _cf_max, _vco_min, \
89 _vco_max, _freq_table, _lock_delay, _ops, \
90 _fixed_rate, _parent) \
91 static const char *tegra_##_name##_parent_names[] = { \
92 #_parent, \
93 }; \
94 static struct clk *tegra_##_name##_parents[] = { \
95 &tegra_##_parent, \
96 }; \
97 static struct clk tegra_##_name; \
98 static struct clk_tegra tegra_##_name##_hw = { \
99 .hw = { \
100 .clk = &tegra_##_name, \
101 }, \
102 .flags = _flags, \
103 .reg = _reg, \
104 .max_rate = _max_rate, \
105 .u.pll = { \
106 .input_min = _input_min, \
107 .input_max = _input_max, \
108 .cf_min = _cf_min, \
109 .cf_max = _cf_max, \
110 .vco_min = _vco_min, \
111 .vco_max = _vco_max, \
112 .freq_table = _freq_table, \
113 .lock_delay = _lock_delay, \
114 .fixed_rate = _fixed_rate, \
115 }, \
116 }; \
117 static struct clk tegra_##_name = { \
118 .name = #_name, \
119 .ops = &_ops, \
120 .hw = &tegra_##_name##_hw.hw, \
121 .parent = &tegra_##_parent, \
122 .parent_names = tegra_##_name##_parent_names, \
123 .parents = tegra_##_name##_parents, \
124 .num_parents = 1, \
125 };
126
127 #define DEFINE_PLL_OUT(_name, _flags, _reg, _reg_shift, \
128 _max_rate, _ops, _parent, _clk_flags) \
129 static const char *tegra_##_name##_parent_names[] = { \
130 #_parent, \
131 }; \
132 static struct clk *tegra_##_name##_parents[] = { \
133 &tegra_##_parent, \
134 }; \
135 static struct clk tegra_##_name; \
136 static struct clk_tegra tegra_##_name##_hw = { \
137 .hw = { \
138 .clk = &tegra_##_name, \
139 }, \
140 .flags = _flags, \
141 .reg = _reg, \
142 .max_rate = _max_rate, \
143 .reg_shift = _reg_shift, \
144 }; \
145 static struct clk tegra_##_name = { \
146 .name = #_name, \
147 .ops = &tegra_pll_div_ops, \
148 .hw = &tegra_##_name##_hw.hw, \
149 .parent = &tegra_##_parent, \
150 .parent_names = tegra_##_name##_parent_names, \
151 .parents = tegra_##_name##_parents, \
152 .num_parents = 1, \
153 .flags = _clk_flags, \
154 };
155
156
157 static struct clk_pll_freq_table tegra_pll_s_freq_table[] = {
158 {32768, 12000000, 366, 1, 1, 0},
159 {32768, 13000000, 397, 1, 1, 0},
160 {32768, 19200000, 586, 1, 1, 0},
161 {32768, 26000000, 793, 1, 1, 0},
162 {0, 0, 0, 0, 0, 0},
163 };
164
165 DEFINE_PLL(pll_s, PLL_ALT_MISC_REG, 0xf0, 26000000, 32768, 32768, 0,
166 0, 12000000, 26000000, tegra_pll_s_freq_table, 300,
167 tegra_pll_ops, 0, clk_32k);
168
169 static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
170 { 12000000, 600000000, 600, 12, 1, 8 },
171 { 13000000, 600000000, 600, 13, 1, 8 },
172 { 19200000, 600000000, 500, 16, 1, 6 },
173 { 26000000, 600000000, 600, 26, 1, 8 },
174 { 0, 0, 0, 0, 0, 0 },
175 };
176
177 DEFINE_PLL(pll_c, PLL_HAS_CPCON, 0x80, 600000000, 2000000, 31000000, 1000000,
178 6000000, 20000000, 1400000000, tegra_pll_c_freq_table, 300,
179 tegra_pll_ops, 0, clk_m);
180
181 DEFINE_PLL_OUT(pll_c_out1, DIV_U71, 0x84, 0, 600000000,
182 tegra_pll_div_ops, pll_c, 0);
183
184 static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
185 { 12000000, 666000000, 666, 12, 1, 8},
186 { 13000000, 666000000, 666, 13, 1, 8},
187 { 19200000, 666000000, 555, 16, 1, 8},
188 { 26000000, 666000000, 666, 26, 1, 8},
189 { 12000000, 600000000, 600, 12, 1, 8},
190 { 13000000, 600000000, 600, 13, 1, 8},
191 { 19200000, 600000000, 375, 12, 1, 6},
192 { 26000000, 600000000, 600, 26, 1, 8},
193 { 0, 0, 0, 0, 0, 0 },
194 };
195
196 DEFINE_PLL(pll_m, PLL_HAS_CPCON, 0x90, 800000000, 2000000, 31000000, 1000000,
197 6000000, 20000000, 1200000000, tegra_pll_m_freq_table, 300,
198 tegra_pll_ops, 0, clk_m);
199
200 DEFINE_PLL_OUT(pll_m_out1, DIV_U71, 0x94, 0, 600000000,
201 tegra_pll_div_ops, pll_m, 0);
202
203 static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
204 { 12000000, 216000000, 432, 12, 2, 8},
205 { 13000000, 216000000, 432, 13, 2, 8},
206 { 19200000, 216000000, 90, 4, 2, 1},
207 { 26000000, 216000000, 432, 26, 2, 8},
208 { 12000000, 432000000, 432, 12, 1, 8},
209 { 13000000, 432000000, 432, 13, 1, 8},
210 { 19200000, 432000000, 90, 4, 1, 1},
211 { 26000000, 432000000, 432, 26, 1, 8},
212 { 0, 0, 0, 0, 0, 0 },
213 };
214
215
216 DEFINE_PLL(pll_p, ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, 0xa0, 432000000,
217 2000000, 31000000, 1000000, 6000000, 20000000, 1400000000,
218 tegra_pll_p_freq_table, 300, tegra_pll_ops, 216000000, clk_m);
219
220 DEFINE_PLL_OUT(pll_p_out1, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4, 0,
221 432000000, tegra_pll_div_ops, pll_p, 0);
222 DEFINE_PLL_OUT(pll_p_out2, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4, 16,
223 432000000, tegra_pll_div_ops, pll_p, 0);
224 DEFINE_PLL_OUT(pll_p_out3, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8, 0,
225 432000000, tegra_pll_div_ops, pll_p, 0);
226 DEFINE_PLL_OUT(pll_p_out4, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8, 16,
227 432000000, tegra_pll_div_ops, pll_p, 0);
228
229 static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
230 { 28800000, 56448000, 49, 25, 1, 1},
231 { 28800000, 73728000, 64, 25, 1, 1},
232 { 28800000, 24000000, 5, 6, 1, 1},
233 { 0, 0, 0, 0, 0, 0 },
234 };
235
236 DEFINE_PLL(pll_a, PLL_HAS_CPCON, 0xb0, 73728000, 2000000, 31000000, 1000000,
237 6000000, 20000000, 1400000000, tegra_pll_a_freq_table, 300,
238 tegra_pll_ops, 0, pll_p_out1);
239
240 DEFINE_PLL_OUT(pll_a_out0, DIV_U71, 0xb4, 0, 73728000,
241 tegra_pll_div_ops, pll_a, 0);
242
243 static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
244 { 12000000, 216000000, 216, 12, 1, 4},
245 { 13000000, 216000000, 216, 13, 1, 4},
246 { 19200000, 216000000, 135, 12, 1, 3},
247 { 26000000, 216000000, 216, 26, 1, 4},
248
249 { 12000000, 297000000, 99, 4, 1, 4 },
250 { 12000000, 339000000, 113, 4, 1, 4 },
251
252 { 12000000, 594000000, 594, 12, 1, 8},
253 { 13000000, 594000000, 594, 13, 1, 8},
254 { 19200000, 594000000, 495, 16, 1, 8},
255 { 26000000, 594000000, 594, 26, 1, 8},
256
257 { 12000000, 616000000, 616, 12, 1, 8},
258
259 { 12000000, 1000000000, 1000, 12, 1, 12},
260 { 13000000, 1000000000, 1000, 13, 1, 12},
261 { 19200000, 1000000000, 625, 12, 1, 8},
262 { 26000000, 1000000000, 1000, 26, 1, 12},
263
264 { 0, 0, 0, 0, 0, 0 },
265 };
266
267 DEFINE_PLL(pll_d, PLL_HAS_CPCON | PLLD, 0xd0, 1000000000, 2000000, 40000000,
268 1000000, 6000000, 40000000, 1000000000, tegra_pll_d_freq_table,
269 1000, tegra_pll_ops, 0, clk_m);
270
271 DEFINE_PLL_OUT(pll_d_out0, DIV_2 | PLLD, 0, 0, 500000000,
272 tegra_pll_div_ops, pll_d, CLK_SET_RATE_PARENT);
273
274 static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
275 { 12000000, 480000000, 960, 12, 2, 0},
276 { 13000000, 480000000, 960, 13, 2, 0},
277 { 19200000, 480000000, 200, 4, 2, 0},
278 { 26000000, 480000000, 960, 26, 2, 0},
279 { 0, 0, 0, 0, 0, 0 },
280 };
281
282 DEFINE_PLL(pll_u, PLLU, 0xc0, 480000000, 2000000, 40000000, 1000000, 6000000,
283 48000000, 960000000, tegra_pll_u_freq_table, 1000,
284 tegra_pll_ops, 0, clk_m);
285
286 static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
287 /* 1 GHz */
288 { 12000000, 1000000000, 1000, 12, 1, 12},
289 { 13000000, 1000000000, 1000, 13, 1, 12},
290 { 19200000, 1000000000, 625, 12, 1, 8},
291 { 26000000, 1000000000, 1000, 26, 1, 12},
292
293 /* 912 MHz */
294 { 12000000, 912000000, 912, 12, 1, 12},
295 { 13000000, 912000000, 912, 13, 1, 12},
296 { 19200000, 912000000, 760, 16, 1, 8},
297 { 26000000, 912000000, 912, 26, 1, 12},
298
299 /* 816 MHz */
300 { 12000000, 816000000, 816, 12, 1, 12},
301 { 13000000, 816000000, 816, 13, 1, 12},
302 { 19200000, 816000000, 680, 16, 1, 8},
303 { 26000000, 816000000, 816, 26, 1, 12},
304
305 /* 760 MHz */
306 { 12000000, 760000000, 760, 12, 1, 12},
307 { 13000000, 760000000, 760, 13, 1, 12},
308 { 19200000, 760000000, 950, 24, 1, 8},
309 { 26000000, 760000000, 760, 26, 1, 12},
310
311 /* 750 MHz */
312 { 12000000, 750000000, 750, 12, 1, 12},
313 { 13000000, 750000000, 750, 13, 1, 12},
314 { 19200000, 750000000, 625, 16, 1, 8},
315 { 26000000, 750000000, 750, 26, 1, 12},
316
317 /* 608 MHz */
318 { 12000000, 608000000, 608, 12, 1, 12},
319 { 13000000, 608000000, 608, 13, 1, 12},
320 { 19200000, 608000000, 380, 12, 1, 8},
321 { 26000000, 608000000, 608, 26, 1, 12},
322
323 /* 456 MHz */
324 { 12000000, 456000000, 456, 12, 1, 12},
325 { 13000000, 456000000, 456, 13, 1, 12},
326 { 19200000, 456000000, 380, 16, 1, 8},
327 { 26000000, 456000000, 456, 26, 1, 12},
328
329 /* 312 MHz */
330 { 12000000, 312000000, 312, 12, 1, 12},
331 { 13000000, 312000000, 312, 13, 1, 12},
332 { 19200000, 312000000, 260, 16, 1, 8},
333 { 26000000, 312000000, 312, 26, 1, 12},
334
335 { 0, 0, 0, 0, 0, 0 },
336 };
337
338 DEFINE_PLL(pll_x, PLL_HAS_CPCON | PLL_ALT_MISC_REG, 0xe0, 1000000000, 2000000,
339 31000000, 1000000, 6000000, 20000000, 1200000000,
340 tegra_pll_x_freq_table, 300, tegra_pllx_ops, 0, clk_m);
341
342 static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
343 { 12000000, 100000000, 200, 24, 1, 0 },
344 { 0, 0, 0, 0, 0, 0 },
345 };
346
347 DEFINE_PLL(pll_e, PLL_ALT_MISC_REG, 0xe8, 100000000, 12000000, 12000000, 0, 0,
348 0, 0, tegra_pll_e_freq_table, 0, tegra_plle_ops, 0, clk_m);
349
350 static const char *tegra_common_parent_names[] = {
351 "clk_m",
352 };
353
354 static struct clk *tegra_common_parents[] = {
355 &tegra_clk_m,
356 };
357
358 static struct clk tegra_clk_d;
359 static struct clk_tegra tegra_clk_d_hw = {
360 .hw = {
361 .clk = &tegra_clk_d,
362 },
363 .flags = PERIPH_NO_RESET,
364 .reg = 0x34,
365 .reg_shift = 12,
366 .max_rate = 52000000,
367 .u.periph = {
368 .clk_num = 90,
369 },
370 };
371
372 static struct clk tegra_clk_d = {
373 .name = "clk_d",
374 .hw = &tegra_clk_d_hw.hw,
375 .ops = &tegra_clk_double_ops,
376 .parent = &tegra_clk_m,
377 .parent_names = tegra_common_parent_names,
378 .parents = tegra_common_parents,
379 .num_parents = ARRAY_SIZE(tegra_common_parent_names),
380 };
381
382 static struct clk tegra_cdev1;
383 static struct clk_tegra tegra_cdev1_hw = {
384 .hw = {
385 .clk = &tegra_cdev1,
386 },
387 .fixed_rate = 26000000,
388 .u.periph = {
389 .clk_num = 94,
390 },
391 };
392 static struct clk tegra_cdev1 = {
393 .name = "cdev1",
394 .hw = &tegra_cdev1_hw.hw,
395 .ops = &tegra_cdev_clk_ops,
396 .flags = CLK_IS_ROOT,
397 };
398
399 /* dap_mclk2, belongs to the cdev2 pingroup. */
400 static struct clk tegra_cdev2;
401 static struct clk_tegra tegra_cdev2_hw = {
402 .hw = {
403 .clk = &tegra_cdev2,
404 },
405 .fixed_rate = 26000000,
406 .u.periph = {
407 .clk_num = 93,
408 },
409 };
410 static struct clk tegra_cdev2 = {
411 .name = "cdev2",
412 .hw = &tegra_cdev2_hw.hw,
413 .ops = &tegra_cdev_clk_ops,
414 .flags = CLK_IS_ROOT,
415 };
416
417 /* initialized before peripheral clocks */
418 static struct clk_mux_sel mux_audio_sync_clk[8+1];
419 static const struct audio_sources {
420 const char *name;
421 int value;
422 } mux_audio_sync_clk_sources[] = {
423 { .name = "spdif_in", .value = 0 },
424 { .name = "i2s1", .value = 1 },
425 { .name = "i2s2", .value = 2 },
426 { .name = "pll_a_out0", .value = 4 },
427 #if 0 /* FIXME: not implemented */
428 { .name = "ac97", .value = 3 },
429 { .name = "ext_audio_clk2", .value = 5 },
430 { .name = "ext_audio_clk1", .value = 6 },
431 { .name = "ext_vimclk", .value = 7 },
432 #endif
433 { NULL, 0 }
434 };
435
436 static const char *audio_parent_names[] = {
437 "spdif_in",
438 "i2s1",
439 "i2s2",
440 "dummy",
441 "pll_a_out0",
442 "dummy",
443 "dummy",
444 "dummy",
445 };
446
447 static struct clk *audio_parents[] = {
448 NULL,
449 NULL,
450 NULL,
451 NULL,
452 NULL,
453 NULL,
454 NULL,
455 NULL,
456 };
457
458 static struct clk tegra_audio;
459 static struct clk_tegra tegra_audio_hw = {
460 .hw = {
461 .clk = &tegra_audio,
462 },
463 .reg = 0x38,
464 .max_rate = 73728000,
465 };
466 DEFINE_CLK_TEGRA(audio, 0, &tegra_audio_sync_clk_ops, 0, audio_parent_names,
467 audio_parents, NULL);
468
469 static const char *audio_2x_parent_names[] = {
470 "audio",
471 };
472
473 static struct clk *audio_2x_parents[] = {
474 &tegra_audio,
475 };
476
477 static struct clk tegra_audio_2x;
478 static struct clk_tegra tegra_audio_2x_hw = {
479 .hw = {
480 .clk = &tegra_audio_2x,
481 },
482 .flags = PERIPH_NO_RESET,
483 .max_rate = 48000000,
484 .reg = 0x34,
485 .reg_shift = 8,
486 .u.periph = {
487 .clk_num = 89,
488 },
489 };
490 DEFINE_CLK_TEGRA(audio_2x, 0, &tegra_clk_double_ops, 0, audio_2x_parent_names,
491 audio_2x_parents, &tegra_audio);
492
493 static struct clk_lookup tegra_audio_clk_lookups[] = {
494 { .con_id = "audio", .clk = &tegra_audio },
495 { .con_id = "audio_2x", .clk = &tegra_audio_2x }
496 };
497
498 /* This is called after peripheral clocks are initialized, as the
499 * audio_sync clock depends on some of the peripheral clocks.
500 */
501
502 static void init_audio_sync_clock_mux(void)
503 {
504 int i;
505 struct clk_mux_sel *sel = mux_audio_sync_clk;
506 const struct audio_sources *src = mux_audio_sync_clk_sources;
507 struct clk_lookup *lookup;
508
509 for (i = 0; src->name; i++, sel++, src++) {
510 sel->input = tegra_get_clock_by_name(src->name);
511 if (!sel->input)
512 pr_err("%s: could not find clk %s\n", __func__,
513 src->name);
514 audio_parents[src->value] = sel->input;
515 sel->value = src->value;
516 }
517
518 lookup = tegra_audio_clk_lookups;
519 for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) {
520 struct clk *c = lookup->clk;
521 struct clk_tegra *clk = to_clk_tegra(c->hw);
522 __clk_init(NULL, c);
523 INIT_LIST_HEAD(&clk->shared_bus_list);
524 clk->lookup.con_id = lookup->con_id;
525 clk->lookup.clk = c;
526 clkdev_add(&clk->lookup);
527 tegra_clk_add(c);
528 }
529 }
530
531 static const char *mux_cclk[] = {
532 "clk_m",
533 "pll_c",
534 "clk_32k",
535 "pll_m",
536 "pll_p",
537 "pll_p_out4",
538 "pll_p_out3",
539 "clk_d",
540 "pll_x",
541 };
542
543
544 static struct clk *mux_cclk_p[] = {
545 &tegra_clk_m,
546 &tegra_pll_c,
547 &tegra_clk_32k,
548 &tegra_pll_m,
549 &tegra_pll_p,
550 &tegra_pll_p_out4,
551 &tegra_pll_p_out3,
552 &tegra_clk_d,
553 &tegra_pll_x,
554 };
555
556 static const char *mux_sclk[] = {
557 "clk_m",
558 "pll_c_out1",
559 "pll_p_out4",
560 "pllp_p_out3",
561 "pll_p_out2",
562 "clk_d",
563 "clk_32k",
564 "pll_m_out1",
565 };
566
567 static struct clk *mux_sclk_p[] = {
568 &tegra_clk_m,
569 &tegra_pll_c_out1,
570 &tegra_pll_p_out4,
571 &tegra_pll_p_out3,
572 &tegra_pll_p_out2,
573 &tegra_clk_d,
574 &tegra_clk_32k,
575 &tegra_pll_m_out1,
576 };
577
578 static struct clk tegra_cclk;
579 static struct clk_tegra tegra_cclk_hw = {
580 .hw = {
581 .clk = &tegra_cclk,
582 },
583 .reg = 0x20,
584 .max_rate = 1000000000,
585 };
586 DEFINE_CLK_TEGRA(cclk, 0, &tegra_super_ops, 0, mux_cclk,
587 mux_cclk_p, NULL);
588
589 static const char *mux_twd[] = {
590 "cclk",
591 };
592
593 static struct clk *mux_twd_p[] = {
594 &tegra_cclk,
595 };
596
597 static struct clk tegra_clk_twd;
598 static struct clk_tegra tegra_clk_twd_hw = {
599 .hw = {
600 .clk = &tegra_clk_twd,
601 },
602 .max_rate = 1000000000,
603 .mul = 1,
604 .div = 4,
605 };
606
607 static struct clk tegra_clk_twd = {
608 .name = "twd",
609 .ops = &tegra_twd_ops,
610 .hw = &tegra_clk_twd_hw.hw,
611 .parent = &tegra_cclk,
612 .parent_names = mux_twd,
613 .parents = mux_twd_p,
614 .num_parents = ARRAY_SIZE(mux_twd),
615 };
616
617 static struct clk tegra_sclk;
618 static struct clk_tegra tegra_sclk_hw = {
619 .hw = {
620 .clk = &tegra_sclk,
621 },
622 .reg = 0x28,
623 .max_rate = 240000000,
624 .min_rate = 120000000,
625 };
626 DEFINE_CLK_TEGRA(sclk, 0, &tegra_super_ops, 0, mux_sclk,
627 mux_sclk_p, NULL);
628
629 static const char *tegra_cop_parent_names[] = {
630 "tegra_sclk",
631 };
632
633 static struct clk *tegra_cop_parents[] = {
634 &tegra_sclk,
635 };
636
637 static struct clk tegra_cop;
638 static struct clk_tegra tegra_cop_hw = {
639 .hw = {
640 .clk = &tegra_cop,
641 },
642 .max_rate = 240000000,
643 .reset = &tegra2_cop_clk_reset,
644 };
645 DEFINE_CLK_TEGRA(cop, 0, &tegra_cop_ops, CLK_SET_RATE_PARENT,
646 tegra_cop_parent_names, tegra_cop_parents, &tegra_sclk);
647
648 static const char *tegra_hclk_parent_names[] = {
649 "tegra_sclk",
650 };
651
652 static struct clk *tegra_hclk_parents[] = {
653 &tegra_sclk,
654 };
655
656 static struct clk tegra_hclk;
657 static struct clk_tegra tegra_hclk_hw = {
658 .hw = {
659 .clk = &tegra_hclk,
660 },
661 .flags = DIV_BUS,
662 .reg = 0x30,
663 .reg_shift = 4,
664 .max_rate = 240000000,
665 };
666 DEFINE_CLK_TEGRA(hclk, 0, &tegra_bus_ops, 0, tegra_hclk_parent_names,
667 tegra_hclk_parents, &tegra_sclk);
668
669 static const char *tegra_pclk_parent_names[] = {
670 "tegra_hclk",
671 };
672
673 static struct clk *tegra_pclk_parents[] = {
674 &tegra_hclk,
675 };
676
677 static struct clk tegra_pclk;
678 static struct clk_tegra tegra_pclk_hw = {
679 .hw = {
680 .clk = &tegra_pclk,
681 },
682 .flags = DIV_BUS,
683 .reg = 0x30,
684 .reg_shift = 0,
685 .max_rate = 120000000,
686 };
687 DEFINE_CLK_TEGRA(pclk, 0, &tegra_bus_ops, 0, tegra_pclk_parent_names,
688 tegra_pclk_parents, &tegra_hclk);
689
690 static const char *tegra_blink_parent_names[] = {
691 "clk_32k",
692 };
693
694 static struct clk *tegra_blink_parents[] = {
695 &tegra_clk_32k,
696 };
697
698 static struct clk tegra_blink;
699 static struct clk_tegra tegra_blink_hw = {
700 .hw = {
701 .clk = &tegra_blink,
702 },
703 .reg = 0x40,
704 .max_rate = 32768,
705 };
706 DEFINE_CLK_TEGRA(blink, 0, &tegra_blink_clk_ops, 0, tegra_blink_parent_names,
707 tegra_blink_parents, &tegra_clk_32k);
708
709 static const char *mux_pllm_pllc_pllp_plla[] = {
710 "pll_m",
711 "pll_c",
712 "pll_p",
713 "pll_a_out0",
714 };
715
716 static struct clk *mux_pllm_pllc_pllp_plla_p[] = {
717 &tegra_pll_m,
718 &tegra_pll_c,
719 &tegra_pll_p,
720 &tegra_pll_a_out0,
721 };
722
723 static const char *mux_pllm_pllc_pllp_clkm[] = {
724 "pll_m",
725 "pll_c",
726 "pll_p",
727 "clk_m",
728 };
729
730 static struct clk *mux_pllm_pllc_pllp_clkm_p[] = {
731 &tegra_pll_m,
732 &tegra_pll_c,
733 &tegra_pll_p,
734 &tegra_clk_m,
735 };
736
737 static const char *mux_pllp_pllc_pllm_clkm[] = {
738 "pll_p",
739 "pll_c",
740 "pll_m",
741 "clk_m",
742 };
743
744 static struct clk *mux_pllp_pllc_pllm_clkm_p[] = {
745 &tegra_pll_p,
746 &tegra_pll_c,
747 &tegra_pll_m,
748 &tegra_clk_m,
749 };
750
751 static const char *mux_pllaout0_audio2x_pllp_clkm[] = {
752 "pll_a_out0",
753 "audio_2x",
754 "pll_p",
755 "clk_m",
756 };
757
758 static struct clk *mux_pllaout0_audio2x_pllp_clkm_p[] = {
759 &tegra_pll_a_out0,
760 &tegra_audio_2x,
761 &tegra_pll_p,
762 &tegra_clk_m,
763 };
764
765 static const char *mux_pllp_plld_pllc_clkm[] = {
766 "pllp",
767 "pll_d_out0",
768 "pll_c",
769 "clk_m",
770 };
771
772 static struct clk *mux_pllp_plld_pllc_clkm_p[] = {
773 &tegra_pll_p,
774 &tegra_pll_d_out0,
775 &tegra_pll_c,
776 &tegra_clk_m,
777 };
778
779 static const char *mux_pllp_pllc_audio_clkm_clk32[] = {
780 "pll_p",
781 "pll_c",
782 "audio",
783 "clk_m",
784 "clk_32k",
785 };
786
787 static struct clk *mux_pllp_pllc_audio_clkm_clk32_p[] = {
788 &tegra_pll_p,
789 &tegra_pll_c,
790 &tegra_audio,
791 &tegra_clk_m,
792 &tegra_clk_32k,
793 };
794
795 static const char *mux_pllp_pllc_pllm[] = {
796 "pll_p",
797 "pll_c",
798 "pll_m"
799 };
800
801 static struct clk *mux_pllp_pllc_pllm_p[] = {
802 &tegra_pll_p,
803 &tegra_pll_c,
804 &tegra_pll_m,
805 };
806
807 static const char *mux_clk_m[] = {
808 "clk_m",
809 };
810
811 static struct clk *mux_clk_m_p[] = {
812 &tegra_clk_m,
813 };
814
815 static const char *mux_pllp_out3[] = {
816 "pll_p_out3",
817 };
818
819 static struct clk *mux_pllp_out3_p[] = {
820 &tegra_pll_p_out3,
821 };
822
823 static const char *mux_plld[] = {
824 "pll_d",
825 };
826
827 static struct clk *mux_plld_p[] = {
828 &tegra_pll_d,
829 };
830
831 static const char *mux_clk_32k[] = {
832 "clk_32k",
833 };
834
835 static struct clk *mux_clk_32k_p[] = {
836 &tegra_clk_32k,
837 };
838
839 static const char *mux_pclk[] = {
840 "pclk",
841 };
842
843 static struct clk *mux_pclk_p[] = {
844 &tegra_pclk,
845 };
846
847 static struct clk tegra_emc;
848 static struct clk_tegra tegra_emc_hw = {
849 .hw = {
850 .clk = &tegra_emc,
851 },
852 .reg = 0x19c,
853 .max_rate = 800000000,
854 .flags = MUX | DIV_U71 | PERIPH_EMC_ENB,
855 .reset = &tegra2_periph_clk_reset,
856 .u.periph = {
857 .clk_num = 57,
858 },
859 };
860 DEFINE_CLK_TEGRA(emc, 0, &tegra_emc_clk_ops, 0, mux_pllm_pllc_pllp_clkm,
861 mux_pllm_pllc_pllp_clkm_p, NULL);
862
863 #define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, \
864 _max, _inputs, _flags) \
865 static struct clk tegra_##_name; \
866 static struct clk_tegra tegra_##_name##_hw = { \
867 .hw = { \
868 .clk = &tegra_##_name, \
869 }, \
870 .lookup = { \
871 .dev_id = _dev, \
872 .con_id = _con, \
873 }, \
874 .reg = _reg, \
875 .flags = _flags, \
876 .max_rate = _max, \
877 .u.periph = { \
878 .clk_num = _clk_num, \
879 }, \
880 .reset = tegra2_periph_clk_reset, \
881 }; \
882 static struct clk tegra_##_name = { \
883 .name = #_name, \
884 .ops = &tegra_periph_clk_ops, \
885 .hw = &tegra_##_name##_hw.hw, \
886 .parent_names = _inputs, \
887 .parents = _inputs##_p, \
888 .num_parents = ARRAY_SIZE(_inputs), \
889 };
890
891 PERIPH_CLK(apbdma, "tegra-apbdma", NULL, 34, 0, 108000000, mux_pclk, 0);
892 PERIPH_CLK(rtc, "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET);
893 PERIPH_CLK(timer, "timer", NULL, 5, 0, 26000000, mux_clk_m, 0);
894 PERIPH_CLK(i2s1, "tegra20-i2s.0", NULL, 11, 0x100, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71);
895 PERIPH_CLK(i2s2, "tegra20-i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71);
896 PERIPH_CLK(spdif_out, "spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71);
897 PERIPH_CLK(spdif_in, "spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71);
898 PERIPH_CLK(pwm, "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71 | MUX_PWM);
899 PERIPH_CLK(spi, "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
900 PERIPH_CLK(xio, "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
901 PERIPH_CLK(twc, "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
902 PERIPH_CLK(sbc1, "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
903 PERIPH_CLK(sbc2, "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
904 PERIPH_CLK(sbc3, "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
905 PERIPH_CLK(sbc4, "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
906 PERIPH_CLK(ide, "ide", NULL, 25, 0x144, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */
907 PERIPH_CLK(ndflash, "tegra_nand", NULL, 13, 0x160, 164000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
908 PERIPH_CLK(vfir, "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
909 PERIPH_CLK(sdmmc1, "sdhci-tegra.0", NULL, 14, 0x150, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
910 PERIPH_CLK(sdmmc2, "sdhci-tegra.1", NULL, 9, 0x154, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
911 PERIPH_CLK(sdmmc3, "sdhci-tegra.2", NULL, 69, 0x1bc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
912 PERIPH_CLK(sdmmc4, "sdhci-tegra.3", NULL, 15, 0x164, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
913 PERIPH_CLK(vcp, "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0);
914 PERIPH_CLK(bsea, "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0);
915 PERIPH_CLK(bsev, "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0);
916 PERIPH_CLK(vde, "tegra-avp", "vde", 61, 0x1c8, 250000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage and process_id */
917 PERIPH_CLK(csite, "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* max rate ??? */
918 /* FIXME: what is la? */
919 PERIPH_CLK(la, "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
920 PERIPH_CLK(owr, "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
921 PERIPH_CLK(nor, "nor", NULL, 42, 0x1d0, 92000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */
922 PERIPH_CLK(mipi, "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
923 PERIPH_CLK(i2c1, "tegra-i2c.0", "div-clk", 12, 0x124, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
924 PERIPH_CLK(i2c2, "tegra-i2c.1", "div-clk", 54, 0x198, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
925 PERIPH_CLK(i2c3, "tegra-i2c.2", "div-clk", 67, 0x1b8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
926 PERIPH_CLK(dvc, "tegra-i2c.3", "div-clk", 47, 0x128, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
927 PERIPH_CLK(uarta, "tegra-uart.0", NULL, 6, 0x178, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
928 PERIPH_CLK(uartb, "tegra-uart.1", NULL, 7, 0x17c, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
929 PERIPH_CLK(uartc, "tegra-uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
930 PERIPH_CLK(uartd, "tegra-uart.3", NULL, 65, 0x1c0, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
931 PERIPH_CLK(uarte, "tegra-uart.4", NULL, 66, 0x1c4, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
932 PERIPH_CLK(3d, "3d", NULL, 24, 0x158, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET); /* scales with voltage and process_id */
933 PERIPH_CLK(2d, "2d", NULL, 21, 0x15c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
934 PERIPH_CLK(vi, "tegra_camera", "vi", 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
935 PERIPH_CLK(vi_sensor, "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET); /* scales with voltage and process_id */
936 PERIPH_CLK(epp, "epp", NULL, 19, 0x16c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
937 PERIPH_CLK(mpe, "mpe", NULL, 60, 0x170, 250000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
938 PERIPH_CLK(host1x, "host1x", NULL, 28, 0x180, 166000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
939 PERIPH_CLK(cve, "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
940 PERIPH_CLK(tvo, "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
941 PERIPH_CLK(hdmi, "hdmi", NULL, 51, 0x18c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
942 PERIPH_CLK(tvdac, "tvdac", NULL, 53, 0x194, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
943 PERIPH_CLK(disp1, "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_plld_pllc_clkm, MUX); /* scales with voltage and process_id */
944 PERIPH_CLK(disp2, "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_plld_pllc_clkm, MUX); /* scales with voltage and process_id */
945 PERIPH_CLK(usbd, "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
946 PERIPH_CLK(usb2, "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
947 PERIPH_CLK(usb3, "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
948 PERIPH_CLK(dsi, "dsi", NULL, 48, 0, 500000000, mux_plld, 0); /* scales with voltage */
949 PERIPH_CLK(csi, "tegra_camera", "csi", 52, 0, 72000000, mux_pllp_out3, 0);
950 PERIPH_CLK(isp, "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0); /* same frequency as VI */
951 PERIPH_CLK(csus, "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET);
952 PERIPH_CLK(pex, NULL, "pex", 70, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET);
953 PERIPH_CLK(afi, NULL, "afi", 72, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET);
954 PERIPH_CLK(pcie_xclk, NULL, "pcie_xclk", 74, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET);
955
956 static struct clk *tegra_list_clks[] = {
957 &tegra_apbdma,
958 &tegra_rtc,
959 &tegra_timer,
960 &tegra_i2s1,
961 &tegra_i2s2,
962 &tegra_spdif_out,
963 &tegra_spdif_in,
964 &tegra_pwm,
965 &tegra_spi,
966 &tegra_xio,
967 &tegra_twc,
968 &tegra_sbc1,
969 &tegra_sbc2,
970 &tegra_sbc3,
971 &tegra_sbc4,
972 &tegra_ide,
973 &tegra_ndflash,
974 &tegra_vfir,
975 &tegra_sdmmc1,
976 &tegra_sdmmc2,
977 &tegra_sdmmc3,
978 &tegra_sdmmc4,
979 &tegra_vcp,
980 &tegra_bsea,
981 &tegra_bsev,
982 &tegra_vde,
983 &tegra_csite,
984 &tegra_la,
985 &tegra_owr,
986 &tegra_nor,
987 &tegra_mipi,
988 &tegra_i2c1,
989 &tegra_i2c2,
990 &tegra_i2c3,
991 &tegra_dvc,
992 &tegra_uarta,
993 &tegra_uartb,
994 &tegra_uartc,
995 &tegra_uartd,
996 &tegra_uarte,
997 &tegra_3d,
998 &tegra_2d,
999 &tegra_vi,
1000 &tegra_vi_sensor,
1001 &tegra_epp,
1002 &tegra_mpe,
1003 &tegra_host1x,
1004 &tegra_cve,
1005 &tegra_tvo,
1006 &tegra_hdmi,
1007 &tegra_tvdac,
1008 &tegra_disp1,
1009 &tegra_disp2,
1010 &tegra_usbd,
1011 &tegra_usb2,
1012 &tegra_usb3,
1013 &tegra_dsi,
1014 &tegra_csi,
1015 &tegra_isp,
1016 &tegra_csus,
1017 &tegra_pex,
1018 &tegra_afi,
1019 &tegra_pcie_xclk,
1020 };
1021
1022 #define CLK_DUPLICATE(_name, _dev, _con) \
1023 { \
1024 .name = _name, \
1025 .lookup = { \
1026 .dev_id = _dev, \
1027 .con_id = _con, \
1028 }, \
1029 }
1030
1031 /* Some clocks may be used by different drivers depending on the board
1032 * configuration. List those here to register them twice in the clock lookup
1033 * table under two names.
1034 */
1035 static struct clk_duplicate tegra_clk_duplicates[] = {
1036 CLK_DUPLICATE("uarta", "serial8250.0", NULL),
1037 CLK_DUPLICATE("uartb", "serial8250.1", NULL),
1038 CLK_DUPLICATE("uartc", "serial8250.2", NULL),
1039 CLK_DUPLICATE("uartd", "serial8250.3", NULL),
1040 CLK_DUPLICATE("uarte", "serial8250.4", NULL),
1041 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
1042 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
1043 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
1044 CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),
1045 CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),
1046 CLK_DUPLICATE("epp", "tegra_grhost", "epp"),
1047 CLK_DUPLICATE("mpe", "tegra_grhost", "mpe"),
1048 CLK_DUPLICATE("cop", "tegra-avp", "cop"),
1049 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
1050 CLK_DUPLICATE("cclk", NULL, "cpu"),
1051 CLK_DUPLICATE("twd", "smp_twd", NULL),
1052 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.0", "fast-clk"),
1053 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.1", "fast-clk"),
1054 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.2", "fast-clk"),
1055 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.3", "fast-clk"),
1056 CLK_DUPLICATE("pll_p", "tegradc.0", "parent"),
1057 CLK_DUPLICATE("pll_p", "tegradc.1", "parent"),
1058 CLK_DUPLICATE("pll_d_out0", "hdmi", "parent"),
1059 };
1060
1061 #define CLK(dev, con, ck) \
1062 { \
1063 .dev_id = dev, \
1064 .con_id = con, \
1065 .clk = ck, \
1066 }
1067
1068 static struct clk *tegra_ptr_clks[] = {
1069 &tegra_clk_32k,
1070 &tegra_pll_s,
1071 &tegra_clk_m,
1072 &tegra_pll_m,
1073 &tegra_pll_m_out1,
1074 &tegra_pll_c,
1075 &tegra_pll_c_out1,
1076 &tegra_pll_p,
1077 &tegra_pll_p_out1,
1078 &tegra_pll_p_out2,
1079 &tegra_pll_p_out3,
1080 &tegra_pll_p_out4,
1081 &tegra_pll_a,
1082 &tegra_pll_a_out0,
1083 &tegra_pll_d,
1084 &tegra_pll_d_out0,
1085 &tegra_pll_u,
1086 &tegra_pll_x,
1087 &tegra_pll_e,
1088 &tegra_cclk,
1089 &tegra_clk_twd,
1090 &tegra_sclk,
1091 &tegra_hclk,
1092 &tegra_pclk,
1093 &tegra_clk_d,
1094 &tegra_cdev1,
1095 &tegra_cdev2,
1096 &tegra_blink,
1097 &tegra_cop,
1098 &tegra_emc,
1099 };
1100
1101 static void tegra2_init_one_clock(struct clk *c)
1102 {
1103 struct clk_tegra *clk = to_clk_tegra(c->hw);
1104 int ret;
1105
1106 ret = __clk_init(NULL, c);
1107 if (ret)
1108 pr_err("clk init failed %s\n", __clk_get_name(c));
1109
1110 INIT_LIST_HEAD(&clk->shared_bus_list);
1111 if (!clk->lookup.dev_id && !clk->lookup.con_id)
1112 clk->lookup.con_id = c->name;
1113 clk->lookup.clk = c;
1114 clkdev_add(&clk->lookup);
1115 tegra_clk_add(c);
1116 }
1117
1118 void __init tegra2_init_clocks(void)
1119 {
1120 int i;
1121 struct clk *c;
1122
1123 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
1124 tegra2_init_one_clock(tegra_ptr_clks[i]);
1125
1126 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
1127 tegra2_init_one_clock(tegra_list_clks[i]);
1128
1129 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
1130 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
1131 if (!c) {
1132 pr_err("%s: Unknown duplicate clock %s\n", __func__,
1133 tegra_clk_duplicates[i].name);
1134 continue;
1135 }
1136
1137 tegra_clk_duplicates[i].lookup.clk = c;
1138 clkdev_add(&tegra_clk_duplicates[i].lookup);
1139 }
1140
1141 init_audio_sync_clock_mux();
1142 tegra20_cpu_car_ops_init();
1143 }
Linux kernel - Deliverables
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