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[deliverable/linux.git] / arch / arm / mach-tegra / tegra2_clocks.c
1 /*
2 * arch/arm/mach-tegra/tegra2_clocks.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/list.h>
23 #include <linux/spinlock.h>
24 #include <linux/delay.h>
25 #include <linux/io.h>
26 #include <linux/clkdev.h>
27 #include <linux/clk.h>
28
29 #include <mach/iomap.h>
30 #include <mach/suspend.h>
31
32 #include "clock.h"
33 #include "fuse.h"
34
35 #define RST_DEVICES 0x004
36 #define RST_DEVICES_SET 0x300
37 #define RST_DEVICES_CLR 0x304
38 #define RST_DEVICES_NUM 3
39
40 #define CLK_OUT_ENB 0x010
41 #define CLK_OUT_ENB_SET 0x320
42 #define CLK_OUT_ENB_CLR 0x324
43 #define CLK_OUT_ENB_NUM 3
44
45 #define CLK_MASK_ARM 0x44
46 #define MISC_CLK_ENB 0x48
47
48 #define OSC_CTRL 0x50
49 #define OSC_CTRL_OSC_FREQ_MASK (3<<30)
50 #define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
51 #define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30)
52 #define OSC_CTRL_OSC_FREQ_12MHZ (2<<30)
53 #define OSC_CTRL_OSC_FREQ_26MHZ (3<<30)
54 #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
55
56 #define OSC_FREQ_DET 0x58
57 #define OSC_FREQ_DET_TRIG (1<<31)
58
59 #define OSC_FREQ_DET_STATUS 0x5C
60 #define OSC_FREQ_DET_BUSY (1<<31)
61 #define OSC_FREQ_DET_CNT_MASK 0xFFFF
62
63 #define PERIPH_CLK_SOURCE_I2S1 0x100
64 #define PERIPH_CLK_SOURCE_EMC 0x19c
65 #define PERIPH_CLK_SOURCE_OSC 0x1fc
66 #define PERIPH_CLK_SOURCE_NUM \
67 ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
68
69 #define PERIPH_CLK_SOURCE_MASK (3<<30)
70 #define PERIPH_CLK_SOURCE_SHIFT 30
71 #define PERIPH_CLK_SOURCE_ENABLE (1<<28)
72 #define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF
73 #define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
74 #define PERIPH_CLK_SOURCE_DIV_SHIFT 0
75
76 #define PLL_BASE 0x0
77 #define PLL_BASE_BYPASS (1<<31)
78 #define PLL_BASE_ENABLE (1<<30)
79 #define PLL_BASE_REF_ENABLE (1<<29)
80 #define PLL_BASE_OVERRIDE (1<<28)
81 #define PLL_BASE_DIVP_MASK (0x7<<20)
82 #define PLL_BASE_DIVP_SHIFT 20
83 #define PLL_BASE_DIVN_MASK (0x3FF<<8)
84 #define PLL_BASE_DIVN_SHIFT 8
85 #define PLL_BASE_DIVM_MASK (0x1F)
86 #define PLL_BASE_DIVM_SHIFT 0
87
88 #define PLL_OUT_RATIO_MASK (0xFF<<8)
89 #define PLL_OUT_RATIO_SHIFT 8
90 #define PLL_OUT_OVERRIDE (1<<2)
91 #define PLL_OUT_CLKEN (1<<1)
92 #define PLL_OUT_RESET_DISABLE (1<<0)
93
94 #define PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
95
96 #define PLL_MISC_DCCON_SHIFT 20
97 #define PLL_MISC_CPCON_SHIFT 8
98 #define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)
99 #define PLL_MISC_LFCON_SHIFT 4
100 #define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)
101 #define PLL_MISC_VCOCON_SHIFT 0
102 #define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)
103
104 #define PLLU_BASE_POST_DIV (1<<20)
105
106 #define PLLD_MISC_CLKENABLE (1<<30)
107 #define PLLD_MISC_DIV_RST (1<<23)
108 #define PLLD_MISC_DCCON_SHIFT 12
109
110 #define PLLE_MISC_READY (1 << 15)
111
112 #define PERIPH_CLK_TO_ENB_REG(c) ((c->u.periph.clk_num / 32) * 4)
113 #define PERIPH_CLK_TO_ENB_SET_REG(c) ((c->u.periph.clk_num / 32) * 8)
114 #define PERIPH_CLK_TO_ENB_BIT(c) (1 << (c->u.periph.clk_num % 32))
115
116 #define SUPER_CLK_MUX 0x00
117 #define SUPER_STATE_SHIFT 28
118 #define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)
119 #define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)
120 #define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)
121 #define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)
122 #define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)
123 #define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)
124 #define SUPER_SOURCE_MASK 0xF
125 #define SUPER_FIQ_SOURCE_SHIFT 12
126 #define SUPER_IRQ_SOURCE_SHIFT 8
127 #define SUPER_RUN_SOURCE_SHIFT 4
128 #define SUPER_IDLE_SOURCE_SHIFT 0
129
130 #define SUPER_CLK_DIVIDER 0x04
131
132 #define BUS_CLK_DISABLE (1<<3)
133 #define BUS_CLK_DIV_MASK 0x3
134
135 #define PMC_CTRL 0x0
136 #define PMC_CTRL_BLINK_ENB (1 << 7)
137
138 #define PMC_DPD_PADS_ORIDE 0x1c
139 #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20)
140
141 #define PMC_BLINK_TIMER_DATA_ON_SHIFT 0
142 #define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff
143 #define PMC_BLINK_TIMER_ENB (1 << 15)
144 #define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16
145 #define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff
146
147 static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
148 static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
149
150 /*
151 * Some clocks share a register with other clocks. Any clock op that
152 * non-atomically modifies a register used by another clock must lock
153 * clock_register_lock first.
154 */
155 static DEFINE_SPINLOCK(clock_register_lock);
156
157 #define clk_writel(value, reg) \
158 __raw_writel(value, (u32)reg_clk_base + (reg))
159 #define clk_readl(reg) \
160 __raw_readl((u32)reg_clk_base + (reg))
161 #define pmc_writel(value, reg) \
162 __raw_writel(value, (u32)reg_pmc_base + (reg))
163 #define pmc_readl(reg) \
164 __raw_readl((u32)reg_pmc_base + (reg))
165
166 unsigned long clk_measure_input_freq(void)
167 {
168 u32 clock_autodetect;
169 clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
170 do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY);
171 clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
172 if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) {
173 return 12000000;
174 } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) {
175 return 13000000;
176 } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) {
177 return 19200000;
178 } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
179 return 26000000;
180 } else {
181 pr_err("%s: Unexpected clock autodetect value %d", __func__, clock_autodetect);
182 BUG();
183 return 0;
184 }
185 }
186
187 static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate)
188 {
189 s64 divider_u71 = parent_rate * 2;
190 divider_u71 += rate - 1;
191 do_div(divider_u71, rate);
192
193 if (divider_u71 - 2 < 0)
194 return 0;
195
196 if (divider_u71 - 2 > 255)
197 return -EINVAL;
198
199 return divider_u71 - 2;
200 }
201
202 static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
203 {
204 s64 divider_u16;
205
206 divider_u16 = parent_rate;
207 divider_u16 += rate - 1;
208 do_div(divider_u16, rate);
209
210 if (divider_u16 - 1 < 0)
211 return 0;
212
213 if (divider_u16 - 1 > 255)
214 return -EINVAL;
215
216 return divider_u16 - 1;
217 }
218
219 /* clk_m functions */
220 static unsigned long tegra2_clk_m_autodetect_rate(struct clk *c)
221 {
222 u32 auto_clock_control = clk_readl(OSC_CTRL) & ~OSC_CTRL_OSC_FREQ_MASK;
223
224 c->rate = clk_measure_input_freq();
225 switch (c->rate) {
226 case 12000000:
227 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
228 break;
229 case 13000000:
230 auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
231 break;
232 case 19200000:
233 auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
234 break;
235 case 26000000:
236 auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
237 break;
238 default:
239 pr_err("%s: Unexpected clock rate %ld", __func__, c->rate);
240 BUG();
241 }
242 clk_writel(auto_clock_control, OSC_CTRL);
243 return c->rate;
244 }
245
246 static void tegra2_clk_m_init(struct clk *c)
247 {
248 pr_debug("%s on clock %s\n", __func__, c->name);
249 tegra2_clk_m_autodetect_rate(c);
250 }
251
252 static int tegra2_clk_m_enable(struct clk *c)
253 {
254 pr_debug("%s on clock %s\n", __func__, c->name);
255 return 0;
256 }
257
258 static void tegra2_clk_m_disable(struct clk *c)
259 {
260 pr_debug("%s on clock %s\n", __func__, c->name);
261 BUG();
262 }
263
264 static struct clk_ops tegra_clk_m_ops = {
265 .init = tegra2_clk_m_init,
266 .enable = tegra2_clk_m_enable,
267 .disable = tegra2_clk_m_disable,
268 };
269
270 void tegra2_periph_reset_assert(struct clk *c)
271 {
272 BUG_ON(!c->ops->reset);
273 c->ops->reset(c, true);
274 }
275
276 void tegra2_periph_reset_deassert(struct clk *c)
277 {
278 BUG_ON(!c->ops->reset);
279 c->ops->reset(c, false);
280 }
281
282 /* super clock functions */
283 /* "super clocks" on tegra have two-stage muxes and a clock skipping
284 * super divider. We will ignore the clock skipping divider, since we
285 * can't lower the voltage when using the clock skip, but we can if we
286 * lower the PLL frequency.
287 */
288 static void tegra2_super_clk_init(struct clk *c)
289 {
290 u32 val;
291 int source;
292 int shift;
293 const struct clk_mux_sel *sel;
294 val = clk_readl(c->reg + SUPER_CLK_MUX);
295 c->state = ON;
296 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
297 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
298 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
299 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
300 source = (val >> shift) & SUPER_SOURCE_MASK;
301 for (sel = c->inputs; sel->input != NULL; sel++) {
302 if (sel->value == source)
303 break;
304 }
305 BUG_ON(sel->input == NULL);
306 c->parent = sel->input;
307 }
308
309 static int tegra2_super_clk_enable(struct clk *c)
310 {
311 clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
312 return 0;
313 }
314
315 static void tegra2_super_clk_disable(struct clk *c)
316 {
317 pr_debug("%s on clock %s\n", __func__, c->name);
318
319 /* oops - don't disable the CPU clock! */
320 BUG();
321 }
322
323 static int tegra2_super_clk_set_parent(struct clk *c, struct clk *p)
324 {
325 u32 val;
326 const struct clk_mux_sel *sel;
327 int shift;
328
329 val = clk_readl(c->reg + SUPER_CLK_MUX);;
330 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
331 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
332 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
333 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
334 for (sel = c->inputs; sel->input != NULL; sel++) {
335 if (sel->input == p) {
336 val &= ~(SUPER_SOURCE_MASK << shift);
337 val |= sel->value << shift;
338
339 if (c->refcnt)
340 clk_enable(p);
341
342 clk_writel(val, c->reg);
343
344 if (c->refcnt && c->parent)
345 clk_disable(c->parent);
346
347 clk_reparent(c, p);
348 return 0;
349 }
350 }
351 return -EINVAL;
352 }
353
354 static struct clk_ops tegra_super_ops = {
355 .init = tegra2_super_clk_init,
356 .enable = tegra2_super_clk_enable,
357 .disable = tegra2_super_clk_disable,
358 .set_parent = tegra2_super_clk_set_parent,
359 };
360
361 /* virtual cpu clock functions */
362 /* some clocks can not be stopped (cpu, memory bus) while the SoC is running.
363 To change the frequency of these clocks, the parent pll may need to be
364 reprogrammed, so the clock must be moved off the pll, the pll reprogrammed,
365 and then the clock moved back to the pll. To hide this sequence, a virtual
366 clock handles it.
367 */
368 static void tegra2_cpu_clk_init(struct clk *c)
369 {
370 }
371
372 static int tegra2_cpu_clk_enable(struct clk *c)
373 {
374 return 0;
375 }
376
377 static void tegra2_cpu_clk_disable(struct clk *c)
378 {
379 pr_debug("%s on clock %s\n", __func__, c->name);
380
381 /* oops - don't disable the CPU clock! */
382 BUG();
383 }
384
385 static int tegra2_cpu_clk_set_rate(struct clk *c, unsigned long rate)
386 {
387 int ret;
388 /*
389 * Take an extra reference to the main pll so it doesn't turn
390 * off when we move the cpu off of it
391 */
392 clk_enable(c->u.cpu.main);
393
394 ret = clk_set_parent(c->parent, c->u.cpu.backup);
395 if (ret) {
396 pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.backup->name);
397 goto out;
398 }
399
400 if (rate == clk_get_rate(c->u.cpu.backup))
401 goto out;
402
403 ret = clk_set_rate(c->u.cpu.main, rate);
404 if (ret) {
405 pr_err("Failed to change cpu pll to %lu\n", rate);
406 goto out;
407 }
408
409 ret = clk_set_parent(c->parent, c->u.cpu.main);
410 if (ret) {
411 pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.main->name);
412 goto out;
413 }
414
415 out:
416 clk_disable(c->u.cpu.main);
417 return ret;
418 }
419
420 static struct clk_ops tegra_cpu_ops = {
421 .init = tegra2_cpu_clk_init,
422 .enable = tegra2_cpu_clk_enable,
423 .disable = tegra2_cpu_clk_disable,
424 .set_rate = tegra2_cpu_clk_set_rate,
425 };
426
427 /* bus clock functions */
428 static void tegra2_bus_clk_init(struct clk *c)
429 {
430 u32 val = clk_readl(c->reg);
431 c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
432 c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
433 c->mul = 1;
434 }
435
436 static int tegra2_bus_clk_enable(struct clk *c)
437 {
438 u32 val;
439 unsigned long flags;
440
441 spin_lock_irqsave(&clock_register_lock, flags);
442
443 val = clk_readl(c->reg);
444 val &= ~(BUS_CLK_DISABLE << c->reg_shift);
445 clk_writel(val, c->reg);
446
447 spin_unlock_irqrestore(&clock_register_lock, flags);
448
449 return 0;
450 }
451
452 static void tegra2_bus_clk_disable(struct clk *c)
453 {
454 u32 val;
455 unsigned long flags;
456
457 spin_lock_irqsave(&clock_register_lock, flags);
458
459 val = clk_readl(c->reg);
460 val |= BUS_CLK_DISABLE << c->reg_shift;
461 clk_writel(val, c->reg);
462
463 spin_unlock_irqrestore(&clock_register_lock, flags);
464 }
465
466 static int tegra2_bus_clk_set_rate(struct clk *c, unsigned long rate)
467 {
468 u32 val;
469 unsigned long parent_rate = clk_get_rate(c->parent);
470 unsigned long flags;
471 int ret = -EINVAL;
472 int i;
473
474 spin_lock_irqsave(&clock_register_lock, flags);
475
476 val = clk_readl(c->reg);
477 for (i = 1; i <= 4; i++) {
478 if (rate == parent_rate / i) {
479 val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
480 val |= (i - 1) << c->reg_shift;
481 clk_writel(val, c->reg);
482 c->div = i;
483 c->mul = 1;
484 ret = 0;
485 break;
486 }
487 }
488
489 spin_unlock_irqrestore(&clock_register_lock, flags);
490
491 return ret;
492 }
493
494 static struct clk_ops tegra_bus_ops = {
495 .init = tegra2_bus_clk_init,
496 .enable = tegra2_bus_clk_enable,
497 .disable = tegra2_bus_clk_disable,
498 .set_rate = tegra2_bus_clk_set_rate,
499 };
500
501 /* Blink output functions */
502
503 static void tegra2_blink_clk_init(struct clk *c)
504 {
505 u32 val;
506
507 val = pmc_readl(PMC_CTRL);
508 c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
509 c->mul = 1;
510 val = pmc_readl(c->reg);
511
512 if (val & PMC_BLINK_TIMER_ENB) {
513 unsigned int on_off;
514
515 on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
516 PMC_BLINK_TIMER_DATA_ON_MASK;
517 val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
518 val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
519 on_off += val;
520 /* each tick in the blink timer is 4 32KHz clocks */
521 c->div = on_off * 4;
522 } else {
523 c->div = 1;
524 }
525 }
526
527 static int tegra2_blink_clk_enable(struct clk *c)
528 {
529 u32 val;
530
531 val = pmc_readl(PMC_DPD_PADS_ORIDE);
532 pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
533
534 val = pmc_readl(PMC_CTRL);
535 pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
536
537 return 0;
538 }
539
540 static void tegra2_blink_clk_disable(struct clk *c)
541 {
542 u32 val;
543
544 val = pmc_readl(PMC_CTRL);
545 pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
546
547 val = pmc_readl(PMC_DPD_PADS_ORIDE);
548 pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
549 }
550
551 static int tegra2_blink_clk_set_rate(struct clk *c, unsigned long rate)
552 {
553 unsigned long parent_rate = clk_get_rate(c->parent);
554 if (rate >= parent_rate) {
555 c->div = 1;
556 pmc_writel(0, c->reg);
557 } else {
558 unsigned int on_off;
559 u32 val;
560
561 on_off = DIV_ROUND_UP(parent_rate / 8, rate);
562 c->div = on_off * 8;
563
564 val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
565 PMC_BLINK_TIMER_DATA_ON_SHIFT;
566 on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
567 on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
568 val |= on_off;
569 val |= PMC_BLINK_TIMER_ENB;
570 pmc_writel(val, c->reg);
571 }
572
573 return 0;
574 }
575
576 static struct clk_ops tegra_blink_clk_ops = {
577 .init = &tegra2_blink_clk_init,
578 .enable = &tegra2_blink_clk_enable,
579 .disable = &tegra2_blink_clk_disable,
580 .set_rate = &tegra2_blink_clk_set_rate,
581 };
582
583 /* PLL Functions */
584 static int tegra2_pll_clk_wait_for_lock(struct clk *c)
585 {
586 udelay(c->u.pll.lock_delay);
587
588 return 0;
589 }
590
591 static void tegra2_pll_clk_init(struct clk *c)
592 {
593 u32 val = clk_readl(c->reg + PLL_BASE);
594
595 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
596
597 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
598 pr_warning("Clock %s has unknown fixed frequency\n", c->name);
599 c->mul = 1;
600 c->div = 1;
601 } else if (val & PLL_BASE_BYPASS) {
602 c->mul = 1;
603 c->div = 1;
604 } else {
605 c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
606 c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
607 if (c->flags & PLLU)
608 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
609 else
610 c->div *= (val & PLL_BASE_DIVP_MASK) ? 2 : 1;
611 }
612 }
613
614 static int tegra2_pll_clk_enable(struct clk *c)
615 {
616 u32 val;
617 pr_debug("%s on clock %s\n", __func__, c->name);
618
619 val = clk_readl(c->reg + PLL_BASE);
620 val &= ~PLL_BASE_BYPASS;
621 val |= PLL_BASE_ENABLE;
622 clk_writel(val, c->reg + PLL_BASE);
623
624 tegra2_pll_clk_wait_for_lock(c);
625
626 return 0;
627 }
628
629 static void tegra2_pll_clk_disable(struct clk *c)
630 {
631 u32 val;
632 pr_debug("%s on clock %s\n", __func__, c->name);
633
634 val = clk_readl(c->reg);
635 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
636 clk_writel(val, c->reg);
637 }
638
639 static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate)
640 {
641 u32 val;
642 unsigned long input_rate;
643 const struct clk_pll_freq_table *sel;
644
645 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
646
647 input_rate = clk_get_rate(c->parent);
648 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
649 if (sel->input_rate == input_rate && sel->output_rate == rate) {
650 c->mul = sel->n;
651 c->div = sel->m * sel->p;
652
653 val = clk_readl(c->reg + PLL_BASE);
654 if (c->flags & PLL_FIXED)
655 val |= PLL_BASE_OVERRIDE;
656 val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK |
657 PLL_BASE_DIVM_MASK);
658 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
659 (sel->n << PLL_BASE_DIVN_SHIFT);
660 BUG_ON(sel->p < 1 || sel->p > 2);
661 if (c->flags & PLLU) {
662 if (sel->p == 1)
663 val |= PLLU_BASE_POST_DIV;
664 } else {
665 if (sel->p == 2)
666 val |= 1 << PLL_BASE_DIVP_SHIFT;
667 }
668 clk_writel(val, c->reg + PLL_BASE);
669
670 if (c->flags & PLL_HAS_CPCON) {
671 val = clk_readl(c->reg + PLL_MISC(c));
672 val &= ~PLL_MISC_CPCON_MASK;
673 val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
674 clk_writel(val, c->reg + PLL_MISC(c));
675 }
676
677 if (c->state == ON)
678 tegra2_pll_clk_enable(c);
679
680 return 0;
681 }
682 }
683 return -EINVAL;
684 }
685
686 static struct clk_ops tegra_pll_ops = {
687 .init = tegra2_pll_clk_init,
688 .enable = tegra2_pll_clk_enable,
689 .disable = tegra2_pll_clk_disable,
690 .set_rate = tegra2_pll_clk_set_rate,
691 };
692
693 static void tegra2_pllx_clk_init(struct clk *c)
694 {
695 tegra2_pll_clk_init(c);
696
697 if (tegra_sku_id() == 7)
698 c->max_rate = 750000000;
699 }
700
701 static struct clk_ops tegra_pllx_ops = {
702 .init = tegra2_pllx_clk_init,
703 .enable = tegra2_pll_clk_enable,
704 .disable = tegra2_pll_clk_disable,
705 .set_rate = tegra2_pll_clk_set_rate,
706 };
707
708 static int tegra2_plle_clk_enable(struct clk *c)
709 {
710 u32 val;
711
712 pr_debug("%s on clock %s\n", __func__, c->name);
713
714 mdelay(1);
715
716 val = clk_readl(c->reg + PLL_BASE);
717 if (!(val & PLLE_MISC_READY))
718 return -EBUSY;
719
720 val = clk_readl(c->reg + PLL_BASE);
721 val |= PLL_BASE_ENABLE | PLL_BASE_BYPASS;
722 clk_writel(val, c->reg + PLL_BASE);
723
724 return 0;
725 }
726
727 static struct clk_ops tegra_plle_ops = {
728 .init = tegra2_pll_clk_init,
729 .enable = tegra2_plle_clk_enable,
730 .set_rate = tegra2_pll_clk_set_rate,
731 };
732
733 /* Clock divider ops */
734 static void tegra2_pll_div_clk_init(struct clk *c)
735 {
736 u32 val = clk_readl(c->reg);
737 u32 divu71;
738 val >>= c->reg_shift;
739 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
740 if (!(val & PLL_OUT_RESET_DISABLE))
741 c->state = OFF;
742
743 if (c->flags & DIV_U71) {
744 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
745 c->div = (divu71 + 2);
746 c->mul = 2;
747 } else if (c->flags & DIV_2) {
748 c->div = 2;
749 c->mul = 1;
750 } else {
751 c->div = 1;
752 c->mul = 1;
753 }
754 }
755
756 static int tegra2_pll_div_clk_enable(struct clk *c)
757 {
758 u32 val;
759 u32 new_val;
760 unsigned long flags;
761
762 pr_debug("%s: %s\n", __func__, c->name);
763 if (c->flags & DIV_U71) {
764 spin_lock_irqsave(&clock_register_lock, flags);
765 val = clk_readl(c->reg);
766 new_val = val >> c->reg_shift;
767 new_val &= 0xFFFF;
768
769 new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
770
771 val &= ~(0xFFFF << c->reg_shift);
772 val |= new_val << c->reg_shift;
773 clk_writel(val, c->reg);
774 spin_unlock_irqrestore(&clock_register_lock, flags);
775 return 0;
776 } else if (c->flags & DIV_2) {
777 BUG_ON(!(c->flags & PLLD));
778 spin_lock_irqsave(&clock_register_lock, flags);
779 val = clk_readl(c->reg);
780 val &= ~PLLD_MISC_DIV_RST;
781 clk_writel(val, c->reg);
782 spin_unlock_irqrestore(&clock_register_lock, flags);
783 return 0;
784 }
785 return -EINVAL;
786 }
787
788 static void tegra2_pll_div_clk_disable(struct clk *c)
789 {
790 u32 val;
791 u32 new_val;
792 unsigned long flags;
793
794 pr_debug("%s: %s\n", __func__, c->name);
795 if (c->flags & DIV_U71) {
796 spin_lock_irqsave(&clock_register_lock, flags);
797 val = clk_readl(c->reg);
798 new_val = val >> c->reg_shift;
799 new_val &= 0xFFFF;
800
801 new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
802
803 val &= ~(0xFFFF << c->reg_shift);
804 val |= new_val << c->reg_shift;
805 clk_writel(val, c->reg);
806 spin_unlock_irqrestore(&clock_register_lock, flags);
807 } else if (c->flags & DIV_2) {
808 BUG_ON(!(c->flags & PLLD));
809 spin_lock_irqsave(&clock_register_lock, flags);
810 val = clk_readl(c->reg);
811 val |= PLLD_MISC_DIV_RST;
812 clk_writel(val, c->reg);
813 spin_unlock_irqrestore(&clock_register_lock, flags);
814 }
815 }
816
817 static int tegra2_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
818 {
819 u32 val;
820 u32 new_val;
821 int divider_u71;
822 unsigned long parent_rate = clk_get_rate(c->parent);
823 unsigned long flags;
824
825 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
826 if (c->flags & DIV_U71) {
827 divider_u71 = clk_div71_get_divider(parent_rate, rate);
828 if (divider_u71 >= 0) {
829 spin_lock_irqsave(&clock_register_lock, flags);
830 val = clk_readl(c->reg);
831 new_val = val >> c->reg_shift;
832 new_val &= 0xFFFF;
833 if (c->flags & DIV_U71_FIXED)
834 new_val |= PLL_OUT_OVERRIDE;
835 new_val &= ~PLL_OUT_RATIO_MASK;
836 new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
837
838 val &= ~(0xFFFF << c->reg_shift);
839 val |= new_val << c->reg_shift;
840 clk_writel(val, c->reg);
841 c->div = divider_u71 + 2;
842 c->mul = 2;
843 spin_unlock_irqrestore(&clock_register_lock, flags);
844 return 0;
845 }
846 } else if (c->flags & DIV_2) {
847 if (parent_rate == rate * 2)
848 return 0;
849 }
850 return -EINVAL;
851 }
852
853 static long tegra2_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
854 {
855 int divider;
856 unsigned long parent_rate = clk_get_rate(c->parent);
857 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
858
859 if (c->flags & DIV_U71) {
860 divider = clk_div71_get_divider(parent_rate, rate);
861 if (divider < 0)
862 return divider;
863 return parent_rate * 2 / (divider + 2);
864 } else if (c->flags & DIV_2) {
865 return parent_rate / 2;
866 }
867 return -EINVAL;
868 }
869
870 static struct clk_ops tegra_pll_div_ops = {
871 .init = tegra2_pll_div_clk_init,
872 .enable = tegra2_pll_div_clk_enable,
873 .disable = tegra2_pll_div_clk_disable,
874 .set_rate = tegra2_pll_div_clk_set_rate,
875 .round_rate = tegra2_pll_div_clk_round_rate,
876 };
877
878 /* Periph clk ops */
879
880 static void tegra2_periph_clk_init(struct clk *c)
881 {
882 u32 val = clk_readl(c->reg);
883 const struct clk_mux_sel *mux = 0;
884 const struct clk_mux_sel *sel;
885 if (c->flags & MUX) {
886 for (sel = c->inputs; sel->input != NULL; sel++) {
887 if (val >> PERIPH_CLK_SOURCE_SHIFT == sel->value)
888 mux = sel;
889 }
890 BUG_ON(!mux);
891
892 c->parent = mux->input;
893 } else {
894 c->parent = c->inputs[0].input;
895 }
896
897 if (c->flags & DIV_U71) {
898 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
899 c->div = divu71 + 2;
900 c->mul = 2;
901 } else if (c->flags & DIV_U16) {
902 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
903 c->div = divu16 + 1;
904 c->mul = 1;
905 } else {
906 c->div = 1;
907 c->mul = 1;
908 }
909
910 c->state = ON;
911 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
912 PERIPH_CLK_TO_ENB_BIT(c)))
913 c->state = OFF;
914 if (!(c->flags & PERIPH_NO_RESET))
915 if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) &
916 PERIPH_CLK_TO_ENB_BIT(c))
917 c->state = OFF;
918 }
919
920 static int tegra2_periph_clk_enable(struct clk *c)
921 {
922 u32 val;
923 pr_debug("%s on clock %s\n", __func__, c->name);
924
925 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
926 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
927 if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET))
928 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
929 RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
930 if (c->flags & PERIPH_EMC_ENB) {
931 /* The EMC peripheral clock has 2 extra enable bits */
932 /* FIXME: Do they need to be disabled? */
933 val = clk_readl(c->reg);
934 val |= 0x3 << 24;
935 clk_writel(val, c->reg);
936 }
937 return 0;
938 }
939
940 static void tegra2_periph_clk_disable(struct clk *c)
941 {
942 pr_debug("%s on clock %s\n", __func__, c->name);
943
944 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
945 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
946 }
947
948 static void tegra2_periph_clk_reset(struct clk *c, bool assert)
949 {
950 unsigned long base = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
951
952 pr_debug("%s %s on clock %s\n", __func__,
953 assert ? "assert" : "deassert", c->name);
954 if (!(c->flags & PERIPH_NO_RESET))
955 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
956 base + PERIPH_CLK_TO_ENB_SET_REG(c));
957 }
958
959 static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p)
960 {
961 u32 val;
962 const struct clk_mux_sel *sel;
963 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
964 for (sel = c->inputs; sel->input != NULL; sel++) {
965 if (sel->input == p) {
966 val = clk_readl(c->reg);
967 val &= ~PERIPH_CLK_SOURCE_MASK;
968 val |= (sel->value) << PERIPH_CLK_SOURCE_SHIFT;
969
970 if (c->refcnt)
971 clk_enable(p);
972
973 clk_writel(val, c->reg);
974
975 if (c->refcnt && c->parent)
976 clk_disable(c->parent);
977
978 clk_reparent(c, p);
979 return 0;
980 }
981 }
982
983 return -EINVAL;
984 }
985
986 static int tegra2_periph_clk_set_rate(struct clk *c, unsigned long rate)
987 {
988 u32 val;
989 int divider;
990 unsigned long parent_rate = clk_get_rate(c->parent);
991
992 if (c->flags & DIV_U71) {
993 divider = clk_div71_get_divider(parent_rate, rate);
994 if (divider >= 0) {
995 val = clk_readl(c->reg);
996 val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
997 val |= divider;
998 clk_writel(val, c->reg);
999 c->div = divider + 2;
1000 c->mul = 2;
1001 return 0;
1002 }
1003 } else if (c->flags & DIV_U16) {
1004 divider = clk_div16_get_divider(parent_rate, rate);
1005 if (divider >= 0) {
1006 val = clk_readl(c->reg);
1007 val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
1008 val |= divider;
1009 clk_writel(val, c->reg);
1010 c->div = divider + 1;
1011 c->mul = 1;
1012 return 0;
1013 }
1014 } else if (parent_rate <= rate) {
1015 c->div = 1;
1016 c->mul = 1;
1017 return 0;
1018 }
1019 return -EINVAL;
1020 }
1021
1022 static long tegra2_periph_clk_round_rate(struct clk *c,
1023 unsigned long rate)
1024 {
1025 int divider;
1026 unsigned long parent_rate = clk_get_rate(c->parent);
1027 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
1028
1029 if (c->flags & DIV_U71) {
1030 divider = clk_div71_get_divider(parent_rate, rate);
1031 if (divider < 0)
1032 return divider;
1033
1034 return parent_rate * 2 / (divider + 2);
1035 } else if (c->flags & DIV_U16) {
1036 divider = clk_div16_get_divider(parent_rate, rate);
1037 if (divider < 0)
1038 return divider;
1039 return parent_rate / (divider + 1);
1040 }
1041 return -EINVAL;
1042 }
1043
1044 static struct clk_ops tegra_periph_clk_ops = {
1045 .init = &tegra2_periph_clk_init,
1046 .enable = &tegra2_periph_clk_enable,
1047 .disable = &tegra2_periph_clk_disable,
1048 .set_parent = &tegra2_periph_clk_set_parent,
1049 .set_rate = &tegra2_periph_clk_set_rate,
1050 .round_rate = &tegra2_periph_clk_round_rate,
1051 .reset = &tegra2_periph_clk_reset,
1052 };
1053
1054 /* Clock doubler ops */
1055 static void tegra2_clk_double_init(struct clk *c)
1056 {
1057 c->mul = 2;
1058 c->div = 1;
1059 c->state = ON;
1060 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1061 PERIPH_CLK_TO_ENB_BIT(c)))
1062 c->state = OFF;
1063 };
1064
1065 static int tegra2_clk_double_set_rate(struct clk *c, unsigned long rate)
1066 {
1067 if (rate != 2 * clk_get_rate(c->parent))
1068 return -EINVAL;
1069 c->mul = 2;
1070 c->div = 1;
1071 return 0;
1072 }
1073
1074 static struct clk_ops tegra_clk_double_ops = {
1075 .init = &tegra2_clk_double_init,
1076 .enable = &tegra2_periph_clk_enable,
1077 .disable = &tegra2_periph_clk_disable,
1078 .set_rate = &tegra2_clk_double_set_rate,
1079 };
1080
1081 /* Audio sync clock ops */
1082 static void tegra2_audio_sync_clk_init(struct clk *c)
1083 {
1084 int source;
1085 const struct clk_mux_sel *sel;
1086 u32 val = clk_readl(c->reg);
1087 c->state = (val & (1<<4)) ? OFF : ON;
1088 source = val & 0xf;
1089 for (sel = c->inputs; sel->input != NULL; sel++)
1090 if (sel->value == source)
1091 break;
1092 BUG_ON(sel->input == NULL);
1093 c->parent = sel->input;
1094 }
1095
1096 static int tegra2_audio_sync_clk_enable(struct clk *c)
1097 {
1098 clk_writel(0, c->reg);
1099 return 0;
1100 }
1101
1102 static void tegra2_audio_sync_clk_disable(struct clk *c)
1103 {
1104 clk_writel(1, c->reg);
1105 }
1106
1107 static int tegra2_audio_sync_clk_set_parent(struct clk *c, struct clk *p)
1108 {
1109 u32 val;
1110 const struct clk_mux_sel *sel;
1111 for (sel = c->inputs; sel->input != NULL; sel++) {
1112 if (sel->input == p) {
1113 val = clk_readl(c->reg);
1114 val &= ~0xf;
1115 val |= sel->value;
1116
1117 if (c->refcnt)
1118 clk_enable(p);
1119
1120 clk_writel(val, c->reg);
1121
1122 if (c->refcnt && c->parent)
1123 clk_disable(c->parent);
1124
1125 clk_reparent(c, p);
1126 return 0;
1127 }
1128 }
1129
1130 return -EINVAL;
1131 }
1132
1133 static int tegra2_audio_sync_clk_set_rate(struct clk *c, unsigned long rate)
1134 {
1135 unsigned long parent_rate;
1136 if (!c->parent) {
1137 pr_err("%s: clock has no parent\n", __func__);
1138 return -EINVAL;
1139 }
1140 parent_rate = c->parent->rate;
1141 if (rate != parent_rate) {
1142 pr_err("%s: %s/%ld differs from parent %s/%ld\n",
1143 __func__,
1144 c->name, rate,
1145 c->parent->name, parent_rate);
1146 return -EINVAL;
1147 }
1148 c->rate = parent_rate;
1149 return 0;
1150 }
1151
1152 static struct clk_ops tegra_audio_sync_clk_ops = {
1153 .init = tegra2_audio_sync_clk_init,
1154 .enable = tegra2_audio_sync_clk_enable,
1155 .disable = tegra2_audio_sync_clk_disable,
1156 .set_rate = tegra2_audio_sync_clk_set_rate,
1157 .set_parent = tegra2_audio_sync_clk_set_parent,
1158 };
1159
1160 /* cdev1 and cdev2 (dap_mclk1 and dap_mclk2) ops */
1161
1162 static void tegra2_cdev_clk_init(struct clk *c)
1163 {
1164 /* We could un-tristate the cdev1 or cdev2 pingroup here; this is
1165 * currently done in the pinmux code. */
1166 c->state = ON;
1167 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1168 PERIPH_CLK_TO_ENB_BIT(c)))
1169 c->state = OFF;
1170 }
1171
1172 static int tegra2_cdev_clk_enable(struct clk *c)
1173 {
1174 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1175 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
1176 return 0;
1177 }
1178
1179 static void tegra2_cdev_clk_disable(struct clk *c)
1180 {
1181 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1182 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1183 }
1184
1185 static struct clk_ops tegra_cdev_clk_ops = {
1186 .init = &tegra2_cdev_clk_init,
1187 .enable = &tegra2_cdev_clk_enable,
1188 .disable = &tegra2_cdev_clk_disable,
1189 };
1190
1191 /* shared bus ops */
1192 /*
1193 * Some clocks may have multiple downstream users that need to request a
1194 * higher clock rate. Shared bus clocks provide a unique shared_bus_user
1195 * clock to each user. The frequency of the bus is set to the highest
1196 * enabled shared_bus_user clock, with a minimum value set by the
1197 * shared bus.
1198 */
1199 static int tegra_clk_shared_bus_update(struct clk *bus)
1200 {
1201 struct clk *c;
1202 unsigned long rate = bus->min_rate;
1203
1204 list_for_each_entry(c, &bus->shared_bus_list, u.shared_bus_user.node)
1205 if (c->u.shared_bus_user.enabled)
1206 rate = max(c->u.shared_bus_user.rate, rate);
1207
1208 if (rate == clk_get_rate_locked(bus))
1209 return 0;
1210
1211 return clk_set_rate_locked(bus, rate);
1212 };
1213
1214 static void tegra_clk_shared_bus_init(struct clk *c)
1215 {
1216 unsigned long flags;
1217
1218 c->max_rate = c->parent->max_rate;
1219 c->u.shared_bus_user.rate = c->parent->max_rate;
1220 c->state = OFF;
1221 c->set = true;
1222
1223 spin_lock_irqsave(&c->parent->spinlock, flags);
1224
1225 list_add_tail(&c->u.shared_bus_user.node,
1226 &c->parent->shared_bus_list);
1227
1228 spin_unlock_irqrestore(&c->parent->spinlock, flags);
1229 }
1230
1231 static int tegra_clk_shared_bus_set_rate(struct clk *c, unsigned long rate)
1232 {
1233 unsigned long flags;
1234 int ret;
1235
1236 rate = clk_round_rate(c->parent, rate);
1237 if (rate < 0)
1238 return rate;
1239
1240 spin_lock_irqsave(&c->parent->spinlock, flags);
1241
1242 c->u.shared_bus_user.rate = rate;
1243 ret = tegra_clk_shared_bus_update(c->parent);
1244
1245 spin_unlock_irqrestore(&c->parent->spinlock, flags);
1246
1247 return ret;
1248 }
1249
1250 static long tegra_clk_shared_bus_round_rate(struct clk *c, unsigned long rate)
1251 {
1252 return clk_round_rate(c->parent, rate);
1253 }
1254
1255 static int tegra_clk_shared_bus_enable(struct clk *c)
1256 {
1257 unsigned long flags;
1258 int ret;
1259
1260 spin_lock_irqsave(&c->parent->spinlock, flags);
1261
1262 c->u.shared_bus_user.enabled = true;
1263 ret = tegra_clk_shared_bus_update(c->parent);
1264
1265 spin_unlock_irqrestore(&c->parent->spinlock, flags);
1266
1267 return ret;
1268 }
1269
1270 static void tegra_clk_shared_bus_disable(struct clk *c)
1271 {
1272 unsigned long flags;
1273 int ret;
1274
1275 spin_lock_irqsave(&c->parent->spinlock, flags);
1276
1277 c->u.shared_bus_user.enabled = false;
1278 ret = tegra_clk_shared_bus_update(c->parent);
1279 WARN_ON_ONCE(ret);
1280
1281 spin_unlock_irqrestore(&c->parent->spinlock, flags);
1282 }
1283
1284 static struct clk_ops tegra_clk_shared_bus_ops = {
1285 .init = tegra_clk_shared_bus_init,
1286 .enable = tegra_clk_shared_bus_enable,
1287 .disable = tegra_clk_shared_bus_disable,
1288 .set_rate = tegra_clk_shared_bus_set_rate,
1289 .round_rate = tegra_clk_shared_bus_round_rate,
1290 };
1291
1292
1293 /* Clock definitions */
1294 static struct clk tegra_clk_32k = {
1295 .name = "clk_32k",
1296 .rate = 32768,
1297 .ops = NULL,
1298 .max_rate = 32768,
1299 };
1300
1301 static struct clk_pll_freq_table tegra_pll_s_freq_table[] = {
1302 {32768, 12000000, 366, 1, 1, 0},
1303 {32768, 13000000, 397, 1, 1, 0},
1304 {32768, 19200000, 586, 1, 1, 0},
1305 {32768, 26000000, 793, 1, 1, 0},
1306 {0, 0, 0, 0, 0, 0},
1307 };
1308
1309 static struct clk tegra_pll_s = {
1310 .name = "pll_s",
1311 .flags = PLL_ALT_MISC_REG,
1312 .ops = &tegra_pll_ops,
1313 .parent = &tegra_clk_32k,
1314 .max_rate = 26000000,
1315 .reg = 0xf0,
1316 .u.pll = {
1317 .input_min = 32768,
1318 .input_max = 32768,
1319 .cf_min = 0, /* FIXME */
1320 .cf_max = 0, /* FIXME */
1321 .vco_min = 12000000,
1322 .vco_max = 26000000,
1323 .freq_table = tegra_pll_s_freq_table,
1324 .lock_delay = 300,
1325 },
1326 };
1327
1328 static struct clk_mux_sel tegra_clk_m_sel[] = {
1329 { .input = &tegra_clk_32k, .value = 0},
1330 { .input = &tegra_pll_s, .value = 1},
1331 { 0, 0},
1332 };
1333
1334 static struct clk tegra_clk_m = {
1335 .name = "clk_m",
1336 .flags = ENABLE_ON_INIT,
1337 .ops = &tegra_clk_m_ops,
1338 .inputs = tegra_clk_m_sel,
1339 .reg = 0x1fc,
1340 .reg_shift = 28,
1341 .max_rate = 26000000,
1342 };
1343
1344 static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
1345 { 0, 0, 0, 0, 0, 0 },
1346 };
1347
1348 static struct clk tegra_pll_c = {
1349 .name = "pll_c",
1350 .flags = PLL_HAS_CPCON,
1351 .ops = &tegra_pll_ops,
1352 .reg = 0x80,
1353 .parent = &tegra_clk_m,
1354 .max_rate = 600000000,
1355 .u.pll = {
1356 .input_min = 2000000,
1357 .input_max = 31000000,
1358 .cf_min = 1000000,
1359 .cf_max = 6000000,
1360 .vco_min = 20000000,
1361 .vco_max = 1400000000,
1362 .freq_table = tegra_pll_c_freq_table,
1363 .lock_delay = 300,
1364 },
1365 };
1366
1367 static struct clk tegra_pll_c_out1 = {
1368 .name = "pll_c_out1",
1369 .ops = &tegra_pll_div_ops,
1370 .flags = DIV_U71,
1371 .parent = &tegra_pll_c,
1372 .reg = 0x84,
1373 .reg_shift = 0,
1374 .max_rate = 600000000,
1375 };
1376
1377 static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
1378 { 12000000, 666000000, 666, 12, 1, 8},
1379 { 13000000, 666000000, 666, 13, 1, 8},
1380 { 19200000, 666000000, 555, 16, 1, 8},
1381 { 26000000, 666000000, 666, 26, 1, 8},
1382 { 12000000, 600000000, 600, 12, 1, 8},
1383 { 13000000, 600000000, 600, 13, 1, 8},
1384 { 19200000, 600000000, 375, 12, 1, 6},
1385 { 26000000, 600000000, 600, 26, 1, 8},
1386 { 0, 0, 0, 0, 0, 0 },
1387 };
1388
1389 static struct clk tegra_pll_m = {
1390 .name = "pll_m",
1391 .flags = PLL_HAS_CPCON,
1392 .ops = &tegra_pll_ops,
1393 .reg = 0x90,
1394 .parent = &tegra_clk_m,
1395 .max_rate = 800000000,
1396 .u.pll = {
1397 .input_min = 2000000,
1398 .input_max = 31000000,
1399 .cf_min = 1000000,
1400 .cf_max = 6000000,
1401 .vco_min = 20000000,
1402 .vco_max = 1200000000,
1403 .freq_table = tegra_pll_m_freq_table,
1404 .lock_delay = 300,
1405 },
1406 };
1407
1408 static struct clk tegra_pll_m_out1 = {
1409 .name = "pll_m_out1",
1410 .ops = &tegra_pll_div_ops,
1411 .flags = DIV_U71,
1412 .parent = &tegra_pll_m,
1413 .reg = 0x94,
1414 .reg_shift = 0,
1415 .max_rate = 600000000,
1416 };
1417
1418 static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
1419 { 12000000, 216000000, 432, 12, 2, 8},
1420 { 13000000, 216000000, 432, 13, 2, 8},
1421 { 19200000, 216000000, 90, 4, 2, 1},
1422 { 26000000, 216000000, 432, 26, 2, 8},
1423 { 12000000, 432000000, 432, 12, 1, 8},
1424 { 13000000, 432000000, 432, 13, 1, 8},
1425 { 19200000, 432000000, 90, 4, 1, 1},
1426 { 26000000, 432000000, 432, 26, 1, 8},
1427 { 0, 0, 0, 0, 0, 0 },
1428 };
1429
1430 static struct clk tegra_pll_p = {
1431 .name = "pll_p",
1432 .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
1433 .ops = &tegra_pll_ops,
1434 .reg = 0xa0,
1435 .parent = &tegra_clk_m,
1436 .max_rate = 432000000,
1437 .u.pll = {
1438 .input_min = 2000000,
1439 .input_max = 31000000,
1440 .cf_min = 1000000,
1441 .cf_max = 6000000,
1442 .vco_min = 20000000,
1443 .vco_max = 1400000000,
1444 .freq_table = tegra_pll_p_freq_table,
1445 .lock_delay = 300,
1446 },
1447 };
1448
1449 static struct clk tegra_pll_p_out1 = {
1450 .name = "pll_p_out1",
1451 .ops = &tegra_pll_div_ops,
1452 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1453 .parent = &tegra_pll_p,
1454 .reg = 0xa4,
1455 .reg_shift = 0,
1456 .max_rate = 432000000,
1457 };
1458
1459 static struct clk tegra_pll_p_out2 = {
1460 .name = "pll_p_out2",
1461 .ops = &tegra_pll_div_ops,
1462 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1463 .parent = &tegra_pll_p,
1464 .reg = 0xa4,
1465 .reg_shift = 16,
1466 .max_rate = 432000000,
1467 };
1468
1469 static struct clk tegra_pll_p_out3 = {
1470 .name = "pll_p_out3",
1471 .ops = &tegra_pll_div_ops,
1472 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1473 .parent = &tegra_pll_p,
1474 .reg = 0xa8,
1475 .reg_shift = 0,
1476 .max_rate = 432000000,
1477 };
1478
1479 static struct clk tegra_pll_p_out4 = {
1480 .name = "pll_p_out4",
1481 .ops = &tegra_pll_div_ops,
1482 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1483 .parent = &tegra_pll_p,
1484 .reg = 0xa8,
1485 .reg_shift = 16,
1486 .max_rate = 432000000,
1487 };
1488
1489 static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
1490 { 28800000, 56448000, 49, 25, 1, 1},
1491 { 28800000, 73728000, 64, 25, 1, 1},
1492 { 28800000, 11289600, 49, 25, 1, 1},
1493 { 28800000, 12288000, 64, 25, 1, 1},
1494 { 28800000, 24000000, 5, 6, 1, 1},
1495 { 0, 0, 0, 0, 0, 0 },
1496 };
1497
1498 static struct clk tegra_pll_a = {
1499 .name = "pll_a",
1500 .flags = PLL_HAS_CPCON,
1501 .ops = &tegra_pll_ops,
1502 .reg = 0xb0,
1503 .parent = &tegra_pll_p_out1,
1504 .max_rate = 56448000,
1505 .u.pll = {
1506 .input_min = 2000000,
1507 .input_max = 31000000,
1508 .cf_min = 1000000,
1509 .cf_max = 6000000,
1510 .vco_min = 20000000,
1511 .vco_max = 1400000000,
1512 .freq_table = tegra_pll_a_freq_table,
1513 .lock_delay = 300,
1514 },
1515 };
1516
1517 static struct clk tegra_pll_a_out0 = {
1518 .name = "pll_a_out0",
1519 .ops = &tegra_pll_div_ops,
1520 .flags = DIV_U71,
1521 .parent = &tegra_pll_a,
1522 .reg = 0xb4,
1523 .reg_shift = 0,
1524 .max_rate = 56448000,
1525 };
1526
1527 static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
1528 { 12000000, 216000000, 216, 12, 1, 4},
1529 { 13000000, 216000000, 216, 13, 1, 4},
1530 { 19200000, 216000000, 135, 12, 1, 3},
1531 { 26000000, 216000000, 216, 26, 1, 4},
1532
1533 { 12000000, 594000000, 594, 12, 1, 8},
1534 { 13000000, 594000000, 594, 13, 1, 8},
1535 { 19200000, 594000000, 495, 16, 1, 8},
1536 { 26000000, 594000000, 594, 26, 1, 8},
1537
1538 { 12000000, 1000000000, 1000, 12, 1, 12},
1539 { 13000000, 1000000000, 1000, 13, 1, 12},
1540 { 19200000, 1000000000, 625, 12, 1, 8},
1541 { 26000000, 1000000000, 1000, 26, 1, 12},
1542
1543 { 0, 0, 0, 0, 0, 0 },
1544 };
1545
1546 static struct clk tegra_pll_d = {
1547 .name = "pll_d",
1548 .flags = PLL_HAS_CPCON | PLLD,
1549 .ops = &tegra_pll_ops,
1550 .reg = 0xd0,
1551 .parent = &tegra_clk_m,
1552 .max_rate = 1000000000,
1553 .u.pll = {
1554 .input_min = 2000000,
1555 .input_max = 40000000,
1556 .cf_min = 1000000,
1557 .cf_max = 6000000,
1558 .vco_min = 40000000,
1559 .vco_max = 1000000000,
1560 .freq_table = tegra_pll_d_freq_table,
1561 .lock_delay = 1000,
1562 },
1563 };
1564
1565 static struct clk tegra_pll_d_out0 = {
1566 .name = "pll_d_out0",
1567 .ops = &tegra_pll_div_ops,
1568 .flags = DIV_2 | PLLD,
1569 .parent = &tegra_pll_d,
1570 .max_rate = 500000000,
1571 };
1572
1573 static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
1574 { 12000000, 480000000, 960, 12, 2, 0},
1575 { 13000000, 480000000, 960, 13, 2, 0},
1576 { 19200000, 480000000, 200, 4, 2, 0},
1577 { 26000000, 480000000, 960, 26, 2, 0},
1578 { 0, 0, 0, 0, 0, 0 },
1579 };
1580
1581 static struct clk tegra_pll_u = {
1582 .name = "pll_u",
1583 .flags = PLLU,
1584 .ops = &tegra_pll_ops,
1585 .reg = 0xc0,
1586 .parent = &tegra_clk_m,
1587 .max_rate = 480000000,
1588 .u.pll = {
1589 .input_min = 2000000,
1590 .input_max = 40000000,
1591 .cf_min = 1000000,
1592 .cf_max = 6000000,
1593 .vco_min = 480000000,
1594 .vco_max = 960000000,
1595 .freq_table = tegra_pll_u_freq_table,
1596 .lock_delay = 1000,
1597 },
1598 };
1599
1600 static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
1601 /* 1 GHz */
1602 { 12000000, 1000000000, 1000, 12, 1, 12},
1603 { 13000000, 1000000000, 1000, 13, 1, 12},
1604 { 19200000, 1000000000, 625, 12, 1, 8},
1605 { 26000000, 1000000000, 1000, 26, 1, 12},
1606
1607 /* 912 MHz */
1608 { 12000000, 912000000, 912, 12, 1, 12},
1609 { 13000000, 912000000, 912, 13, 1, 12},
1610 { 19200000, 912000000, 760, 16, 1, 8},
1611 { 26000000, 912000000, 912, 26, 1, 12},
1612
1613 /* 816 MHz */
1614 { 12000000, 816000000, 816, 12, 1, 12},
1615 { 13000000, 816000000, 816, 13, 1, 12},
1616 { 19200000, 816000000, 680, 16, 1, 8},
1617 { 26000000, 816000000, 816, 26, 1, 12},
1618
1619 /* 760 MHz */
1620 { 12000000, 760000000, 760, 12, 1, 12},
1621 { 13000000, 760000000, 760, 13, 1, 12},
1622 { 19200000, 760000000, 950, 24, 1, 8},
1623 { 26000000, 760000000, 760, 26, 1, 12},
1624
1625 /* 608 MHz */
1626 { 12000000, 608000000, 760, 12, 1, 12},
1627 { 13000000, 608000000, 760, 13, 1, 12},
1628 { 19200000, 608000000, 380, 12, 1, 8},
1629 { 26000000, 608000000, 760, 26, 1, 12},
1630
1631 /* 456 MHz */
1632 { 12000000, 456000000, 456, 12, 1, 12},
1633 { 13000000, 456000000, 456, 13, 1, 12},
1634 { 19200000, 456000000, 380, 16, 1, 8},
1635 { 26000000, 456000000, 456, 26, 1, 12},
1636
1637 /* 312 MHz */
1638 { 12000000, 312000000, 312, 12, 1, 12},
1639 { 13000000, 312000000, 312, 13, 1, 12},
1640 { 19200000, 312000000, 260, 16, 1, 8},
1641 { 26000000, 312000000, 312, 26, 1, 12},
1642
1643 { 0, 0, 0, 0, 0, 0 },
1644 };
1645
1646 static struct clk tegra_pll_x = {
1647 .name = "pll_x",
1648 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG,
1649 .ops = &tegra_pllx_ops,
1650 .reg = 0xe0,
1651 .parent = &tegra_clk_m,
1652 .max_rate = 1000000000,
1653 .u.pll = {
1654 .input_min = 2000000,
1655 .input_max = 31000000,
1656 .cf_min = 1000000,
1657 .cf_max = 6000000,
1658 .vco_min = 20000000,
1659 .vco_max = 1200000000,
1660 .freq_table = tegra_pll_x_freq_table,
1661 .lock_delay = 300,
1662 },
1663 };
1664
1665 static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
1666 { 12000000, 100000000, 200, 24, 1, 0 },
1667 { 0, 0, 0, 0, 0, 0 },
1668 };
1669
1670 static struct clk tegra_pll_e = {
1671 .name = "pll_e",
1672 .flags = PLL_ALT_MISC_REG,
1673 .ops = &tegra_plle_ops,
1674 .parent = &tegra_clk_m,
1675 .reg = 0xe8,
1676 .max_rate = 100000000,
1677 .u.pll = {
1678 .input_min = 12000000,
1679 .input_max = 12000000,
1680 .freq_table = tegra_pll_e_freq_table,
1681 },
1682 };
1683
1684 static struct clk tegra_clk_d = {
1685 .name = "clk_d",
1686 .flags = PERIPH_NO_RESET,
1687 .ops = &tegra_clk_double_ops,
1688 .reg = 0x34,
1689 .reg_shift = 12,
1690 .parent = &tegra_clk_m,
1691 .max_rate = 52000000,
1692 .u.periph = {
1693 .clk_num = 90,
1694 },
1695 };
1696
1697 /* dap_mclk1, belongs to the cdev1 pingroup. */
1698 static struct clk tegra_dev1_clk = {
1699 .name = "clk_dev1",
1700 .ops = &tegra_cdev_clk_ops,
1701 .rate = 26000000,
1702 .max_rate = 26000000,
1703 .u.periph = {
1704 .clk_num = 94,
1705 },
1706 };
1707
1708 /* dap_mclk2, belongs to the cdev2 pingroup. */
1709 static struct clk tegra_dev2_clk = {
1710 .name = "clk_dev2",
1711 .ops = &tegra_cdev_clk_ops,
1712 .rate = 26000000,
1713 .max_rate = 26000000,
1714 .u.periph = {
1715 .clk_num = 93,
1716 },
1717 };
1718
1719 /* initialized before peripheral clocks */
1720 static struct clk_mux_sel mux_audio_sync_clk[8+1];
1721 static const struct audio_sources {
1722 const char *name;
1723 int value;
1724 } mux_audio_sync_clk_sources[] = {
1725 { .name = "spdif_in", .value = 0 },
1726 { .name = "i2s1", .value = 1 },
1727 { .name = "i2s2", .value = 2 },
1728 { .name = "pll_a_out0", .value = 4 },
1729 #if 0 /* FIXME: not implemented */
1730 { .name = "ac97", .value = 3 },
1731 { .name = "ext_audio_clk2", .value = 5 },
1732 { .name = "ext_audio_clk1", .value = 6 },
1733 { .name = "ext_vimclk", .value = 7 },
1734 #endif
1735 { 0, 0 }
1736 };
1737
1738 static struct clk tegra_clk_audio = {
1739 .name = "audio",
1740 .inputs = mux_audio_sync_clk,
1741 .reg = 0x38,
1742 .max_rate = 24000000,
1743 .ops = &tegra_audio_sync_clk_ops
1744 };
1745
1746 static struct clk tegra_clk_audio_2x = {
1747 .name = "audio_2x",
1748 .flags = PERIPH_NO_RESET,
1749 .max_rate = 48000000,
1750 .ops = &tegra_clk_double_ops,
1751 .reg = 0x34,
1752 .reg_shift = 8,
1753 .parent = &tegra_clk_audio,
1754 .u.periph = {
1755 .clk_num = 89,
1756 },
1757 };
1758
1759 struct clk_lookup tegra_audio_clk_lookups[] = {
1760 { .con_id = "audio", .clk = &tegra_clk_audio },
1761 { .con_id = "audio_2x", .clk = &tegra_clk_audio_2x }
1762 };
1763
1764 /* This is called after peripheral clocks are initialized, as the
1765 * audio_sync clock depends on some of the peripheral clocks.
1766 */
1767
1768 static void init_audio_sync_clock_mux(void)
1769 {
1770 int i;
1771 struct clk_mux_sel *sel = mux_audio_sync_clk;
1772 const struct audio_sources *src = mux_audio_sync_clk_sources;
1773 struct clk_lookup *lookup;
1774
1775 for (i = 0; src->name; i++, sel++, src++) {
1776 sel->input = tegra_get_clock_by_name(src->name);
1777 if (!sel->input)
1778 pr_err("%s: could not find clk %s\n", __func__,
1779 src->name);
1780 sel->value = src->value;
1781 }
1782
1783 lookup = tegra_audio_clk_lookups;
1784 for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) {
1785 clk_init(lookup->clk);
1786 clkdev_add(lookup);
1787 }
1788 }
1789
1790 static struct clk_mux_sel mux_cclk[] = {
1791 { .input = &tegra_clk_m, .value = 0},
1792 { .input = &tegra_pll_c, .value = 1},
1793 { .input = &tegra_clk_32k, .value = 2},
1794 { .input = &tegra_pll_m, .value = 3},
1795 { .input = &tegra_pll_p, .value = 4},
1796 { .input = &tegra_pll_p_out4, .value = 5},
1797 { .input = &tegra_pll_p_out3, .value = 6},
1798 { .input = &tegra_clk_d, .value = 7},
1799 { .input = &tegra_pll_x, .value = 8},
1800 { 0, 0},
1801 };
1802
1803 static struct clk_mux_sel mux_sclk[] = {
1804 { .input = &tegra_clk_m, .value = 0},
1805 { .input = &tegra_pll_c_out1, .value = 1},
1806 { .input = &tegra_pll_p_out4, .value = 2},
1807 { .input = &tegra_pll_p_out3, .value = 3},
1808 { .input = &tegra_pll_p_out2, .value = 4},
1809 { .input = &tegra_clk_d, .value = 5},
1810 { .input = &tegra_clk_32k, .value = 6},
1811 { .input = &tegra_pll_m_out1, .value = 7},
1812 { 0, 0},
1813 };
1814
1815 static struct clk tegra_clk_cclk = {
1816 .name = "cclk",
1817 .inputs = mux_cclk,
1818 .reg = 0x20,
1819 .ops = &tegra_super_ops,
1820 .max_rate = 1000000000,
1821 };
1822
1823 static struct clk tegra_clk_sclk = {
1824 .name = "sclk",
1825 .inputs = mux_sclk,
1826 .reg = 0x28,
1827 .ops = &tegra_super_ops,
1828 .max_rate = 600000000,
1829 };
1830
1831 static struct clk tegra_clk_virtual_cpu = {
1832 .name = "cpu",
1833 .parent = &tegra_clk_cclk,
1834 .ops = &tegra_cpu_ops,
1835 .max_rate = 1000000000,
1836 .u.cpu = {
1837 .main = &tegra_pll_x,
1838 .backup = &tegra_pll_p,
1839 },
1840 };
1841
1842 static struct clk tegra_clk_hclk = {
1843 .name = "hclk",
1844 .flags = DIV_BUS,
1845 .parent = &tegra_clk_sclk,
1846 .reg = 0x30,
1847 .reg_shift = 4,
1848 .ops = &tegra_bus_ops,
1849 .max_rate = 240000000,
1850 };
1851
1852 static struct clk tegra_clk_pclk = {
1853 .name = "pclk",
1854 .flags = DIV_BUS,
1855 .parent = &tegra_clk_hclk,
1856 .reg = 0x30,
1857 .reg_shift = 0,
1858 .ops = &tegra_bus_ops,
1859 .max_rate = 108000000,
1860 };
1861
1862 static struct clk tegra_clk_blink = {
1863 .name = "blink",
1864 .parent = &tegra_clk_32k,
1865 .reg = 0x40,
1866 .ops = &tegra_blink_clk_ops,
1867 .max_rate = 32768,
1868 };
1869
1870 static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
1871 { .input = &tegra_pll_m, .value = 0},
1872 { .input = &tegra_pll_c, .value = 1},
1873 { .input = &tegra_pll_p, .value = 2},
1874 { .input = &tegra_pll_a_out0, .value = 3},
1875 { 0, 0},
1876 };
1877
1878 static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
1879 { .input = &tegra_pll_m, .value = 0},
1880 { .input = &tegra_pll_c, .value = 1},
1881 { .input = &tegra_pll_p, .value = 2},
1882 { .input = &tegra_clk_m, .value = 3},
1883 { 0, 0},
1884 };
1885
1886 static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
1887 { .input = &tegra_pll_p, .value = 0},
1888 { .input = &tegra_pll_c, .value = 1},
1889 { .input = &tegra_pll_m, .value = 2},
1890 { .input = &tegra_clk_m, .value = 3},
1891 { 0, 0},
1892 };
1893
1894 static struct clk_mux_sel mux_pllaout0_audio2x_pllp_clkm[] = {
1895 {.input = &tegra_pll_a_out0, .value = 0},
1896 {.input = &tegra_clk_audio_2x, .value = 1},
1897 {.input = &tegra_pll_p, .value = 2},
1898 {.input = &tegra_clk_m, .value = 3},
1899 { 0, 0},
1900 };
1901
1902 static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
1903 {.input = &tegra_pll_p, .value = 0},
1904 {.input = &tegra_pll_d_out0, .value = 1},
1905 {.input = &tegra_pll_c, .value = 2},
1906 {.input = &tegra_clk_m, .value = 3},
1907 { 0, 0},
1908 };
1909
1910 static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = {
1911 {.input = &tegra_pll_p, .value = 0},
1912 {.input = &tegra_pll_c, .value = 1},
1913 {.input = &tegra_clk_audio, .value = 2},
1914 {.input = &tegra_clk_m, .value = 3},
1915 {.input = &tegra_clk_32k, .value = 4},
1916 { 0, 0},
1917 };
1918
1919 static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
1920 {.input = &tegra_pll_p, .value = 0},
1921 {.input = &tegra_pll_c, .value = 1},
1922 {.input = &tegra_pll_m, .value = 2},
1923 { 0, 0},
1924 };
1925
1926 static struct clk_mux_sel mux_clk_m[] = {
1927 { .input = &tegra_clk_m, .value = 0},
1928 { 0, 0},
1929 };
1930
1931 static struct clk_mux_sel mux_pllp_out3[] = {
1932 { .input = &tegra_pll_p_out3, .value = 0},
1933 { 0, 0},
1934 };
1935
1936 static struct clk_mux_sel mux_plld[] = {
1937 { .input = &tegra_pll_d, .value = 0},
1938 { 0, 0},
1939 };
1940
1941 static struct clk_mux_sel mux_clk_32k[] = {
1942 { .input = &tegra_clk_32k, .value = 0},
1943 { 0, 0},
1944 };
1945
1946 static struct clk_mux_sel mux_pclk[] = {
1947 { .input = &tegra_clk_pclk, .value = 0},
1948 { 0, 0},
1949 };
1950
1951 #define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
1952 { \
1953 .name = _name, \
1954 .lookup = { \
1955 .dev_id = _dev, \
1956 .con_id = _con, \
1957 }, \
1958 .ops = &tegra_periph_clk_ops, \
1959 .reg = _reg, \
1960 .inputs = _inputs, \
1961 .flags = _flags, \
1962 .max_rate = _max, \
1963 .u.periph = { \
1964 .clk_num = _clk_num, \
1965 }, \
1966 }
1967
1968 #define SHARED_CLK(_name, _dev, _con, _parent) \
1969 { \
1970 .name = _name, \
1971 .lookup = { \
1972 .dev_id = _dev, \
1973 .con_id = _con, \
1974 }, \
1975 .ops = &tegra_clk_shared_bus_ops, \
1976 .parent = _parent, \
1977 }
1978
1979 struct clk tegra_list_clks[] = {
1980 PERIPH_CLK("apbdma", "tegra-dma", NULL, 34, 0, 108000000, mux_pclk, 0),
1981 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET),
1982 PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
1983 PERIPH_CLK("i2s1", "i2s.0", NULL, 11, 0x100, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
1984 PERIPH_CLK("i2s2", "i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
1985 /* FIXME: spdif has 2 clocks but 1 enable */
1986 PERIPH_CLK("spdif_out", "spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
1987 PERIPH_CLK("spdif_in", "spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71),
1988 PERIPH_CLK("pwm", "pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71),
1989 PERIPH_CLK("spi", "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1990 PERIPH_CLK("xio", "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1991 PERIPH_CLK("twc", "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1992 PERIPH_CLK("sbc1", "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1993 PERIPH_CLK("sbc2", "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1994 PERIPH_CLK("sbc3", "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1995 PERIPH_CLK("sbc4", "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1996 PERIPH_CLK("ide", "ide", NULL, 25, 0x144, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
1997 PERIPH_CLK("ndflash", "tegra_nand", NULL, 13, 0x160, 164000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
1998 /* FIXME: vfir shares an enable with uartb */
1999 PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2000 PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2001 PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2002 PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2003 PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2004 PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, 250000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage and process_id */
2005 PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* max rate ??? */
2006 /* FIXME: what is la? */
2007 PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2008 PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2009 PERIPH_CLK("nor", "nor", NULL, 42, 0x1d0, 92000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
2010 PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2011 PERIPH_CLK("i2c1", "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
2012 PERIPH_CLK("i2c2", "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
2013 PERIPH_CLK("i2c3", "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
2014 PERIPH_CLK("dvc", "tegra-i2c.3", NULL, 47, 0x128, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
2015 PERIPH_CLK("i2c1_i2c", "tegra-i2c.0", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2016 PERIPH_CLK("i2c2_i2c", "tegra-i2c.1", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2017 PERIPH_CLK("i2c3_i2c", "tegra-i2c.2", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2018 PERIPH_CLK("dvc_i2c", "tegra-i2c.3", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2019 PERIPH_CLK("uarta", "uart.0", NULL, 6, 0x178, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2020 PERIPH_CLK("uartb", "uart.1", NULL, 7, 0x17c, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2021 PERIPH_CLK("uartc", "uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2022 PERIPH_CLK("uartd", "uart.3", NULL, 65, 0x1c0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2023 PERIPH_CLK("uarte", "uart.4", NULL, 66, 0x1c4, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2024 PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */
2025 PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2026 /* FIXME: vi and vi_sensor share an enable */
2027 PERIPH_CLK("vi", "tegra_camera", "vi", 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2028 PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET), /* scales with voltage and process_id */
2029 PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2030 PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, 250000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2031 PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 166000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2032 /* FIXME: cve and tvo share an enable */
2033 PERIPH_CLK("cve", "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2034 PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2035 PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2036 PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2037 PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* scales with voltage and process_id */
2038 PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* scales with voltage and process_id */
2039 PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2040 PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2041 PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2042 PERIPH_CLK("emc", "emc", NULL, 57, 0x19c, 800000000, mux_pllm_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_EMC_ENB),
2043 PERIPH_CLK("dsi", "dsi", NULL, 48, 0, 500000000, mux_plld, 0), /* scales with voltage */
2044 PERIPH_CLK("csi", "tegra_camera", "csi", 52, 0, 72000000, mux_pllp_out3, 0),
2045 PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */
2046 PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
2047 PERIPH_CLK("pex", NULL, "pex", 70, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
2048 PERIPH_CLK("afi", NULL, "afi", 72, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
2049 PERIPH_CLK("pcie_xclk", NULL, "pcie_xclk", 74, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
2050 };
2051
2052 #define CLK_DUPLICATE(_name, _dev, _con) \
2053 { \
2054 .name = _name, \
2055 .lookup = { \
2056 .dev_id = _dev, \
2057 .con_id = _con, \
2058 }, \
2059 }
2060
2061 /* Some clocks may be used by different drivers depending on the board
2062 * configuration. List those here to register them twice in the clock lookup
2063 * table under two names.
2064 */
2065 struct clk_duplicate tegra_clk_duplicates[] = {
2066 CLK_DUPLICATE("uarta", "tegra_uart.0", NULL),
2067 CLK_DUPLICATE("uartb", "tegra_uart.1", NULL),
2068 CLK_DUPLICATE("uartc", "tegra_uart.2", NULL),
2069 CLK_DUPLICATE("uartd", "tegra_uart.3", NULL),
2070 CLK_DUPLICATE("uarte", "tegra_uart.4", NULL),
2071 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
2072 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
2073 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
2074 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
2075 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
2076 CLK_DUPLICATE("pwm", "tegra_pwm.0", NULL),
2077 CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL),
2078 CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL),
2079 CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL),
2080 };
2081
2082 #define CLK(dev, con, ck) \
2083 { \
2084 .dev_id = dev, \
2085 .con_id = con, \
2086 .clk = ck, \
2087 }
2088
2089 struct clk *tegra_ptr_clks[] = {
2090 &tegra_clk_32k,
2091 &tegra_pll_s,
2092 &tegra_clk_m,
2093 &tegra_pll_m,
2094 &tegra_pll_m_out1,
2095 &tegra_pll_c,
2096 &tegra_pll_c_out1,
2097 &tegra_pll_p,
2098 &tegra_pll_p_out1,
2099 &tegra_pll_p_out2,
2100 &tegra_pll_p_out3,
2101 &tegra_pll_p_out4,
2102 &tegra_pll_a,
2103 &tegra_pll_a_out0,
2104 &tegra_pll_d,
2105 &tegra_pll_d_out0,
2106 &tegra_pll_u,
2107 &tegra_pll_x,
2108 &tegra_pll_e,
2109 &tegra_clk_cclk,
2110 &tegra_clk_sclk,
2111 &tegra_clk_hclk,
2112 &tegra_clk_pclk,
2113 &tegra_clk_d,
2114 &tegra_dev1_clk,
2115 &tegra_dev2_clk,
2116 &tegra_clk_virtual_cpu,
2117 &tegra_clk_blink,
2118 };
2119
2120 static void tegra2_init_one_clock(struct clk *c)
2121 {
2122 clk_init(c);
2123 INIT_LIST_HEAD(&c->shared_bus_list);
2124 if (!c->lookup.dev_id && !c->lookup.con_id)
2125 c->lookup.con_id = c->name;
2126 c->lookup.clk = c;
2127 clkdev_add(&c->lookup);
2128 }
2129
2130 void __init tegra2_init_clocks(void)
2131 {
2132 int i;
2133 struct clk *c;
2134
2135 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
2136 tegra2_init_one_clock(tegra_ptr_clks[i]);
2137
2138 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
2139 tegra2_init_one_clock(&tegra_list_clks[i]);
2140
2141 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
2142 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
2143 if (!c) {
2144 pr_err("%s: Unknown duplicate clock %s\n", __func__,
2145 tegra_clk_duplicates[i].name);
2146 continue;
2147 }
2148
2149 tegra_clk_duplicates[i].lookup.clk = c;
2150 clkdev_add(&tegra_clk_duplicates[i].lookup);
2151 }
2152
2153 init_audio_sync_clock_mux();
2154 }
2155
2156 #ifdef CONFIG_PM
2157 static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM +
2158 PERIPH_CLK_SOURCE_NUM + 19];
2159
2160 void tegra_clk_suspend(void)
2161 {
2162 unsigned long off, i;
2163 u32 *ctx = clk_rst_suspend;
2164
2165 *ctx++ = clk_readl(OSC_CTRL) & OSC_CTRL_MASK;
2166 *ctx++ = clk_readl(tegra_pll_p.reg + PLL_BASE);
2167 *ctx++ = clk_readl(tegra_pll_p.reg + PLL_MISC(&tegra_pll_p));
2168 *ctx++ = clk_readl(tegra_pll_c.reg + PLL_BASE);
2169 *ctx++ = clk_readl(tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
2170 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_BASE);
2171 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
2172
2173 *ctx++ = clk_readl(tegra_pll_m_out1.reg);
2174 *ctx++ = clk_readl(tegra_pll_p_out1.reg);
2175 *ctx++ = clk_readl(tegra_pll_p_out3.reg);
2176 *ctx++ = clk_readl(tegra_pll_a_out0.reg);
2177 *ctx++ = clk_readl(tegra_pll_c_out1.reg);
2178
2179 *ctx++ = clk_readl(tegra_clk_cclk.reg);
2180 *ctx++ = clk_readl(tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
2181
2182 *ctx++ = clk_readl(tegra_clk_sclk.reg);
2183 *ctx++ = clk_readl(tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
2184 *ctx++ = clk_readl(tegra_clk_pclk.reg);
2185
2186 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
2187 off += 4) {
2188 if (off == PERIPH_CLK_SOURCE_EMC)
2189 continue;
2190 *ctx++ = clk_readl(off);
2191 }
2192
2193 off = RST_DEVICES;
2194 for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
2195 *ctx++ = clk_readl(off);
2196
2197 off = CLK_OUT_ENB;
2198 for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
2199 *ctx++ = clk_readl(off);
2200
2201 *ctx++ = clk_readl(MISC_CLK_ENB);
2202 *ctx++ = clk_readl(CLK_MASK_ARM);
2203 }
2204
2205 void tegra_clk_resume(void)
2206 {
2207 unsigned long off, i;
2208 const u32 *ctx = clk_rst_suspend;
2209 u32 val;
2210
2211 val = clk_readl(OSC_CTRL) & ~OSC_CTRL_MASK;
2212 val |= *ctx++;
2213 clk_writel(val, OSC_CTRL);
2214
2215 clk_writel(*ctx++, tegra_pll_p.reg + PLL_BASE);
2216 clk_writel(*ctx++, tegra_pll_p.reg + PLL_MISC(&tegra_pll_p));
2217 clk_writel(*ctx++, tegra_pll_c.reg + PLL_BASE);
2218 clk_writel(*ctx++, tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
2219 clk_writel(*ctx++, tegra_pll_a.reg + PLL_BASE);
2220 clk_writel(*ctx++, tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
2221 udelay(300);
2222
2223 clk_writel(*ctx++, tegra_pll_m_out1.reg);
2224 clk_writel(*ctx++, tegra_pll_p_out1.reg);
2225 clk_writel(*ctx++, tegra_pll_p_out3.reg);
2226 clk_writel(*ctx++, tegra_pll_a_out0.reg);
2227 clk_writel(*ctx++, tegra_pll_c_out1.reg);
2228
2229 clk_writel(*ctx++, tegra_clk_cclk.reg);
2230 clk_writel(*ctx++, tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
2231
2232 clk_writel(*ctx++, tegra_clk_sclk.reg);
2233 clk_writel(*ctx++, tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
2234 clk_writel(*ctx++, tegra_clk_pclk.reg);
2235
2236 /* enable all clocks before configuring clock sources */
2237 clk_writel(0xbffffff9ul, CLK_OUT_ENB);
2238 clk_writel(0xfefffff7ul, CLK_OUT_ENB + 4);
2239 clk_writel(0x77f01bfful, CLK_OUT_ENB + 8);
2240 wmb();
2241
2242 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
2243 off += 4) {
2244 if (off == PERIPH_CLK_SOURCE_EMC)
2245 continue;
2246 clk_writel(*ctx++, off);
2247 }
2248 wmb();
2249
2250 off = RST_DEVICES;
2251 for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
2252 clk_writel(*ctx++, off);
2253 wmb();
2254
2255 off = CLK_OUT_ENB;
2256 for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
2257 clk_writel(*ctx++, off);
2258 wmb();
2259
2260 clk_writel(*ctx++, MISC_CLK_ENB);
2261 clk_writel(*ctx++, CLK_MASK_ARM);
2262 }
2263 #endif
Linux kernel - Deliverables
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