2 * arch/arm/mach-tegra/tegra30_clocks.c
4 * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/list.h>
24 #include <linux/spinlock.h>
25 #include <linux/delay.h>
26 #include <linux/err.h>
28 #include <linux/clk.h>
29 #include <linux/cpufreq.h>
30 #include <linux/syscore_ops.h>
32 #include <asm/clkdev.h>
34 #include <mach/iomap.h>
39 #define USE_PLL_LOCK_BITS 0
41 #define RST_DEVICES_L 0x004
42 #define RST_DEVICES_H 0x008
43 #define RST_DEVICES_U 0x00C
44 #define RST_DEVICES_V 0x358
45 #define RST_DEVICES_W 0x35C
46 #define RST_DEVICES_SET_L 0x300
47 #define RST_DEVICES_CLR_L 0x304
48 #define RST_DEVICES_SET_V 0x430
49 #define RST_DEVICES_CLR_V 0x434
50 #define RST_DEVICES_NUM 5
52 #define CLK_OUT_ENB_L 0x010
53 #define CLK_OUT_ENB_H 0x014
54 #define CLK_OUT_ENB_U 0x018
55 #define CLK_OUT_ENB_V 0x360
56 #define CLK_OUT_ENB_W 0x364
57 #define CLK_OUT_ENB_SET_L 0x320
58 #define CLK_OUT_ENB_CLR_L 0x324
59 #define CLK_OUT_ENB_SET_V 0x440
60 #define CLK_OUT_ENB_CLR_V 0x444
61 #define CLK_OUT_ENB_NUM 5
63 #define RST_DEVICES_V_SWR_CPULP_RST_DIS (0x1 << 1)
64 #define CLK_OUT_ENB_V_CLK_ENB_CPULP_EN (0x1 << 1)
66 #define PERIPH_CLK_TO_BIT(c) (1 << (c->u.periph.clk_num % 32))
67 #define PERIPH_CLK_TO_RST_REG(c) \
68 periph_clk_to_reg((c), RST_DEVICES_L, RST_DEVICES_V, 4)
69 #define PERIPH_CLK_TO_RST_SET_REG(c) \
70 periph_clk_to_reg((c), RST_DEVICES_SET_L, RST_DEVICES_SET_V, 8)
71 #define PERIPH_CLK_TO_RST_CLR_REG(c) \
72 periph_clk_to_reg((c), RST_DEVICES_CLR_L, RST_DEVICES_CLR_V, 8)
74 #define PERIPH_CLK_TO_ENB_REG(c) \
75 periph_clk_to_reg((c), CLK_OUT_ENB_L, CLK_OUT_ENB_V, 4)
76 #define PERIPH_CLK_TO_ENB_SET_REG(c) \
77 periph_clk_to_reg((c), CLK_OUT_ENB_SET_L, CLK_OUT_ENB_SET_V, 8)
78 #define PERIPH_CLK_TO_ENB_CLR_REG(c) \
79 periph_clk_to_reg((c), CLK_OUT_ENB_CLR_L, CLK_OUT_ENB_CLR_V, 8)
81 #define CLK_MASK_ARM 0x44
82 #define MISC_CLK_ENB 0x48
85 #define OSC_CTRL_OSC_FREQ_MASK (0xF<<28)
86 #define OSC_CTRL_OSC_FREQ_13MHZ (0x0<<28)
87 #define OSC_CTRL_OSC_FREQ_19_2MHZ (0x4<<28)
88 #define OSC_CTRL_OSC_FREQ_12MHZ (0x8<<28)
89 #define OSC_CTRL_OSC_FREQ_26MHZ (0xC<<28)
90 #define OSC_CTRL_OSC_FREQ_16_8MHZ (0x1<<28)
91 #define OSC_CTRL_OSC_FREQ_38_4MHZ (0x5<<28)
92 #define OSC_CTRL_OSC_FREQ_48MHZ (0x9<<28)
93 #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
95 #define OSC_CTRL_PLL_REF_DIV_MASK (3<<26)
96 #define OSC_CTRL_PLL_REF_DIV_1 (0<<26)
97 #define OSC_CTRL_PLL_REF_DIV_2 (1<<26)
98 #define OSC_CTRL_PLL_REF_DIV_4 (2<<26)
100 #define OSC_FREQ_DET 0x58
101 #define OSC_FREQ_DET_TRIG (1<<31)
103 #define OSC_FREQ_DET_STATUS 0x5C
104 #define OSC_FREQ_DET_BUSY (1<<31)
105 #define OSC_FREQ_DET_CNT_MASK 0xFFFF
107 #define PERIPH_CLK_SOURCE_I2S1 0x100
108 #define PERIPH_CLK_SOURCE_EMC 0x19c
109 #define PERIPH_CLK_SOURCE_OSC 0x1fc
110 #define PERIPH_CLK_SOURCE_NUM1 \
111 ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
113 #define PERIPH_CLK_SOURCE_G3D2 0x3b0
114 #define PERIPH_CLK_SOURCE_SE 0x42c
115 #define PERIPH_CLK_SOURCE_NUM2 \
116 ((PERIPH_CLK_SOURCE_SE - PERIPH_CLK_SOURCE_G3D2) / 4 + 1)
118 #define AUDIO_DLY_CLK 0x49c
119 #define AUDIO_SYNC_CLK_SPDIF 0x4b4
120 #define PERIPH_CLK_SOURCE_NUM3 \
121 ((AUDIO_SYNC_CLK_SPDIF - AUDIO_DLY_CLK) / 4 + 1)
123 #define PERIPH_CLK_SOURCE_NUM (PERIPH_CLK_SOURCE_NUM1 + \
124 PERIPH_CLK_SOURCE_NUM2 + \
125 PERIPH_CLK_SOURCE_NUM3)
127 #define CPU_SOFTRST_CTRL 0x380
129 #define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF
130 #define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
131 #define PERIPH_CLK_SOURCE_DIV_SHIFT 0
132 #define PERIPH_CLK_SOURCE_DIVIDLE_SHIFT 8
133 #define PERIPH_CLK_SOURCE_DIVIDLE_VAL 50
134 #define PERIPH_CLK_UART_DIV_ENB (1<<24)
135 #define PERIPH_CLK_VI_SEL_EX_SHIFT 24
136 #define PERIPH_CLK_VI_SEL_EX_MASK (0x3<<PERIPH_CLK_VI_SEL_EX_SHIFT)
137 #define PERIPH_CLK_NAND_DIV_EX_ENB (1<<8)
138 #define PERIPH_CLK_DTV_POLARITY_INV (1<<25)
140 #define AUDIO_SYNC_SOURCE_MASK 0x0F
141 #define AUDIO_SYNC_DISABLE_BIT 0x10
142 #define AUDIO_SYNC_TAP_NIBBLE_SHIFT(c) ((c->reg_shift - 24) * 4)
145 #define PLL_BASE_BYPASS (1<<31)
146 #define PLL_BASE_ENABLE (1<<30)
147 #define PLL_BASE_REF_ENABLE (1<<29)
148 #define PLL_BASE_OVERRIDE (1<<28)
149 #define PLL_BASE_LOCK (1<<27)
150 #define PLL_BASE_DIVP_MASK (0x7<<20)
151 #define PLL_BASE_DIVP_SHIFT 20
152 #define PLL_BASE_DIVN_MASK (0x3FF<<8)
153 #define PLL_BASE_DIVN_SHIFT 8
154 #define PLL_BASE_DIVM_MASK (0x1F)
155 #define PLL_BASE_DIVM_SHIFT 0
157 #define PLL_OUT_RATIO_MASK (0xFF<<8)
158 #define PLL_OUT_RATIO_SHIFT 8
159 #define PLL_OUT_OVERRIDE (1<<2)
160 #define PLL_OUT_CLKEN (1<<1)
161 #define PLL_OUT_RESET_DISABLE (1<<0)
163 #define PLL_MISC(c) \
164 (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
165 #define PLL_MISC_LOCK_ENABLE(c) \
166 (((c)->flags & (PLLU | PLLD)) ? (1<<22) : (1<<18))
168 #define PLL_MISC_DCCON_SHIFT 20
169 #define PLL_MISC_CPCON_SHIFT 8
170 #define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)
171 #define PLL_MISC_LFCON_SHIFT 4
172 #define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)
173 #define PLL_MISC_VCOCON_SHIFT 0
174 #define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)
175 #define PLLD_MISC_CLKENABLE (1<<30)
177 #define PLLU_BASE_POST_DIV (1<<20)
179 #define PLLD_BASE_DSIB_MUX_SHIFT 25
180 #define PLLD_BASE_DSIB_MUX_MASK (1<<PLLD_BASE_DSIB_MUX_SHIFT)
181 #define PLLD_BASE_CSI_CLKENABLE (1<<26)
182 #define PLLD_MISC_DSI_CLKENABLE (1<<30)
183 #define PLLD_MISC_DIV_RST (1<<23)
184 #define PLLD_MISC_DCCON_SHIFT 12
186 #define PLLDU_LFCON_SET_DIVN 600
188 /* FIXME: OUT_OF_TABLE_CPCON per pll */
189 #define OUT_OF_TABLE_CPCON 0x8
191 #define SUPER_CLK_MUX 0x00
192 #define SUPER_STATE_SHIFT 28
193 #define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)
194 #define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)
195 #define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)
196 #define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)
197 #define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)
198 #define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)
199 #define SUPER_LP_DIV2_BYPASS (0x1 << 16)
200 #define SUPER_SOURCE_MASK 0xF
201 #define SUPER_FIQ_SOURCE_SHIFT 12
202 #define SUPER_IRQ_SOURCE_SHIFT 8
203 #define SUPER_RUN_SOURCE_SHIFT 4
204 #define SUPER_IDLE_SOURCE_SHIFT 0
206 #define SUPER_CLK_DIVIDER 0x04
207 #define SUPER_CLOCK_DIV_U71_SHIFT 16
208 #define SUPER_CLOCK_DIV_U71_MASK (0xff << SUPER_CLOCK_DIV_U71_SHIFT)
209 /* guarantees safe cpu backup */
210 #define SUPER_CLOCK_DIV_U71_MIN 0x2
212 #define BUS_CLK_DISABLE (1<<3)
213 #define BUS_CLK_DIV_MASK 0x3
216 #define PMC_CTRL_BLINK_ENB (1 << 7)
218 #define PMC_DPD_PADS_ORIDE 0x1c
219 #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20)
221 #define PMC_BLINK_TIMER_DATA_ON_SHIFT 0
222 #define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff
223 #define PMC_BLINK_TIMER_ENB (1 << 15)
224 #define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16
225 #define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff
227 #define PMC_PLLP_WB0_OVERRIDE 0xf8
228 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE (1 << 12)
230 #define UTMIP_PLL_CFG2 0x488
231 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
232 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
233 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN (1 << 0)
234 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN (1 << 2)
235 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN (1 << 4)
237 #define UTMIP_PLL_CFG1 0x484
238 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
239 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
240 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN (1 << 14)
241 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN (1 << 12)
242 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN (1 << 16)
244 #define PLLE_BASE_CML_ENABLE (1<<31)
245 #define PLLE_BASE_ENABLE (1<<30)
246 #define PLLE_BASE_DIVCML_SHIFT 24
247 #define PLLE_BASE_DIVCML_MASK (0xf<<PLLE_BASE_DIVCML_SHIFT)
248 #define PLLE_BASE_DIVP_SHIFT 16
249 #define PLLE_BASE_DIVP_MASK (0x3f<<PLLE_BASE_DIVP_SHIFT)
250 #define PLLE_BASE_DIVN_SHIFT 8
251 #define PLLE_BASE_DIVN_MASK (0xFF<<PLLE_BASE_DIVN_SHIFT)
252 #define PLLE_BASE_DIVM_SHIFT 0
253 #define PLLE_BASE_DIVM_MASK (0xFF<<PLLE_BASE_DIVM_SHIFT)
254 #define PLLE_BASE_DIV_MASK \
255 (PLLE_BASE_DIVCML_MASK | PLLE_BASE_DIVP_MASK | \
256 PLLE_BASE_DIVN_MASK | PLLE_BASE_DIVM_MASK)
257 #define PLLE_BASE_DIV(m, n, p, cml) \
258 (((cml)<<PLLE_BASE_DIVCML_SHIFT) | ((p)<<PLLE_BASE_DIVP_SHIFT) | \
259 ((n)<<PLLE_BASE_DIVN_SHIFT) | ((m)<<PLLE_BASE_DIVM_SHIFT))
261 #define PLLE_MISC_SETUP_BASE_SHIFT 16
262 #define PLLE_MISC_SETUP_BASE_MASK (0xFFFF<<PLLE_MISC_SETUP_BASE_SHIFT)
263 #define PLLE_MISC_READY (1<<15)
264 #define PLLE_MISC_LOCK (1<<11)
265 #define PLLE_MISC_LOCK_ENABLE (1<<9)
266 #define PLLE_MISC_SETUP_EX_SHIFT 2
267 #define PLLE_MISC_SETUP_EX_MASK (0x3<<PLLE_MISC_SETUP_EX_SHIFT)
268 #define PLLE_MISC_SETUP_MASK \
269 (PLLE_MISC_SETUP_BASE_MASK | PLLE_MISC_SETUP_EX_MASK)
270 #define PLLE_MISC_SETUP_VALUE \
271 ((0x7<<PLLE_MISC_SETUP_BASE_SHIFT) | (0x0<<PLLE_MISC_SETUP_EX_SHIFT))
273 #define PLLE_SS_CTRL 0x68
274 #define PLLE_SS_INCINTRV_SHIFT 24
275 #define PLLE_SS_INCINTRV_MASK (0x3f<<PLLE_SS_INCINTRV_SHIFT)
276 #define PLLE_SS_INC_SHIFT 16
277 #define PLLE_SS_INC_MASK (0xff<<PLLE_SS_INC_SHIFT)
278 #define PLLE_SS_MAX_SHIFT 0
279 #define PLLE_SS_MAX_MASK (0x1ff<<PLLE_SS_MAX_SHIFT)
280 #define PLLE_SS_COEFFICIENTS_MASK \
281 (PLLE_SS_INCINTRV_MASK | PLLE_SS_INC_MASK | PLLE_SS_MAX_MASK)
282 #define PLLE_SS_COEFFICIENTS_12MHZ \
283 ((0x18<<PLLE_SS_INCINTRV_SHIFT) | (0x1<<PLLE_SS_INC_SHIFT) | \
284 (0x24<<PLLE_SS_MAX_SHIFT))
285 #define PLLE_SS_DISABLE ((1<<12) | (1<<11) | (1<<10))
287 #define PLLE_AUX 0x48c
288 #define PLLE_AUX_PLLP_SEL (1<<2)
289 #define PLLE_AUX_CML_SATA_ENABLE (1<<1)
290 #define PLLE_AUX_CML_PCIE_ENABLE (1<<0)
292 #define PMC_SATA_PWRGT 0x1ac
293 #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE (1<<5)
294 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1<<4)
296 #define ROUND_DIVIDER_UP 0
297 #define ROUND_DIVIDER_DOWN 1
299 /* FIXME: recommended safety delay after lock is detected */
300 #define PLL_POST_LOCK_DELAY 100
303 * Structure defining the fields for USB UTMI clocks Parameters.
305 struct utmi_clk_param
{
306 /* Oscillator Frequency in KHz */
308 /* UTMIP PLL Enable Delay Count */
309 u8 enable_delay_count
;
310 /* UTMIP PLL Stable count */
312 /* UTMIP PLL Active delay count */
313 u8 active_delay_count
;
314 /* UTMIP PLL Xtal frequency count */
318 static const struct utmi_clk_param utmi_parameters
[] = {
320 .osc_frequency
= 13000000,
321 .enable_delay_count
= 0x02,
322 .stable_count
= 0x33,
323 .active_delay_count
= 0x05,
324 .xtal_freq_count
= 0x7F
327 .osc_frequency
= 19200000,
328 .enable_delay_count
= 0x03,
329 .stable_count
= 0x4B,
330 .active_delay_count
= 0x06,
331 .xtal_freq_count
= 0xBB},
333 .osc_frequency
= 12000000,
334 .enable_delay_count
= 0x02,
335 .stable_count
= 0x2F,
336 .active_delay_count
= 0x04,
337 .xtal_freq_count
= 0x76
340 .osc_frequency
= 26000000,
341 .enable_delay_count
= 0x04,
342 .stable_count
= 0x66,
343 .active_delay_count
= 0x09,
344 .xtal_freq_count
= 0xFE
347 .osc_frequency
= 16800000,
348 .enable_delay_count
= 0x03,
349 .stable_count
= 0x41,
350 .active_delay_count
= 0x0A,
351 .xtal_freq_count
= 0xA4
355 static void __iomem
*reg_clk_base
= IO_ADDRESS(TEGRA_CLK_RESET_BASE
);
356 static void __iomem
*reg_pmc_base
= IO_ADDRESS(TEGRA_PMC_BASE
);
357 static void __iomem
*misc_gp_hidrev_base
= IO_ADDRESS(TEGRA_APB_MISC_BASE
);
359 #define MISC_GP_HIDREV 0x804
362 * Some peripheral clocks share an enable bit, so refcount the enable bits
363 * in registers CLK_ENABLE_L, ... CLK_ENABLE_W
365 static int tegra_periph_clk_enable_refcount
[CLK_OUT_ENB_NUM
* 32];
367 #define clk_writel(value, reg) \
368 __raw_writel(value, (u32)reg_clk_base + (reg))
369 #define clk_readl(reg) \
370 __raw_readl((u32)reg_clk_base + (reg))
371 #define pmc_writel(value, reg) \
372 __raw_writel(value, (u32)reg_pmc_base + (reg))
373 #define pmc_readl(reg) \
374 __raw_readl((u32)reg_pmc_base + (reg))
375 #define chipid_readl() \
376 __raw_readl((u32)misc_gp_hidrev_base + MISC_GP_HIDREV)
378 #define clk_writel_delay(value, reg) \
380 __raw_writel((value), (u32)reg_clk_base + (reg)); \
384 static inline int clk_set_div(struct clk_tegra
*c
, u32 n
)
386 struct clk
*clk
= c
->hw
.clk
;
388 return clk_set_rate(clk
,
389 (__clk_get_rate(__clk_get_parent(clk
)) + n
- 1) / n
);
392 static inline u32
periph_clk_to_reg(
393 struct clk_tegra
*c
, u32 reg_L
, u32 reg_V
, int offs
)
395 u32 reg
= c
->u
.periph
.clk_num
/ 32;
396 BUG_ON(reg
>= RST_DEVICES_NUM
);
398 reg
= reg_L
+ (reg
* offs
);
400 reg
= reg_V
+ ((reg
- 3) * offs
);
404 static unsigned long clk_measure_input_freq(void)
406 u32 clock_autodetect
;
407 clk_writel(OSC_FREQ_DET_TRIG
| 1, OSC_FREQ_DET
);
408 do {} while (clk_readl(OSC_FREQ_DET_STATUS
) & OSC_FREQ_DET_BUSY
);
409 clock_autodetect
= clk_readl(OSC_FREQ_DET_STATUS
);
410 if (clock_autodetect
>= 732 - 3 && clock_autodetect
<= 732 + 3) {
412 } else if (clock_autodetect
>= 794 - 3 && clock_autodetect
<= 794 + 3) {
414 } else if (clock_autodetect
>= 1172 - 3 && clock_autodetect
<= 1172 + 3) {
416 } else if (clock_autodetect
>= 1587 - 3 && clock_autodetect
<= 1587 + 3) {
418 } else if (clock_autodetect
>= 1025 - 3 && clock_autodetect
<= 1025 + 3) {
420 } else if (clock_autodetect
>= 2344 - 3 && clock_autodetect
<= 2344 + 3) {
422 } else if (clock_autodetect
>= 2928 - 3 && clock_autodetect
<= 2928 + 3) {
425 pr_err("%s: Unexpected clock autodetect value %d", __func__
,
432 static int clk_div71_get_divider(unsigned long parent_rate
, unsigned long rate
,
433 u32 flags
, u32 round_mode
)
435 s64 divider_u71
= parent_rate
;
439 if (!(flags
& DIV_U71_INT
))
441 if (round_mode
== ROUND_DIVIDER_UP
)
442 divider_u71
+= rate
- 1;
443 do_div(divider_u71
, rate
);
444 if (flags
& DIV_U71_INT
)
447 if (divider_u71
- 2 < 0)
450 if (divider_u71
- 2 > 255)
453 return divider_u71
- 2;
456 static int clk_div16_get_divider(unsigned long parent_rate
, unsigned long rate
)
460 divider_u16
= parent_rate
;
463 divider_u16
+= rate
- 1;
464 do_div(divider_u16
, rate
);
466 if (divider_u16
- 1 < 0)
469 if (divider_u16
- 1 > 0xFFFF)
472 return divider_u16
- 1;
475 static unsigned long tegra30_clk_fixed_recalc_rate(struct clk_hw
*hw
,
476 unsigned long parent_rate
)
478 return to_clk_tegra(hw
)->fixed_rate
;
481 struct clk_ops tegra_clk_32k_ops
= {
482 .recalc_rate
= tegra30_clk_fixed_recalc_rate
,
485 /* clk_m functions */
486 static unsigned long tegra30_clk_m_recalc_rate(struct clk_hw
*hw
,
487 unsigned long parent_rate
)
489 if (!to_clk_tegra(hw
)->fixed_rate
)
490 to_clk_tegra(hw
)->fixed_rate
= clk_measure_input_freq();
491 return to_clk_tegra(hw
)->fixed_rate
;
494 static void tegra30_clk_m_init(struct clk_hw
*hw
)
496 u32 osc_ctrl
= clk_readl(OSC_CTRL
);
497 u32 auto_clock_control
= osc_ctrl
& ~OSC_CTRL_OSC_FREQ_MASK
;
498 u32 pll_ref_div
= osc_ctrl
& OSC_CTRL_PLL_REF_DIV_MASK
;
500 switch (to_clk_tegra(hw
)->fixed_rate
) {
502 auto_clock_control
|= OSC_CTRL_OSC_FREQ_12MHZ
;
503 BUG_ON(pll_ref_div
!= OSC_CTRL_PLL_REF_DIV_1
);
506 auto_clock_control
|= OSC_CTRL_OSC_FREQ_13MHZ
;
507 BUG_ON(pll_ref_div
!= OSC_CTRL_PLL_REF_DIV_1
);
510 auto_clock_control
|= OSC_CTRL_OSC_FREQ_19_2MHZ
;
511 BUG_ON(pll_ref_div
!= OSC_CTRL_PLL_REF_DIV_1
);
514 auto_clock_control
|= OSC_CTRL_OSC_FREQ_26MHZ
;
515 BUG_ON(pll_ref_div
!= OSC_CTRL_PLL_REF_DIV_1
);
518 auto_clock_control
|= OSC_CTRL_OSC_FREQ_16_8MHZ
;
519 BUG_ON(pll_ref_div
!= OSC_CTRL_PLL_REF_DIV_1
);
522 auto_clock_control
|= OSC_CTRL_OSC_FREQ_38_4MHZ
;
523 BUG_ON(pll_ref_div
!= OSC_CTRL_PLL_REF_DIV_2
);
526 auto_clock_control
|= OSC_CTRL_OSC_FREQ_48MHZ
;
527 BUG_ON(pll_ref_div
!= OSC_CTRL_PLL_REF_DIV_4
);
530 pr_err("%s: Unexpected clock rate %ld", __func__
,
531 to_clk_tegra(hw
)->fixed_rate
);
534 clk_writel(auto_clock_control
, OSC_CTRL
);
537 struct clk_ops tegra30_clk_m_ops
= {
538 .init
= tegra30_clk_m_init
,
539 .recalc_rate
= tegra30_clk_m_recalc_rate
,
542 static unsigned long tegra30_clk_m_div_recalc_rate(struct clk_hw
*hw
,
543 unsigned long parent_rate
)
545 struct clk_tegra
*c
= to_clk_tegra(hw
);
546 u64 rate
= parent_rate
;
548 if (c
->mul
!= 0 && c
->div
!= 0) {
550 rate
+= c
->div
- 1; /* round up */
551 do_div(rate
, c
->div
);
557 struct clk_ops tegra_clk_m_div_ops
= {
558 .recalc_rate
= tegra30_clk_m_div_recalc_rate
,
561 /* PLL reference divider functions */
562 static unsigned long tegra30_pll_ref_recalc_rate(struct clk_hw
*hw
,
563 unsigned long parent_rate
)
565 struct clk_tegra
*c
= to_clk_tegra(hw
);
566 unsigned long rate
= parent_rate
;
567 u32 pll_ref_div
= clk_readl(OSC_CTRL
) & OSC_CTRL_PLL_REF_DIV_MASK
;
569 switch (pll_ref_div
) {
570 case OSC_CTRL_PLL_REF_DIV_1
:
573 case OSC_CTRL_PLL_REF_DIV_2
:
576 case OSC_CTRL_PLL_REF_DIV_4
:
580 pr_err("%s: Invalid pll ref divider %d", __func__
, pll_ref_div
);
585 if (c
->mul
!= 0 && c
->div
!= 0) {
587 rate
+= c
->div
- 1; /* round up */
588 do_div(rate
, c
->div
);
594 struct clk_ops tegra_pll_ref_ops
= {
595 .recalc_rate
= tegra30_pll_ref_recalc_rate
,
598 /* super clock functions */
599 /* "super clocks" on tegra30 have two-stage muxes, fractional 7.1 divider and
600 * clock skipping super divider. We will ignore the clock skipping divider,
601 * since we can't lower the voltage when using the clock skip, but we can if
602 * we lower the PLL frequency. We will use 7.1 divider for CPU super-clock
603 * only when its parent is a fixed rate PLL, since we can't change PLL rate
606 static void tegra30_super_clk_init(struct clk_hw
*hw
)
608 struct clk_tegra
*c
= to_clk_tegra(hw
);
609 struct clk_tegra
*p
=
610 to_clk_tegra(__clk_get_hw(__clk_get_parent(hw
->clk
)));
613 if (c
->flags
& DIV_U71
) {
614 /* Init safe 7.1 divider value (does not affect PLLX path) */
615 clk_writel(SUPER_CLOCK_DIV_U71_MIN
<< SUPER_CLOCK_DIV_U71_SHIFT
,
616 c
->reg
+ SUPER_CLK_DIVIDER
);
619 if (!(p
->flags
& PLLX
))
620 c
->div
+= SUPER_CLOCK_DIV_U71_MIN
;
622 clk_writel(0, c
->reg
+ SUPER_CLK_DIVIDER
);
625 static u8
tegra30_super_clk_get_parent(struct clk_hw
*hw
)
627 struct clk_tegra
*c
= to_clk_tegra(hw
);
632 val
= clk_readl(c
->reg
+ SUPER_CLK_MUX
);
633 BUG_ON(((val
& SUPER_STATE_MASK
) != SUPER_STATE_RUN
) &&
634 ((val
& SUPER_STATE_MASK
) != SUPER_STATE_IDLE
));
635 shift
= ((val
& SUPER_STATE_MASK
) == SUPER_STATE_IDLE
) ?
636 SUPER_IDLE_SOURCE_SHIFT
: SUPER_RUN_SOURCE_SHIFT
;
637 source
= (val
>> shift
) & SUPER_SOURCE_MASK
;
638 if (c
->flags
& DIV_2
)
639 source
|= val
& SUPER_LP_DIV2_BYPASS
;
644 static int tegra30_super_clk_set_parent(struct clk_hw
*hw
, u8 index
)
646 struct clk_tegra
*c
= to_clk_tegra(hw
);
647 struct clk_tegra
*p
=
648 to_clk_tegra(__clk_get_hw(clk_get_parent(hw
->clk
)));
652 val
= clk_readl(c
->reg
+ SUPER_CLK_MUX
);
653 BUG_ON(((val
& SUPER_STATE_MASK
) != SUPER_STATE_RUN
) &&
654 ((val
& SUPER_STATE_MASK
) != SUPER_STATE_IDLE
));
655 shift
= ((val
& SUPER_STATE_MASK
) == SUPER_STATE_IDLE
) ?
656 SUPER_IDLE_SOURCE_SHIFT
: SUPER_RUN_SOURCE_SHIFT
;
658 /* For LP mode super-clock switch between PLLX direct
659 and divided-by-2 outputs is allowed only when other
660 than PLLX clock source is current parent */
661 if ((c
->flags
& DIV_2
) && (p
->flags
& PLLX
) &&
662 ((index
^ val
) & SUPER_LP_DIV2_BYPASS
)) {
665 val
^= SUPER_LP_DIV2_BYPASS
;
666 clk_writel_delay(val
, c
->reg
);
668 val
&= ~(SUPER_SOURCE_MASK
<< shift
);
669 val
|= (index
& SUPER_SOURCE_MASK
) << shift
;
671 /* 7.1 divider for CPU super-clock does not affect
673 if (c
->flags
& DIV_U71
) {
675 if (!(p
->flags
& PLLX
)) {
676 div
= clk_readl(c
->reg
+
678 div
&= SUPER_CLOCK_DIV_U71_MASK
;
679 div
>>= SUPER_CLOCK_DIV_U71_SHIFT
;
684 clk_writel_delay(val
, c
->reg
);
690 * Do not use super clocks "skippers", since dividing using a clock skipper
691 * does not allow the voltage to be scaled down. Instead adjust the rate of
692 * the parent clock. This requires that the parent of a super clock have no
693 * other children, otherwise the rate will change underneath the other
694 * children. Special case: if fixed rate PLL is CPU super clock parent the
695 * rate of this PLL can't be changed, and it has many other children. In
696 * this case use 7.1 fractional divider to adjust the super clock rate.
698 static int tegra30_super_clk_set_rate(struct clk_hw
*hw
, unsigned long rate
,
699 unsigned long parent_rate
)
701 struct clk_tegra
*c
= to_clk_tegra(hw
);
702 struct clk
*parent
= __clk_get_parent(hw
->clk
);
703 struct clk_tegra
*cparent
= to_clk_tegra(__clk_get_hw(parent
));
705 if ((c
->flags
& DIV_U71
) && (cparent
->flags
& PLL_FIXED
)) {
706 int div
= clk_div71_get_divider(parent_rate
,
707 rate
, c
->flags
, ROUND_DIVIDER_DOWN
);
708 div
= max(div
, SUPER_CLOCK_DIV_U71_MIN
);
710 clk_writel(div
<< SUPER_CLOCK_DIV_U71_SHIFT
,
711 c
->reg
+ SUPER_CLK_DIVIDER
);
719 static unsigned long tegra30_super_clk_recalc_rate(struct clk_hw
*hw
,
720 unsigned long parent_rate
)
722 struct clk_tegra
*c
= to_clk_tegra(hw
);
723 u64 rate
= parent_rate
;
725 if (c
->mul
!= 0 && c
->div
!= 0) {
727 rate
+= c
->div
- 1; /* round up */
728 do_div(rate
, c
->div
);
734 static long tegra30_super_clk_round_rate(struct clk_hw
*hw
, unsigned long rate
,
735 unsigned long *prate
)
737 struct clk_tegra
*c
= to_clk_tegra(hw
);
738 struct clk
*parent
= __clk_get_parent(hw
->clk
);
739 struct clk_tegra
*cparent
= to_clk_tegra(__clk_get_hw(parent
));
743 if ((c
->flags
& DIV_U71
) && (cparent
->flags
& PLL_FIXED
)) {
744 div
= clk_div71_get_divider(*prate
,
745 rate
, c
->flags
, ROUND_DIVIDER_DOWN
);
746 div
= max(div
, SUPER_CLOCK_DIV_U71_MIN
) + 2;
748 rate
+= div
- 1; /* round up */
749 do_div(rate
, c
->div
);
756 struct clk_ops tegra30_super_ops
= {
757 .init
= tegra30_super_clk_init
,
758 .set_parent
= tegra30_super_clk_set_parent
,
759 .get_parent
= tegra30_super_clk_get_parent
,
760 .recalc_rate
= tegra30_super_clk_recalc_rate
,
761 .round_rate
= tegra30_super_clk_round_rate
,
762 .set_rate
= tegra30_super_clk_set_rate
,
765 static unsigned long tegra30_twd_clk_recalc_rate(struct clk_hw
*hw
,
766 unsigned long parent_rate
)
768 struct clk_tegra
*c
= to_clk_tegra(hw
);
769 u64 rate
= parent_rate
;
771 if (c
->mul
!= 0 && c
->div
!= 0) {
773 rate
+= c
->div
- 1; /* round up */
774 do_div(rate
, c
->div
);
780 struct clk_ops tegra30_twd_ops
= {
781 .recalc_rate
= tegra30_twd_clk_recalc_rate
,
784 /* Blink output functions */
785 static int tegra30_blink_clk_is_enabled(struct clk_hw
*hw
)
787 struct clk_tegra
*c
= to_clk_tegra(hw
);
790 val
= pmc_readl(PMC_CTRL
);
791 c
->state
= (val
& PMC_CTRL_BLINK_ENB
) ? ON
: OFF
;
795 static int tegra30_blink_clk_enable(struct clk_hw
*hw
)
799 val
= pmc_readl(PMC_DPD_PADS_ORIDE
);
800 pmc_writel(val
| PMC_DPD_PADS_ORIDE_BLINK_ENB
, PMC_DPD_PADS_ORIDE
);
802 val
= pmc_readl(PMC_CTRL
);
803 pmc_writel(val
| PMC_CTRL_BLINK_ENB
, PMC_CTRL
);
808 static void tegra30_blink_clk_disable(struct clk_hw
*hw
)
812 val
= pmc_readl(PMC_CTRL
);
813 pmc_writel(val
& ~PMC_CTRL_BLINK_ENB
, PMC_CTRL
);
815 val
= pmc_readl(PMC_DPD_PADS_ORIDE
);
816 pmc_writel(val
& ~PMC_DPD_PADS_ORIDE_BLINK_ENB
, PMC_DPD_PADS_ORIDE
);
819 static int tegra30_blink_clk_set_rate(struct clk_hw
*hw
, unsigned long rate
,
820 unsigned long parent_rate
)
822 struct clk_tegra
*c
= to_clk_tegra(hw
);
824 if (rate
>= parent_rate
) {
826 pmc_writel(0, c
->reg
);
831 on_off
= DIV_ROUND_UP(parent_rate
/ 8, rate
);
834 val
= (on_off
& PMC_BLINK_TIMER_DATA_ON_MASK
) <<
835 PMC_BLINK_TIMER_DATA_ON_SHIFT
;
836 on_off
&= PMC_BLINK_TIMER_DATA_OFF_MASK
;
837 on_off
<<= PMC_BLINK_TIMER_DATA_OFF_SHIFT
;
839 val
|= PMC_BLINK_TIMER_ENB
;
840 pmc_writel(val
, c
->reg
);
846 static unsigned long tegra30_blink_clk_recalc_rate(struct clk_hw
*hw
,
847 unsigned long parent_rate
)
849 struct clk_tegra
*c
= to_clk_tegra(hw
);
850 u64 rate
= parent_rate
;
857 val
= pmc_readl(c
->reg
);
859 if (val
& PMC_BLINK_TIMER_ENB
) {
860 on_off
= (val
>> PMC_BLINK_TIMER_DATA_ON_SHIFT
) &
861 PMC_BLINK_TIMER_DATA_ON_MASK
;
862 val
>>= PMC_BLINK_TIMER_DATA_OFF_SHIFT
;
863 val
&= PMC_BLINK_TIMER_DATA_OFF_MASK
;
865 /* each tick in the blink timer is 4 32KHz clocks */
871 if (mul
!= 0 && div
!= 0) {
873 rate
+= div
- 1; /* round up */
879 static long tegra30_blink_clk_round_rate(struct clk_hw
*hw
, unsigned long rate
,
880 unsigned long *prate
)
884 long round_rate
= *prate
;
888 if (rate
>= *prate
) {
891 div
= DIV_ROUND_UP(*prate
/ 8, rate
);
896 round_rate
+= div
- 1;
897 do_div(round_rate
, div
);
902 struct clk_ops tegra30_blink_clk_ops
= {
903 .is_enabled
= tegra30_blink_clk_is_enabled
,
904 .enable
= tegra30_blink_clk_enable
,
905 .disable
= tegra30_blink_clk_disable
,
906 .recalc_rate
= tegra30_blink_clk_recalc_rate
,
907 .round_rate
= tegra30_blink_clk_round_rate
,
908 .set_rate
= tegra30_blink_clk_set_rate
,
911 static void tegra30_utmi_param_configure(struct clk_hw
*hw
)
913 unsigned long main_rate
=
914 __clk_get_rate(__clk_get_parent(__clk_get_parent(hw
->clk
)));
918 for (i
= 0; i
< ARRAY_SIZE(utmi_parameters
); i
++) {
919 if (main_rate
== utmi_parameters
[i
].osc_frequency
)
923 if (i
>= ARRAY_SIZE(utmi_parameters
)) {
924 pr_err("%s: Unexpected main rate %lu\n", __func__
, main_rate
);
928 reg
= clk_readl(UTMIP_PLL_CFG2
);
930 /* Program UTMIP PLL stable and active counts */
931 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
932 reg
&= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
933 reg
|= UTMIP_PLL_CFG2_STABLE_COUNT(
934 utmi_parameters
[i
].stable_count
);
936 reg
&= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
938 reg
|= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(
939 utmi_parameters
[i
].active_delay_count
);
941 /* Remove power downs from UTMIP PLL control bits */
942 reg
&= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN
;
943 reg
&= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN
;
944 reg
&= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN
;
946 clk_writel(reg
, UTMIP_PLL_CFG2
);
948 /* Program UTMIP PLL delay and oscillator frequency counts */
949 reg
= clk_readl(UTMIP_PLL_CFG1
);
950 reg
&= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
952 reg
|= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(
953 utmi_parameters
[i
].enable_delay_count
);
955 reg
&= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
956 reg
|= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(
957 utmi_parameters
[i
].xtal_freq_count
);
959 /* Remove power downs from UTMIP PLL control bits */
960 reg
&= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN
;
961 reg
&= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN
;
962 reg
&= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN
;
964 clk_writel(reg
, UTMIP_PLL_CFG1
);
968 static int tegra30_pll_clk_wait_for_lock(struct clk_tegra
*c
, u32 lock_reg
,
973 #if USE_PLL_LOCK_BITS
975 for (i
= 0; i
< c
->u
.pll
.lock_delay
; i
++) {
976 if (clk_readl(lock_reg
) & lock_bit
) {
977 udelay(PLL_POST_LOCK_DELAY
);
980 udelay(2); /* timeout = 2 * lock time */
982 pr_err("Timed out waiting for lock bit on pll %s",
983 __clk_get_name(hw
->clk
));
986 udelay(c
->u
.pll
.lock_delay
);
991 static int tegra30_pll_clk_is_enabled(struct clk_hw
*hw
)
993 struct clk_tegra
*c
= to_clk_tegra(hw
);
994 u32 val
= clk_readl(c
->reg
+ PLL_BASE
);
996 c
->state
= (val
& PLL_BASE_ENABLE
) ? ON
: OFF
;
1000 static void tegra30_pll_clk_init(struct clk_hw
*hw
)
1002 struct clk_tegra
*c
= to_clk_tegra(hw
);
1004 if (c
->flags
& PLLU
)
1005 tegra30_utmi_param_configure(hw
);
1008 static int tegra30_pll_clk_enable(struct clk_hw
*hw
)
1010 struct clk_tegra
*c
= to_clk_tegra(hw
);
1012 pr_debug("%s on clock %s\n", __func__
, __clk_get_name(hw
->clk
));
1014 #if USE_PLL_LOCK_BITS
1015 val
= clk_readl(c
->reg
+ PLL_MISC(c
));
1016 val
|= PLL_MISC_LOCK_ENABLE(c
);
1017 clk_writel(val
, c
->reg
+ PLL_MISC(c
));
1019 val
= clk_readl(c
->reg
+ PLL_BASE
);
1020 val
&= ~PLL_BASE_BYPASS
;
1021 val
|= PLL_BASE_ENABLE
;
1022 clk_writel(val
, c
->reg
+ PLL_BASE
);
1024 if (c
->flags
& PLLM
) {
1025 val
= pmc_readl(PMC_PLLP_WB0_OVERRIDE
);
1026 val
|= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE
;
1027 pmc_writel(val
, PMC_PLLP_WB0_OVERRIDE
);
1030 tegra30_pll_clk_wait_for_lock(c
, c
->reg
+ PLL_BASE
, PLL_BASE_LOCK
);
1035 static void tegra30_pll_clk_disable(struct clk_hw
*hw
)
1037 struct clk_tegra
*c
= to_clk_tegra(hw
);
1039 pr_debug("%s on clock %s\n", __func__
, __clk_get_name(hw
->clk
));
1041 val
= clk_readl(c
->reg
);
1042 val
&= ~(PLL_BASE_BYPASS
| PLL_BASE_ENABLE
);
1043 clk_writel(val
, c
->reg
);
1045 if (c
->flags
& PLLM
) {
1046 val
= pmc_readl(PMC_PLLP_WB0_OVERRIDE
);
1047 val
&= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE
;
1048 pmc_writel(val
, PMC_PLLP_WB0_OVERRIDE
);
1052 static int tegra30_pll_clk_set_rate(struct clk_hw
*hw
, unsigned long rate
,
1053 unsigned long parent_rate
)
1055 struct clk_tegra
*c
= to_clk_tegra(hw
);
1056 u32 val
, p_div
, old_base
;
1057 unsigned long input_rate
;
1058 const struct clk_pll_freq_table
*sel
;
1059 struct clk_pll_freq_table cfg
;
1061 if (c
->flags
& PLL_FIXED
) {
1063 if (rate
!= c
->u
.pll
.fixed_rate
) {
1064 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
1065 __func__
, __clk_get_name(hw
->clk
),
1066 c
->u
.pll
.fixed_rate
, rate
);
1072 if (c
->flags
& PLLM
) {
1073 if (rate
!= __clk_get_rate(hw
->clk
)) {
1074 pr_err("%s: Can not change memory %s rate in flight\n",
1075 __func__
, __clk_get_name(hw
->clk
));
1081 input_rate
= parent_rate
;
1083 /* Check if the target rate is tabulated */
1084 for (sel
= c
->u
.pll
.freq_table
; sel
->input_rate
!= 0; sel
++) {
1085 if (sel
->input_rate
== input_rate
&& sel
->output_rate
== rate
) {
1086 if (c
->flags
& PLLU
) {
1087 BUG_ON(sel
->p
< 1 || sel
->p
> 2);
1089 p_div
= PLLU_BASE_POST_DIV
;
1092 for (val
= sel
->p
; val
> 1; val
>>= 1)
1094 p_div
<<= PLL_BASE_DIVP_SHIFT
;
1100 /* Configure out-of-table rate */
1101 if (sel
->input_rate
== 0) {
1102 unsigned long cfreq
;
1103 BUG_ON(c
->flags
& PLLU
);
1106 switch (input_rate
) {
1109 cfreq
= (rate
<= 1000000 * 1000) ? 1000000 : 2000000;
1112 cfreq
= (rate
<= 1000000 * 1000) ? 1000000 : 2600000;
1116 cfreq
= (rate
<= 1200000 * 1000) ? 1200000 : 2400000;
1119 pr_err("%s: Unexpected reference rate %lu\n",
1120 __func__
, input_rate
);
1124 /* Raise VCO to guarantee 0.5% accuracy */
1125 for (cfg
.output_rate
= rate
; cfg
.output_rate
< 200 * cfreq
;
1126 cfg
.output_rate
<<= 1)
1129 cfg
.p
= 0x1 << p_div
;
1130 cfg
.m
= input_rate
/ cfreq
;
1131 cfg
.n
= cfg
.output_rate
/ cfreq
;
1132 cfg
.cpcon
= OUT_OF_TABLE_CPCON
;
1134 if ((cfg
.m
> (PLL_BASE_DIVM_MASK
>> PLL_BASE_DIVM_SHIFT
)) ||
1135 (cfg
.n
> (PLL_BASE_DIVN_MASK
>> PLL_BASE_DIVN_SHIFT
)) ||
1136 (p_div
> (PLL_BASE_DIVP_MASK
>> PLL_BASE_DIVP_SHIFT
)) ||
1137 (cfg
.output_rate
> c
->u
.pll
.vco_max
)) {
1138 pr_err("%s: Failed to set %s out-of-table rate %lu\n",
1139 __func__
, __clk_get_name(hw
->clk
), rate
);
1142 p_div
<<= PLL_BASE_DIVP_SHIFT
;
1146 c
->div
= sel
->m
* sel
->p
;
1148 old_base
= val
= clk_readl(c
->reg
+ PLL_BASE
);
1149 val
&= ~(PLL_BASE_DIVM_MASK
| PLL_BASE_DIVN_MASK
|
1150 ((c
->flags
& PLLU
) ? PLLU_BASE_POST_DIV
: PLL_BASE_DIVP_MASK
));
1151 val
|= (sel
->m
<< PLL_BASE_DIVM_SHIFT
) |
1152 (sel
->n
<< PLL_BASE_DIVN_SHIFT
) | p_div
;
1153 if (val
== old_base
)
1156 if (c
->state
== ON
) {
1157 tegra30_pll_clk_disable(hw
);
1158 val
&= ~(PLL_BASE_BYPASS
| PLL_BASE_ENABLE
);
1160 clk_writel(val
, c
->reg
+ PLL_BASE
);
1162 if (c
->flags
& PLL_HAS_CPCON
) {
1163 val
= clk_readl(c
->reg
+ PLL_MISC(c
));
1164 val
&= ~PLL_MISC_CPCON_MASK
;
1165 val
|= sel
->cpcon
<< PLL_MISC_CPCON_SHIFT
;
1166 if (c
->flags
& (PLLU
| PLLD
)) {
1167 val
&= ~PLL_MISC_LFCON_MASK
;
1168 if (sel
->n
>= PLLDU_LFCON_SET_DIVN
)
1169 val
|= 0x1 << PLL_MISC_LFCON_SHIFT
;
1170 } else if (c
->flags
& (PLLX
| PLLM
)) {
1171 val
&= ~(0x1 << PLL_MISC_DCCON_SHIFT
);
1172 if (rate
>= (c
->u
.pll
.vco_max
>> 1))
1173 val
|= 0x1 << PLL_MISC_DCCON_SHIFT
;
1175 clk_writel(val
, c
->reg
+ PLL_MISC(c
));
1179 tegra30_pll_clk_enable(hw
);
1181 c
->u
.pll
.fixed_rate
= rate
;
1186 static long tegra30_pll_round_rate(struct clk_hw
*hw
, unsigned long rate
,
1187 unsigned long *prate
)
1189 struct clk_tegra
*c
= to_clk_tegra(hw
);
1190 unsigned long input_rate
= *prate
;
1191 unsigned long output_rate
= *prate
;
1192 const struct clk_pll_freq_table
*sel
;
1193 struct clk_pll_freq_table cfg
;
1199 if (c
->flags
& PLL_FIXED
)
1200 return c
->u
.pll
.fixed_rate
;
1202 if (c
->flags
& PLLM
)
1203 return __clk_get_rate(hw
->clk
);
1206 /* Check if the target rate is tabulated */
1207 for (sel
= c
->u
.pll
.freq_table
; sel
->input_rate
!= 0; sel
++) {
1208 if (sel
->input_rate
== input_rate
&& sel
->output_rate
== rate
) {
1209 if (c
->flags
& PLLU
) {
1210 BUG_ON(sel
->p
< 1 || sel
->p
> 2);
1212 p_div
= PLLU_BASE_POST_DIV
;
1215 for (val
= sel
->p
; val
> 1; val
>>= 1)
1217 p_div
<<= PLL_BASE_DIVP_SHIFT
;
1223 if (sel
->input_rate
== 0) {
1224 unsigned long cfreq
;
1225 BUG_ON(c
->flags
& PLLU
);
1228 switch (input_rate
) {
1231 cfreq
= (rate
<= 1000000 * 1000) ? 1000000 : 2000000;
1234 cfreq
= (rate
<= 1000000 * 1000) ? 1000000 : 2600000;
1238 cfreq
= (rate
<= 1200000 * 1000) ? 1200000 : 2400000;
1241 pr_err("%s: Unexpected reference rate %lu\n",
1242 __func__
, input_rate
);
1246 /* Raise VCO to guarantee 0.5% accuracy */
1247 for (cfg
.output_rate
= rate
; cfg
.output_rate
< 200 * cfreq
;
1248 cfg
.output_rate
<<= 1)
1251 cfg
.p
= 0x1 << p_div
;
1252 cfg
.m
= input_rate
/ cfreq
;
1253 cfg
.n
= cfg
.output_rate
/ cfreq
;
1257 div
= sel
->m
* sel
->p
;
1260 output_rate
+= div
- 1; /* round up */
1261 do_div(output_rate
, div
);
1266 static unsigned long tegra30_pll_recalc_rate(struct clk_hw
*hw
,
1267 unsigned long parent_rate
)
1269 struct clk_tegra
*c
= to_clk_tegra(hw
);
1270 u64 rate
= parent_rate
;
1271 u32 val
= clk_readl(c
->reg
+ PLL_BASE
);
1273 if (c
->flags
& PLL_FIXED
&& !(val
& PLL_BASE_OVERRIDE
)) {
1274 const struct clk_pll_freq_table
*sel
;
1275 for (sel
= c
->u
.pll
.freq_table
; sel
->input_rate
!= 0; sel
++) {
1276 if (sel
->input_rate
== parent_rate
&&
1277 sel
->output_rate
== c
->u
.pll
.fixed_rate
) {
1279 c
->div
= sel
->m
* sel
->p
;
1283 pr_err("Clock %s has unknown fixed frequency\n",
1284 __clk_get_name(hw
->clk
));
1286 } else if (val
& PLL_BASE_BYPASS
) {
1290 c
->mul
= (val
& PLL_BASE_DIVN_MASK
) >> PLL_BASE_DIVN_SHIFT
;
1291 c
->div
= (val
& PLL_BASE_DIVM_MASK
) >> PLL_BASE_DIVM_SHIFT
;
1292 if (c
->flags
& PLLU
)
1293 c
->div
*= (val
& PLLU_BASE_POST_DIV
) ? 1 : 2;
1295 c
->div
*= (0x1 << ((val
& PLL_BASE_DIVP_MASK
) >>
1296 PLL_BASE_DIVP_SHIFT
));
1299 if (c
->mul
!= 0 && c
->div
!= 0) {
1301 rate
+= c
->div
- 1; /* round up */
1302 do_div(rate
, c
->div
);
1308 struct clk_ops tegra30_pll_ops
= {
1309 .is_enabled
= tegra30_pll_clk_is_enabled
,
1310 .init
= tegra30_pll_clk_init
,
1311 .enable
= tegra30_pll_clk_enable
,
1312 .disable
= tegra30_pll_clk_disable
,
1313 .recalc_rate
= tegra30_pll_recalc_rate
,
1314 .round_rate
= tegra30_pll_round_rate
,
1315 .set_rate
= tegra30_pll_clk_set_rate
,
1318 int tegra30_plld_clk_cfg_ex(struct clk_hw
*hw
,
1319 enum tegra_clk_ex_param p
, u32 setting
)
1321 struct clk_tegra
*c
= to_clk_tegra(hw
);
1325 case TEGRA_CLK_PLLD_CSI_OUT_ENB
:
1326 mask
= PLLD_BASE_CSI_CLKENABLE
;
1327 reg
= c
->reg
+ PLL_BASE
;
1329 case TEGRA_CLK_PLLD_DSI_OUT_ENB
:
1330 mask
= PLLD_MISC_DSI_CLKENABLE
;
1331 reg
= c
->reg
+ PLL_MISC(c
);
1333 case TEGRA_CLK_PLLD_MIPI_MUX_SEL
:
1334 if (!(c
->flags
& PLL_ALT_MISC_REG
)) {
1335 mask
= PLLD_BASE_DSIB_MUX_MASK
;
1336 reg
= c
->reg
+ PLL_BASE
;
1339 /* fall through - error since PLLD2 does not have MUX_SEL control */
1344 val
= clk_readl(reg
);
1349 clk_writel(val
, reg
);
1353 static int tegra30_plle_clk_is_enabled(struct clk_hw
*hw
)
1355 struct clk_tegra
*c
= to_clk_tegra(hw
);
1358 val
= clk_readl(c
->reg
+ PLL_BASE
);
1359 c
->state
= (val
& PLLE_BASE_ENABLE
) ? ON
: OFF
;
1363 static void tegra30_plle_clk_disable(struct clk_hw
*hw
)
1365 struct clk_tegra
*c
= to_clk_tegra(hw
);
1368 val
= clk_readl(c
->reg
+ PLL_BASE
);
1369 val
&= ~(PLLE_BASE_CML_ENABLE
| PLLE_BASE_ENABLE
);
1370 clk_writel(val
, c
->reg
+ PLL_BASE
);
1373 static void tegra30_plle_training(struct clk_tegra
*c
)
1377 /* PLLE is already disabled, and setup cleared;
1378 * create falling edge on PLLE IDDQ input */
1379 val
= pmc_readl(PMC_SATA_PWRGT
);
1380 val
|= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE
;
1381 pmc_writel(val
, PMC_SATA_PWRGT
);
1383 val
= pmc_readl(PMC_SATA_PWRGT
);
1384 val
|= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL
;
1385 pmc_writel(val
, PMC_SATA_PWRGT
);
1387 val
= pmc_readl(PMC_SATA_PWRGT
);
1388 val
&= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE
;
1389 pmc_writel(val
, PMC_SATA_PWRGT
);
1392 val
= clk_readl(c
->reg
+ PLL_MISC(c
));
1393 } while (!(val
& PLLE_MISC_READY
));
1396 static int tegra30_plle_configure(struct clk_hw
*hw
, bool force_training
)
1398 struct clk_tegra
*c
= to_clk_tegra(hw
);
1399 struct clk
*parent
= __clk_get_parent(hw
->clk
);
1400 const struct clk_pll_freq_table
*sel
;
1403 unsigned long rate
= c
->u
.pll
.fixed_rate
;
1404 unsigned long input_rate
= __clk_get_rate(parent
);
1406 for (sel
= c
->u
.pll
.freq_table
; sel
->input_rate
!= 0; sel
++) {
1407 if (sel
->input_rate
== input_rate
&& sel
->output_rate
== rate
)
1411 if (sel
->input_rate
== 0)
1414 /* disable PLLE, clear setup fiels */
1415 tegra30_plle_clk_disable(hw
);
1417 val
= clk_readl(c
->reg
+ PLL_MISC(c
));
1418 val
&= ~(PLLE_MISC_LOCK_ENABLE
| PLLE_MISC_SETUP_MASK
);
1419 clk_writel(val
, c
->reg
+ PLL_MISC(c
));
1422 val
= clk_readl(c
->reg
+ PLL_MISC(c
));
1423 if (force_training
|| (!(val
& PLLE_MISC_READY
)))
1424 tegra30_plle_training(c
);
1426 /* configure dividers, setup, disable SS */
1427 val
= clk_readl(c
->reg
+ PLL_BASE
);
1428 val
&= ~PLLE_BASE_DIV_MASK
;
1429 val
|= PLLE_BASE_DIV(sel
->m
, sel
->n
, sel
->p
, sel
->cpcon
);
1430 clk_writel(val
, c
->reg
+ PLL_BASE
);
1432 c
->div
= sel
->m
* sel
->p
;
1434 val
= clk_readl(c
->reg
+ PLL_MISC(c
));
1435 val
|= PLLE_MISC_SETUP_VALUE
;
1436 val
|= PLLE_MISC_LOCK_ENABLE
;
1437 clk_writel(val
, c
->reg
+ PLL_MISC(c
));
1439 val
= clk_readl(PLLE_SS_CTRL
);
1440 val
|= PLLE_SS_DISABLE
;
1441 clk_writel(val
, PLLE_SS_CTRL
);
1443 /* enable and lock PLLE*/
1444 val
= clk_readl(c
->reg
+ PLL_BASE
);
1445 val
|= (PLLE_BASE_CML_ENABLE
| PLLE_BASE_ENABLE
);
1446 clk_writel(val
, c
->reg
+ PLL_BASE
);
1448 tegra30_pll_clk_wait_for_lock(c
, c
->reg
+ PLL_MISC(c
), PLLE_MISC_LOCK
);
1453 static int tegra30_plle_clk_enable(struct clk_hw
*hw
)
1455 struct clk_tegra
*c
= to_clk_tegra(hw
);
1457 return tegra30_plle_configure(hw
, !c
->set
);
1460 static unsigned long tegra30_plle_clk_recalc_rate(struct clk_hw
*hw
,
1461 unsigned long parent_rate
)
1463 struct clk_tegra
*c
= to_clk_tegra(hw
);
1464 unsigned long rate
= parent_rate
;
1467 val
= clk_readl(c
->reg
+ PLL_BASE
);
1468 c
->mul
= (val
& PLLE_BASE_DIVN_MASK
) >> PLLE_BASE_DIVN_SHIFT
;
1469 c
->div
= (val
& PLLE_BASE_DIVM_MASK
) >> PLLE_BASE_DIVM_SHIFT
;
1470 c
->div
*= (val
& PLLE_BASE_DIVP_MASK
) >> PLLE_BASE_DIVP_SHIFT
;
1472 if (c
->mul
!= 0 && c
->div
!= 0) {
1474 rate
+= c
->div
- 1; /* round up */
1475 do_div(rate
, c
->div
);
1480 struct clk_ops tegra30_plle_ops
= {
1481 .is_enabled
= tegra30_plle_clk_is_enabled
,
1482 .enable
= tegra30_plle_clk_enable
,
1483 .disable
= tegra30_plle_clk_disable
,
1484 .recalc_rate
= tegra30_plle_clk_recalc_rate
,
1487 /* Clock divider ops */
1488 static int tegra30_pll_div_clk_is_enabled(struct clk_hw
*hw
)
1490 struct clk_tegra
*c
= to_clk_tegra(hw
);
1492 if (c
->flags
& DIV_U71
) {
1493 u32 val
= clk_readl(c
->reg
);
1494 val
>>= c
->reg_shift
;
1495 c
->state
= (val
& PLL_OUT_CLKEN
) ? ON
: OFF
;
1496 if (!(val
& PLL_OUT_RESET_DISABLE
))
1504 static int tegra30_pll_div_clk_enable(struct clk_hw
*hw
)
1506 struct clk_tegra
*c
= to_clk_tegra(hw
);
1510 pr_debug("%s: %s\n", __func__
, __clk_get_name(hw
->clk
));
1511 if (c
->flags
& DIV_U71
) {
1512 val
= clk_readl(c
->reg
);
1513 new_val
= val
>> c
->reg_shift
;
1516 new_val
|= PLL_OUT_CLKEN
| PLL_OUT_RESET_DISABLE
;
1518 val
&= ~(0xFFFF << c
->reg_shift
);
1519 val
|= new_val
<< c
->reg_shift
;
1520 clk_writel_delay(val
, c
->reg
);
1522 } else if (c
->flags
& DIV_2
) {
1528 static void tegra30_pll_div_clk_disable(struct clk_hw
*hw
)
1530 struct clk_tegra
*c
= to_clk_tegra(hw
);
1534 pr_debug("%s: %s\n", __func__
, __clk_get_name(hw
->clk
));
1535 if (c
->flags
& DIV_U71
) {
1536 val
= clk_readl(c
->reg
);
1537 new_val
= val
>> c
->reg_shift
;
1540 new_val
&= ~(PLL_OUT_CLKEN
| PLL_OUT_RESET_DISABLE
);
1542 val
&= ~(0xFFFF << c
->reg_shift
);
1543 val
|= new_val
<< c
->reg_shift
;
1544 clk_writel_delay(val
, c
->reg
);
1548 static int tegra30_pll_div_clk_set_rate(struct clk_hw
*hw
, unsigned long rate
,
1549 unsigned long parent_rate
)
1551 struct clk_tegra
*c
= to_clk_tegra(hw
);
1556 if (c
->flags
& DIV_U71
) {
1557 divider_u71
= clk_div71_get_divider(
1558 parent_rate
, rate
, c
->flags
, ROUND_DIVIDER_UP
);
1559 if (divider_u71
>= 0) {
1560 val
= clk_readl(c
->reg
);
1561 new_val
= val
>> c
->reg_shift
;
1563 if (c
->flags
& DIV_U71_FIXED
)
1564 new_val
|= PLL_OUT_OVERRIDE
;
1565 new_val
&= ~PLL_OUT_RATIO_MASK
;
1566 new_val
|= divider_u71
<< PLL_OUT_RATIO_SHIFT
;
1568 val
&= ~(0xFFFF << c
->reg_shift
);
1569 val
|= new_val
<< c
->reg_shift
;
1570 clk_writel_delay(val
, c
->reg
);
1571 c
->div
= divider_u71
+ 2;
1573 c
->fixed_rate
= rate
;
1576 } else if (c
->flags
& DIV_2
) {
1577 c
->fixed_rate
= rate
;
1584 static unsigned long tegra30_pll_div_clk_recalc_rate(struct clk_hw
*hw
,
1585 unsigned long parent_rate
)
1587 struct clk_tegra
*c
= to_clk_tegra(hw
);
1588 u64 rate
= parent_rate
;
1590 if (c
->flags
& DIV_U71
) {
1592 u32 val
= clk_readl(c
->reg
);
1593 val
>>= c
->reg_shift
;
1595 divu71
= (val
& PLL_OUT_RATIO_MASK
) >> PLL_OUT_RATIO_SHIFT
;
1596 c
->div
= (divu71
+ 2);
1598 } else if (c
->flags
& DIV_2
) {
1599 if (c
->flags
& (PLLD
| PLLX
)) {
1608 if (c
->mul
!= 0 && c
->div
!= 0) {
1610 rate
+= c
->div
- 1; /* round up */
1611 do_div(rate
, c
->div
);
1617 static long tegra30_pll_div_clk_round_rate(struct clk_hw
*hw
,
1618 unsigned long rate
, unsigned long *prate
)
1620 struct clk_tegra
*c
= to_clk_tegra(hw
);
1621 unsigned long parent_rate
= __clk_get_rate(__clk_get_parent(hw
->clk
));
1625 parent_rate
= *prate
;
1627 if (c
->flags
& DIV_U71
) {
1628 divider
= clk_div71_get_divider(
1629 parent_rate
, rate
, c
->flags
, ROUND_DIVIDER_UP
);
1632 return DIV_ROUND_UP(parent_rate
* 2, divider
+ 2);
1633 } else if (c
->flags
& DIV_2
) {
1641 struct clk_ops tegra30_pll_div_ops
= {
1642 .is_enabled
= tegra30_pll_div_clk_is_enabled
,
1643 .enable
= tegra30_pll_div_clk_enable
,
1644 .disable
= tegra30_pll_div_clk_disable
,
1645 .set_rate
= tegra30_pll_div_clk_set_rate
,
1646 .recalc_rate
= tegra30_pll_div_clk_recalc_rate
,
1647 .round_rate
= tegra30_pll_div_clk_round_rate
,
1650 /* Periph clk ops */
1651 static inline u32
periph_clk_source_mask(struct clk_tegra
*c
)
1653 if (c
->flags
& MUX8
)
1655 else if (c
->flags
& MUX_PWM
)
1657 else if (c
->flags
& MUX_CLK_OUT
)
1658 return 3 << (c
->u
.periph
.clk_num
+ 4);
1659 else if (c
->flags
& PLLD
)
1660 return PLLD_BASE_DSIB_MUX_MASK
;
1665 static inline u32
periph_clk_source_shift(struct clk_tegra
*c
)
1667 if (c
->flags
& MUX8
)
1669 else if (c
->flags
& MUX_PWM
)
1671 else if (c
->flags
& MUX_CLK_OUT
)
1672 return c
->u
.periph
.clk_num
+ 4;
1673 else if (c
->flags
& PLLD
)
1674 return PLLD_BASE_DSIB_MUX_SHIFT
;
1679 static int tegra30_periph_clk_is_enabled(struct clk_hw
*hw
)
1681 struct clk_tegra
*c
= to_clk_tegra(hw
);
1684 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c
)) & PERIPH_CLK_TO_BIT(c
)))
1686 if (!(c
->flags
& PERIPH_NO_RESET
))
1687 if (clk_readl(PERIPH_CLK_TO_RST_REG(c
)) & PERIPH_CLK_TO_BIT(c
))
1692 static int tegra30_periph_clk_enable(struct clk_hw
*hw
)
1694 struct clk_tegra
*c
= to_clk_tegra(hw
);
1696 tegra_periph_clk_enable_refcount
[c
->u
.periph
.clk_num
]++;
1697 if (tegra_periph_clk_enable_refcount
[c
->u
.periph
.clk_num
] > 1)
1700 clk_writel_delay(PERIPH_CLK_TO_BIT(c
), PERIPH_CLK_TO_ENB_SET_REG(c
));
1701 if (!(c
->flags
& PERIPH_NO_RESET
) &&
1702 !(c
->flags
& PERIPH_MANUAL_RESET
)) {
1703 if (clk_readl(PERIPH_CLK_TO_RST_REG(c
)) &
1704 PERIPH_CLK_TO_BIT(c
)) {
1705 udelay(5); /* reset propagation delay */
1706 clk_writel(PERIPH_CLK_TO_BIT(c
),
1707 PERIPH_CLK_TO_RST_CLR_REG(c
));
1713 static void tegra30_periph_clk_disable(struct clk_hw
*hw
)
1715 struct clk_tegra
*c
= to_clk_tegra(hw
);
1718 tegra_periph_clk_enable_refcount
[c
->u
.periph
.clk_num
]--;
1720 if (tegra_periph_clk_enable_refcount
[c
->u
.periph
.clk_num
] > 0)
1723 /* If peripheral is in the APB bus then read the APB bus to
1724 * flush the write operation in apb bus. This will avoid the
1725 * peripheral access after disabling clock*/
1726 if (c
->flags
& PERIPH_ON_APB
)
1727 val
= chipid_readl();
1729 clk_writel_delay(PERIPH_CLK_TO_BIT(c
), PERIPH_CLK_TO_ENB_CLR_REG(c
));
1732 void tegra30_periph_clk_reset(struct clk_hw
*hw
, bool assert)
1734 struct clk_tegra
*c
= to_clk_tegra(hw
);
1737 if (!(c
->flags
& PERIPH_NO_RESET
)) {
1739 /* If peripheral is in the APB bus then read the APB
1740 * bus to flush the write operation in apb bus. This
1741 * will avoid the peripheral access after disabling
1743 if (c
->flags
& PERIPH_ON_APB
)
1744 val
= chipid_readl();
1746 clk_writel(PERIPH_CLK_TO_BIT(c
),
1747 PERIPH_CLK_TO_RST_SET_REG(c
));
1749 clk_writel(PERIPH_CLK_TO_BIT(c
),
1750 PERIPH_CLK_TO_RST_CLR_REG(c
));
1754 static int tegra30_periph_clk_set_parent(struct clk_hw
*hw
, u8 index
)
1756 struct clk_tegra
*c
= to_clk_tegra(hw
);
1759 if (!(c
->flags
& MUX
))
1760 return (index
== 0) ? 0 : (-EINVAL
);
1762 val
= clk_readl(c
->reg
);
1763 val
&= ~periph_clk_source_mask(c
);
1764 val
|= (index
<< periph_clk_source_shift(c
));
1765 clk_writel_delay(val
, c
->reg
);
1769 static u8
tegra30_periph_clk_get_parent(struct clk_hw
*hw
)
1771 struct clk_tegra
*c
= to_clk_tegra(hw
);
1772 u32 val
= clk_readl(c
->reg
);
1773 int source
= (val
& periph_clk_source_mask(c
)) >>
1774 periph_clk_source_shift(c
);
1776 if (!(c
->flags
& MUX
))
1782 static int tegra30_periph_clk_set_rate(struct clk_hw
*hw
, unsigned long rate
,
1783 unsigned long parent_rate
)
1785 struct clk_tegra
*c
= to_clk_tegra(hw
);
1789 if (c
->flags
& DIV_U71
) {
1790 divider
= clk_div71_get_divider(
1791 parent_rate
, rate
, c
->flags
, ROUND_DIVIDER_UP
);
1793 val
= clk_readl(c
->reg
);
1794 val
&= ~PERIPH_CLK_SOURCE_DIVU71_MASK
;
1796 if (c
->flags
& DIV_U71_UART
) {
1798 val
|= PERIPH_CLK_UART_DIV_ENB
;
1800 val
&= ~PERIPH_CLK_UART_DIV_ENB
;
1802 clk_writel_delay(val
, c
->reg
);
1803 c
->div
= divider
+ 2;
1807 } else if (c
->flags
& DIV_U16
) {
1808 divider
= clk_div16_get_divider(parent_rate
, rate
);
1810 val
= clk_readl(c
->reg
);
1811 val
&= ~PERIPH_CLK_SOURCE_DIVU16_MASK
;
1813 clk_writel_delay(val
, c
->reg
);
1814 c
->div
= divider
+ 1;
1818 } else if (parent_rate
<= rate
) {
1826 static long tegra30_periph_clk_round_rate(struct clk_hw
*hw
, unsigned long rate
,
1827 unsigned long *prate
)
1829 struct clk_tegra
*c
= to_clk_tegra(hw
);
1830 unsigned long parent_rate
= __clk_get_rate(__clk_get_parent(hw
->clk
));
1834 parent_rate
= *prate
;
1836 if (c
->flags
& DIV_U71
) {
1837 divider
= clk_div71_get_divider(
1838 parent_rate
, rate
, c
->flags
, ROUND_DIVIDER_UP
);
1842 return DIV_ROUND_UP(parent_rate
* 2, divider
+ 2);
1843 } else if (c
->flags
& DIV_U16
) {
1844 divider
= clk_div16_get_divider(parent_rate
, rate
);
1847 return DIV_ROUND_UP(parent_rate
, divider
+ 1);
1852 static unsigned long tegra30_periph_clk_recalc_rate(struct clk_hw
*hw
,
1853 unsigned long parent_rate
)
1855 struct clk_tegra
*c
= to_clk_tegra(hw
);
1856 u64 rate
= parent_rate
;
1857 u32 val
= clk_readl(c
->reg
);
1859 if (c
->flags
& DIV_U71
) {
1860 u32 divu71
= val
& PERIPH_CLK_SOURCE_DIVU71_MASK
;
1861 if ((c
->flags
& DIV_U71_UART
) &&
1862 (!(val
& PERIPH_CLK_UART_DIV_ENB
))) {
1865 if (c
->flags
& DIV_U71_IDLE
) {
1866 val
&= ~(PERIPH_CLK_SOURCE_DIVU71_MASK
<<
1867 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT
);
1868 val
|= (PERIPH_CLK_SOURCE_DIVIDLE_VAL
<<
1869 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT
);
1870 clk_writel(val
, c
->reg
);
1872 c
->div
= divu71
+ 2;
1874 } else if (c
->flags
& DIV_U16
) {
1875 u32 divu16
= val
& PERIPH_CLK_SOURCE_DIVU16_MASK
;
1876 c
->div
= divu16
+ 1;
1883 if (c
->mul
!= 0 && c
->div
!= 0) {
1885 rate
+= c
->div
- 1; /* round up */
1886 do_div(rate
, c
->div
);
1891 struct clk_ops tegra30_periph_clk_ops
= {
1892 .is_enabled
= tegra30_periph_clk_is_enabled
,
1893 .enable
= tegra30_periph_clk_enable
,
1894 .disable
= tegra30_periph_clk_disable
,
1895 .set_parent
= tegra30_periph_clk_set_parent
,
1896 .get_parent
= tegra30_periph_clk_get_parent
,
1897 .set_rate
= tegra30_periph_clk_set_rate
,
1898 .round_rate
= tegra30_periph_clk_round_rate
,
1899 .recalc_rate
= tegra30_periph_clk_recalc_rate
,
1902 static int tegra30_dsib_clk_set_parent(struct clk_hw
*hw
, u8 index
)
1904 struct clk
*d
= clk_get_sys(NULL
, "pll_d");
1905 /* The DSIB parent selection bit is in PLLD base
1906 register - can not do direct r-m-w, must be
1907 protected by PLLD lock */
1909 d
, TEGRA_CLK_PLLD_MIPI_MUX_SEL
, index
);
1914 struct clk_ops tegra30_dsib_clk_ops
= {
1915 .is_enabled
= tegra30_periph_clk_is_enabled
,
1916 .enable
= &tegra30_periph_clk_enable
,
1917 .disable
= &tegra30_periph_clk_disable
,
1918 .set_parent
= &tegra30_dsib_clk_set_parent
,
1919 .get_parent
= &tegra30_periph_clk_get_parent
,
1920 .set_rate
= &tegra30_periph_clk_set_rate
,
1921 .round_rate
= &tegra30_periph_clk_round_rate
,
1922 .recalc_rate
= &tegra30_periph_clk_recalc_rate
,
1925 /* Periph extended clock configuration ops */
1926 int tegra30_vi_clk_cfg_ex(struct clk_hw
*hw
,
1927 enum tegra_clk_ex_param p
, u32 setting
)
1929 struct clk_tegra
*c
= to_clk_tegra(hw
);
1931 if (p
== TEGRA_CLK_VI_INP_SEL
) {
1932 u32 val
= clk_readl(c
->reg
);
1933 val
&= ~PERIPH_CLK_VI_SEL_EX_MASK
;
1934 val
|= (setting
<< PERIPH_CLK_VI_SEL_EX_SHIFT
) &
1935 PERIPH_CLK_VI_SEL_EX_MASK
;
1936 clk_writel(val
, c
->reg
);
1942 int tegra30_nand_clk_cfg_ex(struct clk_hw
*hw
,
1943 enum tegra_clk_ex_param p
, u32 setting
)
1945 struct clk_tegra
*c
= to_clk_tegra(hw
);
1947 if (p
== TEGRA_CLK_NAND_PAD_DIV2_ENB
) {
1948 u32 val
= clk_readl(c
->reg
);
1950 val
|= PERIPH_CLK_NAND_DIV_EX_ENB
;
1952 val
&= ~PERIPH_CLK_NAND_DIV_EX_ENB
;
1953 clk_writel(val
, c
->reg
);
1959 int tegra30_dtv_clk_cfg_ex(struct clk_hw
*hw
,
1960 enum tegra_clk_ex_param p
, u32 setting
)
1962 struct clk_tegra
*c
= to_clk_tegra(hw
);
1964 if (p
== TEGRA_CLK_DTV_INVERT
) {
1965 u32 val
= clk_readl(c
->reg
);
1967 val
|= PERIPH_CLK_DTV_POLARITY_INV
;
1969 val
&= ~PERIPH_CLK_DTV_POLARITY_INV
;
1970 clk_writel(val
, c
->reg
);
1976 /* Output clock ops */
1978 static DEFINE_SPINLOCK(clk_out_lock
);
1980 static int tegra30_clk_out_is_enabled(struct clk_hw
*hw
)
1982 struct clk_tegra
*c
= to_clk_tegra(hw
);
1983 u32 val
= pmc_readl(c
->reg
);
1985 c
->state
= (val
& (0x1 << c
->u
.periph
.clk_num
)) ? ON
: OFF
;
1991 static int tegra30_clk_out_enable(struct clk_hw
*hw
)
1993 struct clk_tegra
*c
= to_clk_tegra(hw
);
1995 unsigned long flags
;
1997 spin_lock_irqsave(&clk_out_lock
, flags
);
1998 val
= pmc_readl(c
->reg
);
1999 val
|= (0x1 << c
->u
.periph
.clk_num
);
2000 pmc_writel(val
, c
->reg
);
2001 spin_unlock_irqrestore(&clk_out_lock
, flags
);
2006 static void tegra30_clk_out_disable(struct clk_hw
*hw
)
2008 struct clk_tegra
*c
= to_clk_tegra(hw
);
2010 unsigned long flags
;
2012 spin_lock_irqsave(&clk_out_lock
, flags
);
2013 val
= pmc_readl(c
->reg
);
2014 val
&= ~(0x1 << c
->u
.periph
.clk_num
);
2015 pmc_writel(val
, c
->reg
);
2016 spin_unlock_irqrestore(&clk_out_lock
, flags
);
2019 static int tegra30_clk_out_set_parent(struct clk_hw
*hw
, u8 index
)
2021 struct clk_tegra
*c
= to_clk_tegra(hw
);
2023 unsigned long flags
;
2025 spin_lock_irqsave(&clk_out_lock
, flags
);
2026 val
= pmc_readl(c
->reg
);
2027 val
&= ~periph_clk_source_mask(c
);
2028 val
|= (index
<< periph_clk_source_shift(c
));
2029 pmc_writel(val
, c
->reg
);
2030 spin_unlock_irqrestore(&clk_out_lock
, flags
);
2035 static u8
tegra30_clk_out_get_parent(struct clk_hw
*hw
)
2037 struct clk_tegra
*c
= to_clk_tegra(hw
);
2038 u32 val
= pmc_readl(c
->reg
);
2041 source
= (val
& periph_clk_source_mask(c
)) >>
2042 periph_clk_source_shift(c
);
2046 struct clk_ops tegra_clk_out_ops
= {
2047 .is_enabled
= tegra30_clk_out_is_enabled
,
2048 .enable
= tegra30_clk_out_enable
,
2049 .disable
= tegra30_clk_out_disable
,
2050 .set_parent
= tegra30_clk_out_set_parent
,
2051 .get_parent
= tegra30_clk_out_get_parent
,
2052 .recalc_rate
= tegra30_clk_fixed_recalc_rate
,
2055 /* Clock doubler ops */
2056 static int tegra30_clk_double_is_enabled(struct clk_hw
*hw
)
2058 struct clk_tegra
*c
= to_clk_tegra(hw
);
2061 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c
)) & PERIPH_CLK_TO_BIT(c
)))
2066 static int tegra30_clk_double_set_rate(struct clk_hw
*hw
, unsigned long rate
,
2067 unsigned long parent_rate
)
2069 struct clk_tegra
*c
= to_clk_tegra(hw
);
2072 if (rate
== parent_rate
) {
2073 val
= clk_readl(c
->reg
) | (0x1 << c
->reg_shift
);
2074 clk_writel(val
, c
->reg
);
2078 } else if (rate
== 2 * parent_rate
) {
2079 val
= clk_readl(c
->reg
) & (~(0x1 << c
->reg_shift
));
2080 clk_writel(val
, c
->reg
);
2088 static unsigned long tegra30_clk_double_recalc_rate(struct clk_hw
*hw
,
2089 unsigned long parent_rate
)
2091 struct clk_tegra
*c
= to_clk_tegra(hw
);
2092 u64 rate
= parent_rate
;
2094 u32 val
= clk_readl(c
->reg
);
2095 c
->mul
= val
& (0x1 << c
->reg_shift
) ? 1 : 2;
2098 if (c
->mul
!= 0 && c
->div
!= 0) {
2100 rate
+= c
->div
- 1; /* round up */
2101 do_div(rate
, c
->div
);
2107 static long tegra30_clk_double_round_rate(struct clk_hw
*hw
, unsigned long rate
,
2108 unsigned long *prate
)
2110 unsigned long output_rate
= *prate
;
2112 do_div(output_rate
, 2);
2116 struct clk_ops tegra30_clk_double_ops
= {
2117 .is_enabled
= tegra30_clk_double_is_enabled
,
2118 .enable
= tegra30_periph_clk_enable
,
2119 .disable
= tegra30_periph_clk_disable
,
2120 .recalc_rate
= tegra30_clk_double_recalc_rate
,
2121 .round_rate
= tegra30_clk_double_round_rate
,
2122 .set_rate
= tegra30_clk_double_set_rate
,
2125 /* Audio sync clock ops */
2126 struct clk_ops tegra_sync_source_ops
= {
2127 .recalc_rate
= tegra30_clk_fixed_recalc_rate
,
2130 static int tegra30_audio_sync_clk_is_enabled(struct clk_hw
*hw
)
2132 struct clk_tegra
*c
= to_clk_tegra(hw
);
2133 u32 val
= clk_readl(c
->reg
);
2134 c
->state
= (val
& AUDIO_SYNC_DISABLE_BIT
) ? OFF
: ON
;
2138 static int tegra30_audio_sync_clk_enable(struct clk_hw
*hw
)
2140 struct clk_tegra
*c
= to_clk_tegra(hw
);
2141 u32 val
= clk_readl(c
->reg
);
2142 clk_writel((val
& (~AUDIO_SYNC_DISABLE_BIT
)), c
->reg
);
2146 static void tegra30_audio_sync_clk_disable(struct clk_hw
*hw
)
2148 struct clk_tegra
*c
= to_clk_tegra(hw
);
2149 u32 val
= clk_readl(c
->reg
);
2150 clk_writel((val
| AUDIO_SYNC_DISABLE_BIT
), c
->reg
);
2153 static int tegra30_audio_sync_clk_set_parent(struct clk_hw
*hw
, u8 index
)
2155 struct clk_tegra
*c
= to_clk_tegra(hw
);
2158 val
= clk_readl(c
->reg
);
2159 val
&= ~AUDIO_SYNC_SOURCE_MASK
;
2162 clk_writel(val
, c
->reg
);
2166 static u8
tegra30_audio_sync_clk_get_parent(struct clk_hw
*hw
)
2168 struct clk_tegra
*c
= to_clk_tegra(hw
);
2169 u32 val
= clk_readl(c
->reg
);
2172 source
= val
& AUDIO_SYNC_SOURCE_MASK
;
2176 struct clk_ops tegra30_audio_sync_clk_ops
= {
2177 .is_enabled
= tegra30_audio_sync_clk_is_enabled
,
2178 .enable
= tegra30_audio_sync_clk_enable
,
2179 .disable
= tegra30_audio_sync_clk_disable
,
2180 .set_parent
= tegra30_audio_sync_clk_set_parent
,
2181 .get_parent
= tegra30_audio_sync_clk_get_parent
,
2182 .recalc_rate
= tegra30_clk_fixed_recalc_rate
,
2185 /* cml0 (pcie), and cml1 (sata) clock ops */
2186 static int tegra30_cml_clk_is_enabled(struct clk_hw
*hw
)
2188 struct clk_tegra
*c
= to_clk_tegra(hw
);
2189 u32 val
= clk_readl(c
->reg
);
2190 c
->state
= val
& (0x1 << c
->u
.periph
.clk_num
) ? ON
: OFF
;
2194 static int tegra30_cml_clk_enable(struct clk_hw
*hw
)
2196 struct clk_tegra
*c
= to_clk_tegra(hw
);
2198 u32 val
= clk_readl(c
->reg
);
2199 val
|= (0x1 << c
->u
.periph
.clk_num
);
2200 clk_writel(val
, c
->reg
);
2205 static void tegra30_cml_clk_disable(struct clk_hw
*hw
)
2207 struct clk_tegra
*c
= to_clk_tegra(hw
);
2209 u32 val
= clk_readl(c
->reg
);
2210 val
&= ~(0x1 << c
->u
.periph
.clk_num
);
2211 clk_writel(val
, c
->reg
);
2214 struct clk_ops tegra_cml_clk_ops
= {
2215 .is_enabled
= tegra30_cml_clk_is_enabled
,
2216 .enable
= tegra30_cml_clk_enable
,
2217 .disable
= tegra30_cml_clk_disable
,
2218 .recalc_rate
= tegra30_clk_fixed_recalc_rate
,
2221 struct clk_ops tegra_pciex_clk_ops
= {
2222 .recalc_rate
= tegra30_clk_fixed_recalc_rate
,